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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 99.07 96.67 100.00 100.00 98.83 98.33 90.79


Total test records in report: 917
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T791 /workspace/coverage/default/38.adc_ctrl_poweron_counter.2878101810 Jun 21 06:54:31 PM PDT 24 Jun 21 06:54:40 PM PDT 24 3194789314 ps
T792 /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.770095861 Jun 21 06:51:32 PM PDT 24 Jun 21 06:53:04 PM PDT 24 325995473059 ps
T793 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3199302349 Jun 21 06:46:26 PM PDT 24 Jun 21 06:46:37 PM PDT 24 455529618 ps
T106 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4219698467 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:30 PM PDT 24 330445027 ps
T56 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2640441029 Jun 21 06:45:56 PM PDT 24 Jun 21 06:47:02 PM PDT 24 13037309182 ps
T794 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.497290114 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:17 PM PDT 24 441594061 ps
T59 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.50996122 Jun 21 06:46:09 PM PDT 24 Jun 21 06:46:28 PM PDT 24 365462712 ps
T795 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.405498059 Jun 21 06:46:09 PM PDT 24 Jun 21 06:46:27 PM PDT 24 415423119 ps
T111 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1744667913 Jun 21 06:45:57 PM PDT 24 Jun 21 06:46:17 PM PDT 24 764285079 ps
T94 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.529383756 Jun 21 06:45:57 PM PDT 24 Jun 21 06:46:17 PM PDT 24 499474991 ps
T57 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3012240885 Jun 21 06:46:10 PM PDT 24 Jun 21 06:46:33 PM PDT 24 4874671284 ps
T68 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2031377720 Jun 21 06:45:55 PM PDT 24 Jun 21 06:46:16 PM PDT 24 715377695 ps
T95 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1365934318 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:16 PM PDT 24 1068348328 ps
T96 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4053248216 Jun 21 06:46:00 PM PDT 24 Jun 21 06:46:20 PM PDT 24 852677771 ps
T97 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3005840239 Jun 21 06:45:57 PM PDT 24 Jun 21 06:46:16 PM PDT 24 447540712 ps
T796 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.239676766 Jun 21 06:46:26 PM PDT 24 Jun 21 06:46:36 PM PDT 24 436241770 ps
T797 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1779180971 Jun 21 06:46:19 PM PDT 24 Jun 21 06:46:34 PM PDT 24 314032911 ps
T58 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4263938381 Jun 21 06:45:47 PM PDT 24 Jun 21 06:47:07 PM PDT 24 23325045640 ps
T98 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.304935509 Jun 21 06:45:48 PM PDT 24 Jun 21 06:46:10 PM PDT 24 433547788 ps
T798 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4066511125 Jun 21 06:45:59 PM PDT 24 Jun 21 06:46:17 PM PDT 24 420230906 ps
T799 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2898547667 Jun 21 06:46:25 PM PDT 24 Jun 21 06:46:36 PM PDT 24 307852282 ps
T800 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.300601401 Jun 21 06:46:25 PM PDT 24 Jun 21 06:46:37 PM PDT 24 473041985 ps
T99 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1292918981 Jun 21 06:46:12 PM PDT 24 Jun 21 06:46:29 PM PDT 24 322487721 ps
T69 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1044997927 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:18 PM PDT 24 550735861 ps
T801 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3457884756 Jun 21 06:46:28 PM PDT 24 Jun 21 06:46:39 PM PDT 24 529911917 ps
T71 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.345754354 Jun 21 06:45:49 PM PDT 24 Jun 21 06:46:10 PM PDT 24 685565888 ps
T802 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2668280694 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:16 PM PDT 24 545541741 ps
T60 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.246639729 Jun 21 06:46:09 PM PDT 24 Jun 21 06:46:29 PM PDT 24 4730086002 ps
T61 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1845317472 Jun 21 06:46:08 PM PDT 24 Jun 21 06:46:29 PM PDT 24 4570403414 ps
T803 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2918181520 Jun 21 06:46:25 PM PDT 24 Jun 21 06:46:37 PM PDT 24 509547944 ps
T91 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2664466862 Jun 21 06:46:07 PM PDT 24 Jun 21 06:46:26 PM PDT 24 573068373 ps
T804 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3147931783 Jun 21 06:46:12 PM PDT 24 Jun 21 06:46:29 PM PDT 24 469382313 ps
T805 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4210297615 Jun 21 06:46:29 PM PDT 24 Jun 21 06:46:39 PM PDT 24 494960481 ps
T77 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3637782187 Jun 21 06:46:15 PM PDT 24 Jun 21 06:46:32 PM PDT 24 593533989 ps
T806 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.234672248 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:15 PM PDT 24 331531010 ps
T62 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.922705661 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:20 PM PDT 24 4754378571 ps
T807 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2600534225 Jun 21 06:46:28 PM PDT 24 Jun 21 06:46:38 PM PDT 24 503508149 ps
T107 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2675605928 Jun 21 06:45:55 PM PDT 24 Jun 21 06:46:17 PM PDT 24 4372705960 ps
T76 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.598402111 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:18 PM PDT 24 654509263 ps
T108 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3731419386 Jun 21 06:45:59 PM PDT 24 Jun 21 06:46:29 PM PDT 24 4932002307 ps
T70 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.593789091 Jun 21 06:46:05 PM PDT 24 Jun 21 06:46:24 PM PDT 24 1029622370 ps
T109 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2293651891 Jun 21 06:46:18 PM PDT 24 Jun 21 06:46:38 PM PDT 24 4113125315 ps
T110 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2717790555 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:19 PM PDT 24 2251530691 ps
T808 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1087303749 Jun 21 06:46:15 PM PDT 24 Jun 21 06:46:31 PM PDT 24 319323851 ps
T74 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2078245457 Jun 21 06:46:19 PM PDT 24 Jun 21 06:46:35 PM PDT 24 458682281 ps
T100 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4082804212 Jun 21 06:46:04 PM PDT 24 Jun 21 06:46:24 PM PDT 24 408995289 ps
T809 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3503813159 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:15 PM PDT 24 351025399 ps
T810 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3210679102 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:31 PM PDT 24 431649876 ps
T811 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.529381002 Jun 21 06:46:26 PM PDT 24 Jun 21 06:46:37 PM PDT 24 293698999 ps
T75 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1934665278 Jun 21 06:46:05 PM PDT 24 Jun 21 06:46:26 PM PDT 24 935972668 ps
T101 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1825392844 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:30 PM PDT 24 514260835 ps
T812 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1134241432 Jun 21 06:45:59 PM PDT 24 Jun 21 06:46:18 PM PDT 24 537541701 ps
T813 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4212559593 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:18 PM PDT 24 283155779 ps
T814 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2459176894 Jun 21 06:45:59 PM PDT 24 Jun 21 06:46:18 PM PDT 24 418330915 ps
T334 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3667467588 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:36 PM PDT 24 4266679641 ps
T815 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3244580236 Jun 21 06:45:59 PM PDT 24 Jun 21 06:46:18 PM PDT 24 518533468 ps
T816 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4041814312 Jun 21 06:45:49 PM PDT 24 Jun 21 06:46:11 PM PDT 24 355334323 ps
T332 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4036644229 Jun 21 06:45:59 PM PDT 24 Jun 21 06:46:27 PM PDT 24 7638033950 ps
T102 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.220844598 Jun 21 06:45:59 PM PDT 24 Jun 21 06:46:19 PM PDT 24 361782302 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.4258242870 Jun 21 06:46:12 PM PDT 24 Jun 21 06:46:30 PM PDT 24 413807746 ps
T818 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3076427012 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:32 PM PDT 24 412728293 ps
T819 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3925006575 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:17 PM PDT 24 597143318 ps
T820 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.951464993 Jun 21 06:46:04 PM PDT 24 Jun 21 06:46:26 PM PDT 24 4024370766 ps
T821 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.285669989 Jun 21 06:46:25 PM PDT 24 Jun 21 06:46:37 PM PDT 24 510361618 ps
T822 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3008147486 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:33 PM PDT 24 4850830939 ps
T823 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2666474331 Jun 21 06:46:06 PM PDT 24 Jun 21 06:46:28 PM PDT 24 2393399842 ps
T824 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.893250213 Jun 21 06:46:05 PM PDT 24 Jun 21 06:46:24 PM PDT 24 522221149 ps
T825 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.623471831 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:35 PM PDT 24 3833588361 ps
T826 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1197256228 Jun 21 06:46:09 PM PDT 24 Jun 21 06:46:28 PM PDT 24 535797694 ps
T827 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4104547562 Jun 21 06:46:09 PM PDT 24 Jun 21 06:46:27 PM PDT 24 367876523 ps
T78 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.107755240 Jun 21 06:46:07 PM PDT 24 Jun 21 06:46:34 PM PDT 24 3916826632 ps
T828 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3642398167 Jun 21 06:46:03 PM PDT 24 Jun 21 06:46:21 PM PDT 24 450171047 ps
T829 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2619325487 Jun 21 06:46:10 PM PDT 24 Jun 21 06:46:28 PM PDT 24 359809852 ps
T830 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3839577583 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:31 PM PDT 24 4684140594 ps
T333 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1153550106 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:33 PM PDT 24 4567984399 ps
T831 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2705488133 Jun 21 06:46:06 PM PDT 24 Jun 21 06:46:28 PM PDT 24 4335564422 ps
T832 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3328012596 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:17 PM PDT 24 1021789383 ps
T833 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3532760744 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:17 PM PDT 24 538344853 ps
T834 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3605903232 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:18 PM PDT 24 464908316 ps
T835 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2598307277 Jun 21 06:46:06 PM PDT 24 Jun 21 06:46:32 PM PDT 24 4531615646 ps
T836 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.348473536 Jun 21 06:46:08 PM PDT 24 Jun 21 06:46:27 PM PDT 24 483666420 ps
T837 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2767068080 Jun 21 06:45:49 PM PDT 24 Jun 21 06:46:10 PM PDT 24 706425370 ps
T838 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2671425225 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:32 PM PDT 24 429874261 ps
T103 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3962181394 Jun 21 06:45:48 PM PDT 24 Jun 21 06:46:11 PM PDT 24 657037199 ps
T839 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1469686503 Jun 21 06:46:26 PM PDT 24 Jun 21 06:46:37 PM PDT 24 329059509 ps
T840 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2440335138 Jun 21 06:46:08 PM PDT 24 Jun 21 06:46:30 PM PDT 24 3956483703 ps
T841 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.262868175 Jun 21 06:45:47 PM PDT 24 Jun 21 06:46:09 PM PDT 24 2517628782 ps
T104 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1348001257 Jun 21 06:45:59 PM PDT 24 Jun 21 06:47:08 PM PDT 24 28351057532 ps
T842 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3519697470 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:29 PM PDT 24 551961654 ps
T843 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3098419845 Jun 21 06:46:09 PM PDT 24 Jun 21 06:46:37 PM PDT 24 4454815512 ps
T844 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.430530965 Jun 21 06:46:00 PM PDT 24 Jun 21 06:46:20 PM PDT 24 1129240685 ps
T845 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3466288271 Jun 21 06:45:59 PM PDT 24 Jun 21 06:46:19 PM PDT 24 393536281 ps
T846 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3886871348 Jun 21 06:46:19 PM PDT 24 Jun 21 06:46:33 PM PDT 24 581096602 ps
T847 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3982160646 Jun 21 06:46:07 PM PDT 24 Jun 21 06:46:26 PM PDT 24 452837211 ps
T848 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3712920177 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:17 PM PDT 24 543836711 ps
T849 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3006169133 Jun 21 06:45:55 PM PDT 24 Jun 21 06:46:21 PM PDT 24 8486260490 ps
T105 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3271382239 Jun 21 06:45:55 PM PDT 24 Jun 21 06:46:14 PM PDT 24 385698357 ps
T850 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3746671687 Jun 21 06:46:12 PM PDT 24 Jun 21 06:46:30 PM PDT 24 494306179 ps
T851 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1890540171 Jun 21 06:46:27 PM PDT 24 Jun 21 06:46:38 PM PDT 24 541375877 ps
T852 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1979153356 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:15 PM PDT 24 281105547 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.74492653 Jun 21 06:45:48 PM PDT 24 Jun 21 06:46:10 PM PDT 24 354069102 ps
T854 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.353546820 Jun 21 06:46:04 PM PDT 24 Jun 21 06:46:26 PM PDT 24 4166899821 ps
T855 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2927330586 Jun 21 06:45:55 PM PDT 24 Jun 21 06:46:16 PM PDT 24 576256702 ps
T856 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.14834957 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:31 PM PDT 24 529904726 ps
T857 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1977669659 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:33 PM PDT 24 2289463790 ps
T858 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1251554683 Jun 21 06:46:27 PM PDT 24 Jun 21 06:46:37 PM PDT 24 411007390 ps
T859 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2976862739 Jun 21 06:46:16 PM PDT 24 Jun 21 06:46:32 PM PDT 24 507069839 ps
T860 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1556601906 Jun 21 06:46:24 PM PDT 24 Jun 21 06:46:35 PM PDT 24 500626445 ps
T861 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3192353284 Jun 21 06:46:24 PM PDT 24 Jun 21 06:46:35 PM PDT 24 446880410 ps
T862 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3594841253 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:16 PM PDT 24 423870114 ps
T863 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2130530674 Jun 21 06:46:12 PM PDT 24 Jun 21 06:46:30 PM PDT 24 2194688843 ps
T864 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3737371483 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:18 PM PDT 24 701005284 ps
T865 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3550987856 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:23 PM PDT 24 8641752725 ps
T866 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.609499005 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:15 PM PDT 24 346384066 ps
T867 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3565636182 Jun 21 06:45:57 PM PDT 24 Jun 21 06:46:18 PM PDT 24 832075076 ps
T868 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1493563766 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:31 PM PDT 24 541967761 ps
T869 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4140853220 Jun 21 06:46:00 PM PDT 24 Jun 21 06:46:21 PM PDT 24 539426312 ps
T870 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4160873260 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:31 PM PDT 24 440864423 ps
T79 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.701169029 Jun 21 06:46:00 PM PDT 24 Jun 21 06:46:26 PM PDT 24 8456514770 ps
T871 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3610501434 Jun 21 06:45:55 PM PDT 24 Jun 21 06:46:15 PM PDT 24 569578459 ps
T872 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.114153457 Jun 21 06:46:25 PM PDT 24 Jun 21 06:46:36 PM PDT 24 405070263 ps
T873 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.832388351 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:30 PM PDT 24 670050854 ps
T874 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2494369280 Jun 21 06:45:55 PM PDT 24 Jun 21 06:46:43 PM PDT 24 26219754275 ps
T875 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3154629386 Jun 21 06:46:10 PM PDT 24 Jun 21 06:46:28 PM PDT 24 337796718 ps
T876 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2465689627 Jun 21 06:46:26 PM PDT 24 Jun 21 06:46:38 PM PDT 24 312711793 ps
T877 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2958360615 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:28 PM PDT 24 4765350864 ps
T878 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2180633105 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:32 PM PDT 24 490487377 ps
T879 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2630451511 Jun 21 06:46:15 PM PDT 24 Jun 21 06:46:32 PM PDT 24 472759125 ps
T880 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.342938074 Jun 21 06:46:06 PM PDT 24 Jun 21 06:46:25 PM PDT 24 616265044 ps
T881 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1785153287 Jun 21 06:46:06 PM PDT 24 Jun 21 06:46:28 PM PDT 24 4702502270 ps
T882 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1380150940 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:29 PM PDT 24 401092500 ps
T883 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.599467997 Jun 21 06:46:15 PM PDT 24 Jun 21 06:46:31 PM PDT 24 337537901 ps
T884 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2680416470 Jun 21 06:46:05 PM PDT 24 Jun 21 06:46:25 PM PDT 24 542316049 ps
T885 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.610348758 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:49 PM PDT 24 5161426735 ps
T886 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1360520037 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:31 PM PDT 24 320813873 ps
T887 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.878332705 Jun 21 06:46:04 PM PDT 24 Jun 21 06:46:22 PM PDT 24 508901239 ps
T888 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.543417658 Jun 21 06:46:09 PM PDT 24 Jun 21 06:46:28 PM PDT 24 350063655 ps
T889 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.885676263 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:18 PM PDT 24 328256160 ps
T890 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2513954079 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:33 PM PDT 24 405595185 ps
T891 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1663757139 Jun 21 06:46:04 PM PDT 24 Jun 21 06:46:24 PM PDT 24 307322091 ps
T892 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4036259074 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:31 PM PDT 24 457430984 ps
T893 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3983761510 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:31 PM PDT 24 575896306 ps
T894 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.283138414 Jun 21 06:45:57 PM PDT 24 Jun 21 06:46:23 PM PDT 24 4947947644 ps
T895 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.755904139 Jun 21 06:46:25 PM PDT 24 Jun 21 06:46:37 PM PDT 24 418153300 ps
T896 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2376494893 Jun 21 06:45:56 PM PDT 24 Jun 21 06:46:17 PM PDT 24 1868048064 ps
T897 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1129892673 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:31 PM PDT 24 378084371 ps
T80 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2350875280 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:39 PM PDT 24 8504233159 ps
T898 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3959473661 Jun 21 06:46:25 PM PDT 24 Jun 21 06:46:37 PM PDT 24 441302459 ps
T899 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3182525281 Jun 21 06:45:57 PM PDT 24 Jun 21 06:46:24 PM PDT 24 2711381798 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1892389021 Jun 21 06:45:46 PM PDT 24 Jun 21 06:46:09 PM PDT 24 1032109486 ps
T901 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2474244778 Jun 21 06:46:15 PM PDT 24 Jun 21 06:46:32 PM PDT 24 595936542 ps
T902 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2462339728 Jun 21 06:46:00 PM PDT 24 Jun 21 06:47:14 PM PDT 24 26563457211 ps
T903 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1201848994 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:31 PM PDT 24 327284236 ps
T904 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3279143201 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:36 PM PDT 24 10459372301 ps
T905 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3731512116 Jun 21 06:46:09 PM PDT 24 Jun 21 06:46:27 PM PDT 24 542799655 ps
T906 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.667850708 Jun 21 06:46:14 PM PDT 24 Jun 21 06:46:42 PM PDT 24 8322344019 ps
T907 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1026754881 Jun 21 06:45:45 PM PDT 24 Jun 21 06:46:18 PM PDT 24 8178647403 ps
T908 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1479458955 Jun 21 06:45:57 PM PDT 24 Jun 21 06:46:31 PM PDT 24 8141790947 ps
T909 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2413882784 Jun 21 06:46:26 PM PDT 24 Jun 21 06:46:37 PM PDT 24 507215974 ps
T910 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3152297120 Jun 21 06:45:55 PM PDT 24 Jun 21 06:46:18 PM PDT 24 1237791355 ps
T911 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4271753100 Jun 21 06:45:59 PM PDT 24 Jun 21 06:46:18 PM PDT 24 560500260 ps
T912 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3909866797 Jun 21 06:46:13 PM PDT 24 Jun 21 06:46:30 PM PDT 24 487184041 ps
T913 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2983399734 Jun 21 06:46:25 PM PDT 24 Jun 21 06:46:37 PM PDT 24 516241343 ps
T914 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.466254010 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:21 PM PDT 24 4141303677 ps
T915 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1207143420 Jun 21 06:45:58 PM PDT 24 Jun 21 06:46:19 PM PDT 24 1735964582 ps
T916 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4229062145 Jun 21 06:46:05 PM PDT 24 Jun 21 06:46:24 PM PDT 24 292071365 ps
T917 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3491753456 Jun 21 06:46:06 PM PDT 24 Jun 21 06:46:24 PM PDT 24 371354116 ps

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1439393878
Short name T2
Test name
Test status
Simulation time 335591001392 ps
CPU time 219.36 seconds
Started Jun 21 06:55:22 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 210944 kb
Host smart-2fe58a52-d7ae-4fb9-a605-4cb9e4e31e0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439393878 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1439393878
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4138638895
Short name T17
Test name
Test status
Simulation time 812947611964 ps
CPU time 635.62 seconds
Started Jun 21 06:50:53 PM PDT 24
Finished Jun 21 07:01:35 PM PDT 24
Peak memory 218028 kb
Host smart-df122df7-6a9e-4777-92bd-a3a5b761f9f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138638895 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.4138638895
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.313076980
Short name T11
Test name
Test status
Simulation time 494969618545 ps
CPU time 1166.71 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 07:10:36 PM PDT 24
Peak memory 202224 kb
Host smart-878599b1-34d5-4367-87d6-8872aeaacbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313076980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.313076980
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2097719769
Short name T37
Test name
Test status
Simulation time 321291696744 ps
CPU time 268.7 seconds
Started Jun 21 06:53:12 PM PDT 24
Finished Jun 21 06:57:43 PM PDT 24
Peak memory 218436 kb
Host smart-8c869825-07ef-4c97-b46e-6ea8770948c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097719769 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2097719769
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2217951571
Short name T5
Test name
Test status
Simulation time 670610140186 ps
CPU time 981.07 seconds
Started Jun 21 06:55:14 PM PDT 24
Finished Jun 21 07:11:39 PM PDT 24
Peak memory 202220 kb
Host smart-34ba3117-7799-4a66-af59-70aa1b5844aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217951571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2217951571
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4049068381
Short name T217
Test name
Test status
Simulation time 494246319113 ps
CPU time 1236.05 seconds
Started Jun 21 06:51:42 PM PDT 24
Finished Jun 21 07:12:22 PM PDT 24
Peak memory 202320 kb
Host smart-931bf1ec-1372-4777-809a-d903797301d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049068381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4049068381
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.976957627
Short name T48
Test name
Test status
Simulation time 524034341835 ps
CPU time 253.73 seconds
Started Jun 21 06:52:55 PM PDT 24
Finished Jun 21 06:57:12 PM PDT 24
Peak memory 202244 kb
Host smart-20c84857-e831-49f9-b309-f29d7cb44991
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976957627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.976957627
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.627371525
Short name T134
Test name
Test status
Simulation time 535367990324 ps
CPU time 601.02 seconds
Started Jun 21 06:52:21 PM PDT 24
Finished Jun 21 07:02:25 PM PDT 24
Peak memory 202316 kb
Host smart-44d7cb21-0525-4221-9881-f627b3995537
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627371525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.627371525
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2859126026
Short name T7
Test name
Test status
Simulation time 319984661631 ps
CPU time 91.74 seconds
Started Jun 21 06:51:41 PM PDT 24
Finished Jun 21 06:53:17 PM PDT 24
Peak memory 202296 kb
Host smart-e1ee29eb-1986-4b0a-882f-c44d7731d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859126026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2859126026
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1534006296
Short name T225
Test name
Test status
Simulation time 512390964022 ps
CPU time 1119.97 seconds
Started Jun 21 06:52:00 PM PDT 24
Finished Jun 21 07:10:43 PM PDT 24
Peak memory 202248 kb
Host smart-8b534eea-8dc7-49c2-945d-0face3c1a574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534006296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1534006296
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2902822713
Short name T65
Test name
Test status
Simulation time 7980138209 ps
CPU time 19.64 seconds
Started Jun 21 06:51:08 PM PDT 24
Finished Jun 21 06:51:31 PM PDT 24
Peak memory 218828 kb
Host smart-960bc1ce-9ab9-4441-aff7-ecb115b836f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902822713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2902822713
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2433722764
Short name T127
Test name
Test status
Simulation time 571620308259 ps
CPU time 1315.8 seconds
Started Jun 21 06:53:13 PM PDT 24
Finished Jun 21 07:15:11 PM PDT 24
Peak memory 202224 kb
Host smart-607f0673-cfae-4300-b0d8-325703bed5bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433722764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2433722764
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2390140936
Short name T252
Test name
Test status
Simulation time 507064361770 ps
CPU time 210.3 seconds
Started Jun 21 06:53:52 PM PDT 24
Finished Jun 21 06:57:31 PM PDT 24
Peak memory 202328 kb
Host smart-5d650014-446c-442d-956a-d51dfbc03bfe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390140936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2390140936
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2784953246
Short name T151
Test name
Test status
Simulation time 351308721116 ps
CPU time 775.67 seconds
Started Jun 21 06:54:54 PM PDT 24
Finished Jun 21 07:07:52 PM PDT 24
Peak memory 202260 kb
Host smart-2936e07e-3cb8-4205-8705-b9ea0d23242b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784953246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2784953246
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3298273064
Short name T149
Test name
Test status
Simulation time 356476425152 ps
CPU time 741.72 seconds
Started Jun 21 06:55:44 PM PDT 24
Finished Jun 21 07:08:08 PM PDT 24
Peak memory 202344 kb
Host smart-b2118b3f-7a4a-43fd-b0d6-5667684b7129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298273064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3298273064
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4263938381
Short name T58
Test name
Test status
Simulation time 23325045640 ps
CPU time 60.16 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:47:07 PM PDT 24
Peak memory 201396 kb
Host smart-68dd5ef2-b6b1-4a66-851b-a35bc7e9aabd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263938381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4263938381
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.584497860
Short name T141
Test name
Test status
Simulation time 534136446592 ps
CPU time 329.83 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 06:56:30 PM PDT 24
Peak memory 202284 kb
Host smart-37e8dec9-57f7-4fb0-b418-ab5a13c461cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584497860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.584497860
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2896115705
Short name T191
Test name
Test status
Simulation time 383958923027 ps
CPU time 464.89 seconds
Started Jun 21 06:53:05 PM PDT 24
Finished Jun 21 07:00:53 PM PDT 24
Peak memory 201888 kb
Host smart-8d20fa84-baa7-4196-b58d-3ffbee128f9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896115705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2896115705
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2031377720
Short name T68
Test name
Test status
Simulation time 715377695 ps
CPU time 2.69 seconds
Started Jun 21 06:45:55 PM PDT 24
Finished Jun 21 06:46:16 PM PDT 24
Peak memory 201408 kb
Host smart-bcba4f92-3fbf-4501-97ce-59e6b549f74f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031377720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2031377720
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.762710099
Short name T23
Test name
Test status
Simulation time 323091234635 ps
CPU time 198.28 seconds
Started Jun 21 06:50:56 PM PDT 24
Finished Jun 21 06:54:20 PM PDT 24
Peak memory 202208 kb
Host smart-257860a1-d8ca-4d0b-879e-f5d07b3a1056
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=762710099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.762710099
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1853883240
Short name T175
Test name
Test status
Simulation time 394902985246 ps
CPU time 699.47 seconds
Started Jun 21 06:51:18 PM PDT 24
Finished Jun 21 07:03:01 PM PDT 24
Peak memory 210812 kb
Host smart-31206212-5dc0-45d1-9d99-c1943bc7d2d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853883240 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1853883240
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.4088897271
Short name T274
Test name
Test status
Simulation time 526616855239 ps
CPU time 237.89 seconds
Started Jun 21 06:51:45 PM PDT 24
Finished Jun 21 06:55:48 PM PDT 24
Peak memory 202240 kb
Host smart-3ea26ffc-22ca-4597-9d7a-d2430db5aa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088897271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4088897271
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1077849774
Short name T282
Test name
Test status
Simulation time 354988503381 ps
CPU time 396.65 seconds
Started Jun 21 06:55:08 PM PDT 24
Finished Jun 21 07:01:48 PM PDT 24
Peak memory 202196 kb
Host smart-1477b46a-4254-4382-92ea-637f104cde7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077849774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1077849774
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1969613829
Short name T46
Test name
Test status
Simulation time 165516708392 ps
CPU time 55.13 seconds
Started Jun 21 06:55:45 PM PDT 24
Finished Jun 21 06:56:42 PM PDT 24
Peak memory 202228 kb
Host smart-3d666d69-6454-4fd8-85e4-78e6b6357899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969613829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1969613829
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.117532634
Short name T26
Test name
Test status
Simulation time 346262359775 ps
CPU time 762.41 seconds
Started Jun 21 06:52:33 PM PDT 24
Finished Jun 21 07:05:17 PM PDT 24
Peak memory 202236 kb
Host smart-e7b528ac-f4aa-4d96-9b4b-828463a31b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117532634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.117532634
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1612843082
Short name T181
Test name
Test status
Simulation time 521818007952 ps
CPU time 309.11 seconds
Started Jun 21 06:51:25 PM PDT 24
Finished Jun 21 06:56:42 PM PDT 24
Peak memory 202224 kb
Host smart-05de2de2-a8f9-4f3b-9fa7-3651d9754298
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612843082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1612843082
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.812209126
Short name T222
Test name
Test status
Simulation time 486964344190 ps
CPU time 558.01 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 07:03:03 PM PDT 24
Peak memory 202220 kb
Host smart-89119d3d-7c97-40fe-942d-9c89ee1935e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812209126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.812209126
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1064791843
Short name T15
Test name
Test status
Simulation time 1611573646449 ps
CPU time 606.81 seconds
Started Jun 21 06:53:54 PM PDT 24
Finished Jun 21 07:04:09 PM PDT 24
Peak memory 210816 kb
Host smart-a6ddbddb-cfde-4759-9278-8272e6d6dc05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064791843 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1064791843
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1463379157
Short name T293
Test name
Test status
Simulation time 363527336469 ps
CPU time 855.12 seconds
Started Jun 21 06:51:45 PM PDT 24
Finished Jun 21 07:06:05 PM PDT 24
Peak memory 202272 kb
Host smart-943b03b8-0862-40e9-9534-bc3d3135663d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463379157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1463379157
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1171523047
Short name T72
Test name
Test status
Simulation time 295671735 ps
CPU time 1.22 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:52:25 PM PDT 24
Peak memory 201892 kb
Host smart-d9dad1cf-83f1-45a2-a106-d2fcaf4b2075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171523047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1171523047
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.687386242
Short name T6
Test name
Test status
Simulation time 162989062927 ps
CPU time 32.87 seconds
Started Jun 21 06:51:16 PM PDT 24
Finished Jun 21 06:51:51 PM PDT 24
Peak memory 202316 kb
Host smart-b50ab6c1-9911-4d55-bbb8-1ef66efa48bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687386242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.687386242
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4036644229
Short name T332
Test name
Test status
Simulation time 7638033950 ps
CPU time 10.73 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:46:27 PM PDT 24
Peak memory 201380 kb
Host smart-d49e10e9-77af-46fc-a87d-b8637da8aa06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036644229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4036644229
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1518999473
Short name T39
Test name
Test status
Simulation time 57230306579 ps
CPU time 138.19 seconds
Started Jun 21 06:51:31 PM PDT 24
Finished Jun 21 06:53:55 PM PDT 24
Peak memory 211892 kb
Host smart-87b9c00d-0017-42f8-b775-e186dd0fcdfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518999473 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1518999473
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1438894894
Short name T327
Test name
Test status
Simulation time 323427403790 ps
CPU time 203 seconds
Started Jun 21 06:53:57 PM PDT 24
Finished Jun 21 06:57:27 PM PDT 24
Peak memory 202176 kb
Host smart-5e6fa8d5-b635-476a-9563-e82a1ecffe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438894894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1438894894
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.580725534
Short name T231
Test name
Test status
Simulation time 325072186109 ps
CPU time 483.57 seconds
Started Jun 21 06:55:15 PM PDT 24
Finished Jun 21 07:03:23 PM PDT 24
Peak memory 210776 kb
Host smart-f039ddf2-1b14-4487-9dc6-bf8860c36828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580725534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
580725534
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.996968298
Short name T137
Test name
Test status
Simulation time 492542987085 ps
CPU time 1085.97 seconds
Started Jun 21 06:50:53 PM PDT 24
Finished Jun 21 07:09:05 PM PDT 24
Peak memory 202312 kb
Host smart-b461736a-9d9f-40de-9a42-fd2dcaa7016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996968298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.996968298
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1776649494
Short name T162
Test name
Test status
Simulation time 535868940744 ps
CPU time 318.79 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 06:58:14 PM PDT 24
Peak memory 202308 kb
Host smart-60f5607d-b10f-4020-af44-a970434f6239
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776649494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1776649494
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.63202080
Short name T237
Test name
Test status
Simulation time 496950681872 ps
CPU time 1182.75 seconds
Started Jun 21 06:52:43 PM PDT 24
Finished Jun 21 07:12:29 PM PDT 24
Peak memory 202356 kb
Host smart-66e09dfc-8a39-482b-8658-65d01f7252bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63202080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.63202080
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.979823571
Short name T154
Test name
Test status
Simulation time 321311265291 ps
CPU time 749.76 seconds
Started Jun 21 06:51:00 PM PDT 24
Finished Jun 21 07:03:34 PM PDT 24
Peak memory 202228 kb
Host smart-8544855d-a855-41eb-b9b2-5e436deb5efe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979823571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.979823571
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2694273469
Short name T220
Test name
Test status
Simulation time 92923749919 ps
CPU time 200.96 seconds
Started Jun 21 06:52:55 PM PDT 24
Finished Jun 21 06:56:20 PM PDT 24
Peak memory 218128 kb
Host smart-c7744391-edf3-43d1-aa41-cdc1232f6a2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694273469 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2694273469
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1771550201
Short name T218
Test name
Test status
Simulation time 330386716141 ps
CPU time 734.52 seconds
Started Jun 21 06:52:03 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 202240 kb
Host smart-6fab73b1-b4d0-44f9-b97b-431c7f2354c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771550201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1771550201
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3912433955
Short name T227
Test name
Test status
Simulation time 177178733788 ps
CPU time 413.87 seconds
Started Jun 21 06:53:22 PM PDT 24
Finished Jun 21 07:00:23 PM PDT 24
Peak memory 202180 kb
Host smart-61c0c84a-f109-4081-84a3-d92c4a52f4bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912433955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3912433955
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3326248488
Short name T273
Test name
Test status
Simulation time 188208833306 ps
CPU time 440.83 seconds
Started Jun 21 06:51:04 PM PDT 24
Finished Jun 21 06:58:28 PM PDT 24
Peak memory 202232 kb
Host smart-717d8ab6-ebc3-41ee-b374-9fdf1360ce22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326248488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3326248488
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.454666114
Short name T47
Test name
Test status
Simulation time 374227353928 ps
CPU time 795.07 seconds
Started Jun 21 06:54:00 PM PDT 24
Finished Jun 21 07:07:20 PM PDT 24
Peak memory 202216 kb
Host smart-ded81265-aa3e-46d2-9302-65708edb4029
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454666114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.454666114
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.304935509
Short name T98
Test name
Test status
Simulation time 433547788 ps
CPU time 1.81 seconds
Started Jun 21 06:45:48 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 201160 kb
Host smart-b85c298b-dcdd-4527-8cd9-281a0e7fb159
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304935509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.304935509
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2822790676
Short name T147
Test name
Test status
Simulation time 327545303267 ps
CPU time 199.88 seconds
Started Jun 21 06:51:25 PM PDT 24
Finished Jun 21 06:54:51 PM PDT 24
Peak memory 202312 kb
Host smart-8aa8bf53-52bc-445c-8291-659e86f3fc34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822790676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2822790676
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2068314526
Short name T86
Test name
Test status
Simulation time 436171145968 ps
CPU time 494.65 seconds
Started Jun 21 06:53:15 PM PDT 24
Finished Jun 21 07:01:32 PM PDT 24
Peak memory 210744 kb
Host smart-dfb6fa3c-a24f-4999-a786-c6bd64ec792b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068314526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2068314526
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.291425054
Short name T265
Test name
Test status
Simulation time 498472720557 ps
CPU time 1162.09 seconds
Started Jun 21 06:53:57 PM PDT 24
Finished Jun 21 07:13:26 PM PDT 24
Peak memory 202204 kb
Host smart-846b2860-9bfc-483b-a13c-2b31a4268271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291425054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.291425054
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2992310429
Short name T278
Test name
Test status
Simulation time 524733598451 ps
CPU time 313.89 seconds
Started Jun 21 06:54:32 PM PDT 24
Finished Jun 21 06:59:49 PM PDT 24
Peak memory 202248 kb
Host smart-b353be47-0bab-4509-a026-e63c42d399c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992310429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2992310429
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1554939457
Short name T33
Test name
Test status
Simulation time 201799126454 ps
CPU time 183.14 seconds
Started Jun 21 06:55:07 PM PDT 24
Finished Jun 21 06:58:12 PM PDT 24
Peak memory 202256 kb
Host smart-823d8e0a-2040-46bd-a800-e96bc1243427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554939457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1554939457
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3592082570
Short name T224
Test name
Test status
Simulation time 345368889294 ps
CPU time 420.7 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:59:24 PM PDT 24
Peak memory 202184 kb
Host smart-a744cce6-394e-4ac4-89ae-cc3f606f8d5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592082570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3592082570
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1849629794
Short name T41
Test name
Test status
Simulation time 154598584207 ps
CPU time 151.52 seconds
Started Jun 21 06:51:11 PM PDT 24
Finished Jun 21 06:53:45 PM PDT 24
Peak memory 210924 kb
Host smart-8ecddfe7-f50f-40de-8560-ba8e587a4274
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849629794 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1849629794
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.345754354
Short name T71
Test name
Test status
Simulation time 685565888 ps
CPU time 1.97 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 201388 kb
Host smart-ce5f5a68-91dd-4262-b78a-5d797a6e5fea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345754354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.345754354
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.182314310
Short name T369
Test name
Test status
Simulation time 600526497324 ps
CPU time 1223.13 seconds
Started Jun 21 06:50:47 PM PDT 24
Finished Jun 21 07:11:15 PM PDT 24
Peak memory 202180 kb
Host smart-4a1a0397-3087-41f2-8d90-449723c287ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182314310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.182314310
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2622017731
Short name T214
Test name
Test status
Simulation time 484885925640 ps
CPU time 1064.25 seconds
Started Jun 21 06:54:26 PM PDT 24
Finished Jun 21 07:12:12 PM PDT 24
Peak memory 202276 kb
Host smart-dee95a16-9624-42ac-8f4e-2c83c4516d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622017731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2622017731
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1559408351
Short name T159
Test name
Test status
Simulation time 505136099567 ps
CPU time 85.81 seconds
Started Jun 21 06:51:04 PM PDT 24
Finished Jun 21 06:52:33 PM PDT 24
Peak memory 202252 kb
Host smart-4d09910b-be19-4136-8280-c929f56da967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559408351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1559408351
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2604086616
Short name T241
Test name
Test status
Simulation time 502683086729 ps
CPU time 442.71 seconds
Started Jun 21 06:51:17 PM PDT 24
Finished Jun 21 06:58:43 PM PDT 24
Peak memory 202312 kb
Host smart-05595698-9743-4d0b-ad26-0286433b3c63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604086616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2604086616
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.701169029
Short name T79
Test name
Test status
Simulation time 8456514770 ps
CPU time 7.17 seconds
Started Jun 21 06:46:00 PM PDT 24
Finished Jun 21 06:46:26 PM PDT 24
Peak memory 201384 kb
Host smart-5d5daded-7a38-4825-a0d7-c26d8f1681e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701169029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.701169029
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2367426539
Short name T198
Test name
Test status
Simulation time 4241116115560 ps
CPU time 1600.89 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 07:17:41 PM PDT 24
Peak memory 210732 kb
Host smart-e6ca94b7-d000-418e-afd8-71cc35f4dc60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367426539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2367426539
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1994789374
Short name T303
Test name
Test status
Simulation time 329899339611 ps
CPU time 764.87 seconds
Started Jun 21 06:53:32 PM PDT 24
Finished Jun 21 07:06:31 PM PDT 24
Peak memory 202344 kb
Host smart-a5270cd3-7c98-4b64-b919-610c51da0b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994789374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1994789374
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3582882302
Short name T287
Test name
Test status
Simulation time 585618056596 ps
CPU time 202.58 seconds
Started Jun 21 06:53:52 PM PDT 24
Finished Jun 21 06:57:24 PM PDT 24
Peak memory 202308 kb
Host smart-51d4fbd1-9668-47a4-95ea-70673d6fa697
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582882302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3582882302
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3621240273
Short name T259
Test name
Test status
Simulation time 501998447870 ps
CPU time 257.26 seconds
Started Jun 21 06:53:54 PM PDT 24
Finished Jun 21 06:58:20 PM PDT 24
Peak memory 202192 kb
Host smart-b5a5bb52-8a77-46bd-8b56-8b408d701dbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621240273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3621240273
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2111476954
Short name T294
Test name
Test status
Simulation time 494870530142 ps
CPU time 186.62 seconds
Started Jun 21 06:52:01 PM PDT 24
Finished Jun 21 06:55:12 PM PDT 24
Peak memory 202320 kb
Host smart-52904858-b729-4399-a785-5bf8c3426908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111476954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2111476954
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2626380291
Short name T219
Test name
Test status
Simulation time 166447900546 ps
CPU time 30.48 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:52:54 PM PDT 24
Peak memory 202312 kb
Host smart-ceb2ef14-1585-4383-aae7-bc3dce589f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626380291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2626380291
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3424254659
Short name T209
Test name
Test status
Simulation time 99485385150 ps
CPU time 397.59 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 06:59:33 PM PDT 24
Peak memory 202536 kb
Host smart-2f7daadc-4b89-4f19-be2c-a3a8a8e3ec86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424254659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3424254659
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1041207772
Short name T160
Test name
Test status
Simulation time 537130534507 ps
CPU time 203.13 seconds
Started Jun 21 06:54:02 PM PDT 24
Finished Jun 21 06:57:29 PM PDT 24
Peak memory 202232 kb
Host smart-e6d0f0ed-77e8-4460-9bb1-3ef702fa66fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041207772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1041207772
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2062271187
Short name T208
Test name
Test status
Simulation time 125717598335 ps
CPU time 675.01 seconds
Started Jun 21 06:55:15 PM PDT 24
Finished Jun 21 07:06:34 PM PDT 24
Peak memory 202556 kb
Host smart-48c4fc29-311d-4f32-baa1-3f13060e41f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062271187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2062271187
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1162382248
Short name T203
Test name
Test status
Simulation time 90556736339 ps
CPU time 465.03 seconds
Started Jun 21 06:55:51 PM PDT 24
Finished Jun 21 07:03:38 PM PDT 24
Peak memory 202544 kb
Host smart-9c479a0d-f0b0-4731-a28d-b599e8f4b1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162382248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1162382248
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.4109600340
Short name T290
Test name
Test status
Simulation time 335939303382 ps
CPU time 807.2 seconds
Started Jun 21 06:51:15 PM PDT 24
Finished Jun 21 07:04:45 PM PDT 24
Peak memory 202236 kb
Host smart-32467afd-7bc0-4033-bd84-df92bd7bf982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109600340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.4109600340
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3461107989
Short name T283
Test name
Test status
Simulation time 500560902202 ps
CPU time 412.9 seconds
Started Jun 21 06:50:47 PM PDT 24
Finished Jun 21 06:57:46 PM PDT 24
Peak memory 202244 kb
Host smart-86f9b4a2-48f0-4bcb-bd31-2d6aedc4b2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461107989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3461107989
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3136360747
Short name T128
Test name
Test status
Simulation time 678252955816 ps
CPU time 370.63 seconds
Started Jun 21 06:50:46 PM PDT 24
Finished Jun 21 06:57:02 PM PDT 24
Peak memory 202288 kb
Host smart-dc3174fc-dbde-4536-9c01-bb93d3b8642f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136360747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3136360747
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4142610953
Short name T201
Test name
Test status
Simulation time 202341384792 ps
CPU time 1095.07 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 07:09:15 PM PDT 24
Peak memory 202536 kb
Host smart-91753e99-5db4-41ba-be7c-0c4d5cfe69f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142610953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4142610953
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.737305624
Short name T275
Test name
Test status
Simulation time 329613552511 ps
CPU time 200.31 seconds
Started Jun 21 06:51:41 PM PDT 24
Finished Jun 21 06:55:06 PM PDT 24
Peak memory 202228 kb
Host smart-df461bb7-29a0-42b4-8434-c043d8f461c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737305624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
737305624
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.398513297
Short name T93
Test name
Test status
Simulation time 74982379675 ps
CPU time 48.2 seconds
Started Jun 21 06:52:00 PM PDT 24
Finished Jun 21 06:52:52 PM PDT 24
Peak memory 217632 kb
Host smart-7410fbb8-d925-4fb4-a5fb-938727b9a790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398513297 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.398513297
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.549550420
Short name T210
Test name
Test status
Simulation time 124371949920 ps
CPU time 650.96 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 07:03:48 PM PDT 24
Peak memory 202560 kb
Host smart-cd31b0df-003f-4b03-9428-a0656cb48a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549550420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.549550420
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3806286559
Short name T316
Test name
Test status
Simulation time 490533697669 ps
CPU time 272.09 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 06:58:28 PM PDT 24
Peak memory 202244 kb
Host smart-319e4f63-d518-479b-8486-5b0de50de398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806286559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3806286559
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.896746695
Short name T246
Test name
Test status
Simulation time 327785898113 ps
CPU time 403.05 seconds
Started Jun 21 06:53:52 PM PDT 24
Finished Jun 21 07:00:44 PM PDT 24
Peak memory 202200 kb
Host smart-af193a75-803d-43f0-876e-daff3e5a44e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896746695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.896746695
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.104373828
Short name T298
Test name
Test status
Simulation time 169548098044 ps
CPU time 378.37 seconds
Started Jun 21 06:54:02 PM PDT 24
Finished Jun 21 07:00:24 PM PDT 24
Peak memory 202248 kb
Host smart-c9d56e4b-25ef-4114-af8d-2e55417e826e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104373828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.104373828
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3072250251
Short name T169
Test name
Test status
Simulation time 498347592086 ps
CPU time 295.32 seconds
Started Jun 21 06:54:06 PM PDT 24
Finished Jun 21 06:59:03 PM PDT 24
Peak memory 202264 kb
Host smart-c12e97e1-8729-496c-8444-a7670f56532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072250251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3072250251
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2463464554
Short name T271
Test name
Test status
Simulation time 456598464804 ps
CPU time 913.03 seconds
Started Jun 21 06:54:20 PM PDT 24
Finished Jun 21 07:09:35 PM PDT 24
Peak memory 202640 kb
Host smart-579c97d9-5519-4189-babe-cbbf10dd42fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463464554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2463464554
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2799562034
Short name T295
Test name
Test status
Simulation time 381676595181 ps
CPU time 208.44 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 06:54:37 PM PDT 24
Peak memory 202304 kb
Host smart-98b6d7e6-a4bd-4db1-9d13-4ef33ccd6953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799562034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2799562034
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1609333263
Short name T249
Test name
Test status
Simulation time 614012412535 ps
CPU time 91.62 seconds
Started Jun 21 06:54:49 PM PDT 24
Finished Jun 21 06:56:22 PM PDT 24
Peak memory 212392 kb
Host smart-95c739a6-105a-43fe-bd53-59c1390e079e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609333263 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1609333263
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2596064407
Short name T320
Test name
Test status
Simulation time 523439147954 ps
CPU time 1224.7 seconds
Started Jun 21 06:55:14 PM PDT 24
Finished Jun 21 07:15:43 PM PDT 24
Peak memory 202248 kb
Host smart-e90a45e2-5b97-4ed1-ac4b-59ba526a711e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596064407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2596064407
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4064274073
Short name T300
Test name
Test status
Simulation time 320569016124 ps
CPU time 278.47 seconds
Started Jun 21 06:55:18 PM PDT 24
Finished Jun 21 06:59:59 PM PDT 24
Peak memory 202200 kb
Host smart-d048d49f-b68e-4912-9ad4-93d8285d09ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064274073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4064274073
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3583155339
Short name T338
Test name
Test status
Simulation time 792577432988 ps
CPU time 720.56 seconds
Started Jun 21 06:51:25 PM PDT 24
Finished Jun 21 07:03:33 PM PDT 24
Peak memory 213368 kb
Host smart-98955ae0-70ff-4b8b-b8e7-1fa1f5e37c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583155339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3583155339
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3962181394
Short name T103
Test name
Test status
Simulation time 657037199 ps
CPU time 2.67 seconds
Started Jun 21 06:45:48 PM PDT 24
Finished Jun 21 06:46:11 PM PDT 24
Peak memory 201316 kb
Host smart-997d966f-6d49-47a4-869b-72c674a87503
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962181394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3962181394
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1892389021
Short name T900
Test name
Test status
Simulation time 1032109486 ps
CPU time 1.84 seconds
Started Jun 21 06:45:46 PM PDT 24
Finished Jun 21 06:46:09 PM PDT 24
Peak memory 201144 kb
Host smart-c56a67ce-ef06-4def-aad6-c48639040e57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892389021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1892389021
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2767068080
Short name T837
Test name
Test status
Simulation time 706425370 ps
CPU time 1.4 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 201220 kb
Host smart-e0dde8ee-8e0b-4f54-9bf5-cf05a7db1551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767068080 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2767068080
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.74492653
Short name T853
Test name
Test status
Simulation time 354069102 ps
CPU time 1.49 seconds
Started Jun 21 06:45:48 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 201148 kb
Host smart-d2cdd53f-6a84-4b3b-ab3f-79a5f4081c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74492653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.74492653
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.262868175
Short name T841
Test name
Test status
Simulation time 2517628782 ps
CPU time 2.21 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:46:09 PM PDT 24
Peak memory 201220 kb
Host smart-8c8d6a1b-01e5-4a6b-b397-58de8fbd4805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262868175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.262868175
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1026754881
Short name T907
Test name
Test status
Simulation time 8178647403 ps
CPU time 12.24 seconds
Started Jun 21 06:45:45 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201376 kb
Host smart-6301c352-19b6-4a0f-9bd6-e4eda4174706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026754881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1026754881
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3565636182
Short name T867
Test name
Test status
Simulation time 832075076 ps
CPU time 3.22 seconds
Started Jun 21 06:45:57 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201344 kb
Host smart-e9f0f1f5-5c4f-47d9-a5ac-ddaa81faf265
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565636182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3565636182
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2640441029
Short name T56
Test name
Test status
Simulation time 13037309182 ps
CPU time 47.88 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:47:02 PM PDT 24
Peak memory 201296 kb
Host smart-90f1f823-3c35-430a-b846-2d2b8e745dec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640441029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2640441029
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3328012596
Short name T832
Test name
Test status
Simulation time 1021789383 ps
CPU time 1.82 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201140 kb
Host smart-97d306dd-c156-4516-9e60-6bb99f82af63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328012596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3328012596
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.598402111
Short name T76
Test name
Test status
Simulation time 654509263 ps
CPU time 1.62 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201400 kb
Host smart-a3499940-989c-4a84-9091-fc4b221ecf0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598402111 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.598402111
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.529383756
Short name T94
Test name
Test status
Simulation time 499474991 ps
CPU time 1.97 seconds
Started Jun 21 06:45:57 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201152 kb
Host smart-aa49386c-1959-4131-8394-c822f454318d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529383756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.529383756
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1979153356
Short name T852
Test name
Test status
Simulation time 281105547 ps
CPU time 1.29 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:15 PM PDT 24
Peak memory 201004 kb
Host smart-f7b2b7b2-4b48-4387-b0f4-c3977cc7507e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979153356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1979153356
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2675605928
Short name T107
Test name
Test status
Simulation time 4372705960 ps
CPU time 3.61 seconds
Started Jun 21 06:45:55 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201392 kb
Host smart-27ae067c-b39a-476c-98d1-510abbefbcad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675605928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2675605928
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4041814312
Short name T816
Test name
Test status
Simulation time 355334323 ps
CPU time 2.98 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:11 PM PDT 24
Peak memory 210628 kb
Host smart-7b63f29a-f2b3-4ee0-b162-502db80d3c63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041814312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.4041814312
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3642398167
Short name T828
Test name
Test status
Simulation time 450171047 ps
CPU time 1.08 seconds
Started Jun 21 06:46:03 PM PDT 24
Finished Jun 21 06:46:21 PM PDT 24
Peak memory 201172 kb
Host smart-efb4939b-5d63-4088-9afd-7d1df43b7dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642398167 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3642398167
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4082804212
Short name T100
Test name
Test status
Simulation time 408995289 ps
CPU time 1.21 seconds
Started Jun 21 06:46:04 PM PDT 24
Finished Jun 21 06:46:24 PM PDT 24
Peak memory 201156 kb
Host smart-6fa60abe-5ea1-440a-b911-f0834791a816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082804212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.4082804212
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.405498059
Short name T795
Test name
Test status
Simulation time 415423119 ps
CPU time 1.47 seconds
Started Jun 21 06:46:09 PM PDT 24
Finished Jun 21 06:46:27 PM PDT 24
Peak memory 201140 kb
Host smart-7ab8b3af-2056-4463-bcc5-ddbf0983bedb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405498059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.405498059
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.951464993
Short name T820
Test name
Test status
Simulation time 4024370766 ps
CPU time 4.86 seconds
Started Jun 21 06:46:04 PM PDT 24
Finished Jun 21 06:46:26 PM PDT 24
Peak memory 201444 kb
Host smart-e3079db7-4a9b-48a7-892b-17d4d6ab65fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951464993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.951464993
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1934665278
Short name T75
Test name
Test status
Simulation time 935972668 ps
CPU time 2.93 seconds
Started Jun 21 06:46:05 PM PDT 24
Finished Jun 21 06:46:26 PM PDT 24
Peak memory 210608 kb
Host smart-554eb6d2-92a7-4f3e-bb02-e4dd0eaa7eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934665278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1934665278
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.107755240
Short name T78
Test name
Test status
Simulation time 3916826632 ps
CPU time 9.62 seconds
Started Jun 21 06:46:07 PM PDT 24
Finished Jun 21 06:46:34 PM PDT 24
Peak memory 201400 kb
Host smart-d9992787-b529-4fb7-af3f-d6dd35d05d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107755240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.107755240
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4104547562
Short name T827
Test name
Test status
Simulation time 367876523 ps
CPU time 1.74 seconds
Started Jun 21 06:46:09 PM PDT 24
Finished Jun 21 06:46:27 PM PDT 24
Peak memory 201152 kb
Host smart-44d0f6b1-6afc-49da-96d7-330733005e53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104547562 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.4104547562
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.878332705
Short name T887
Test name
Test status
Simulation time 508901239 ps
CPU time 1.19 seconds
Started Jun 21 06:46:04 PM PDT 24
Finished Jun 21 06:46:22 PM PDT 24
Peak memory 201064 kb
Host smart-ce9621ce-8537-4b1b-8285-3b3c714db81f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878332705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.878332705
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3491753456
Short name T917
Test name
Test status
Simulation time 371354116 ps
CPU time 0.85 seconds
Started Jun 21 06:46:06 PM PDT 24
Finished Jun 21 06:46:24 PM PDT 24
Peak memory 201200 kb
Host smart-402bc65c-277e-4249-ada3-6bf04cf80292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491753456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3491753456
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2440335138
Short name T840
Test name
Test status
Simulation time 3956483703 ps
CPU time 5.45 seconds
Started Jun 21 06:46:08 PM PDT 24
Finished Jun 21 06:46:30 PM PDT 24
Peak memory 201444 kb
Host smart-bf17fccc-b214-4814-b246-1c91694f0208
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440335138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2440335138
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1663757139
Short name T891
Test name
Test status
Simulation time 307322091 ps
CPU time 2.52 seconds
Started Jun 21 06:46:04 PM PDT 24
Finished Jun 21 06:46:24 PM PDT 24
Peak memory 210604 kb
Host smart-09541c01-ecd6-4582-93ef-0f35f512443a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663757139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1663757139
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2705488133
Short name T831
Test name
Test status
Simulation time 4335564422 ps
CPU time 4.26 seconds
Started Jun 21 06:46:06 PM PDT 24
Finished Jun 21 06:46:28 PM PDT 24
Peak memory 201380 kb
Host smart-975a1368-d7b1-4086-a63a-fcbf808eb0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705488133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2705488133
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3982160646
Short name T847
Test name
Test status
Simulation time 452837211 ps
CPU time 1.77 seconds
Started Jun 21 06:46:07 PM PDT 24
Finished Jun 21 06:46:26 PM PDT 24
Peak memory 201216 kb
Host smart-70f9ceeb-4467-4b3e-ac94-b222275af807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982160646 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3982160646
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3731512116
Short name T905
Test name
Test status
Simulation time 542799655 ps
CPU time 1.4 seconds
Started Jun 21 06:46:09 PM PDT 24
Finished Jun 21 06:46:27 PM PDT 24
Peak memory 201164 kb
Host smart-717461cd-a84c-46e0-8a08-2c99c61befad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731512116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3731512116
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4229062145
Short name T916
Test name
Test status
Simulation time 292071365 ps
CPU time 0.94 seconds
Started Jun 21 06:46:05 PM PDT 24
Finished Jun 21 06:46:24 PM PDT 24
Peak memory 201132 kb
Host smart-1a2b6b27-a629-48d0-839a-11e22b32a6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229062145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.4229062145
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.353546820
Short name T854
Test name
Test status
Simulation time 4166899821 ps
CPU time 4.42 seconds
Started Jun 21 06:46:04 PM PDT 24
Finished Jun 21 06:46:26 PM PDT 24
Peak memory 201404 kb
Host smart-85ecc225-e42d-46f9-9635-10872fa02801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353546820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.353546820
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.893250213
Short name T824
Test name
Test status
Simulation time 522221149 ps
CPU time 1.73 seconds
Started Jun 21 06:46:05 PM PDT 24
Finished Jun 21 06:46:24 PM PDT 24
Peak memory 201440 kb
Host smart-c25e2dce-e818-4238-89e7-6fcffaef5cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893250213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.893250213
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1845317472
Short name T61
Test name
Test status
Simulation time 4570403414 ps
CPU time 4.17 seconds
Started Jun 21 06:46:08 PM PDT 24
Finished Jun 21 06:46:29 PM PDT 24
Peak memory 201428 kb
Host smart-4953a195-1532-4acf-8bf0-a26d3cdffd68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845317472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1845317472
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3886871348
Short name T846
Test name
Test status
Simulation time 581096602 ps
CPU time 1.12 seconds
Started Jun 21 06:46:19 PM PDT 24
Finished Jun 21 06:46:33 PM PDT 24
Peak memory 201232 kb
Host smart-ea118356-090f-4471-8cb2-d6838b859b19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886871348 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3886871348
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4219698467
Short name T106
Test name
Test status
Simulation time 330445027 ps
CPU time 1.51 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:30 PM PDT 24
Peak memory 201128 kb
Host smart-252468c0-108e-4bc5-9a7f-5c8ed122dd0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219698467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4219698467
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3519697470
Short name T842
Test name
Test status
Simulation time 551961654 ps
CPU time 0.69 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:29 PM PDT 24
Peak memory 201128 kb
Host smart-4d0d1e89-719c-4866-a19a-738dcd91b605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519697470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3519697470
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2130530674
Short name T863
Test name
Test status
Simulation time 2194688843 ps
CPU time 2.06 seconds
Started Jun 21 06:46:12 PM PDT 24
Finished Jun 21 06:46:30 PM PDT 24
Peak memory 201168 kb
Host smart-a0d8c041-462f-40bf-9219-66df2451d9ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130530674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2130530674
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2671425225
Short name T838
Test name
Test status
Simulation time 429874261 ps
CPU time 2.14 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:32 PM PDT 24
Peak memory 201380 kb
Host smart-153bceb7-2977-441d-9ebb-c2c4fd3aabf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671425225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2671425225
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1153550106
Short name T333
Test name
Test status
Simulation time 4567984399 ps
CPU time 3.93 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:33 PM PDT 24
Peak memory 201384 kb
Host smart-b6ae4f7d-f3f9-4241-bdeb-8c6d4ca28fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153550106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1153550106
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.543417658
Short name T888
Test name
Test status
Simulation time 350063655 ps
CPU time 1.33 seconds
Started Jun 21 06:46:09 PM PDT 24
Finished Jun 21 06:46:28 PM PDT 24
Peak memory 201232 kb
Host smart-b84a5ef7-f354-43b3-9355-27f30bb4cc6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543417658 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.543417658
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.4258242870
Short name T817
Test name
Test status
Simulation time 413807746 ps
CPU time 1.76 seconds
Started Jun 21 06:46:12 PM PDT 24
Finished Jun 21 06:46:30 PM PDT 24
Peak memory 201112 kb
Host smart-250aa989-4ebb-4220-9f58-05ed83d79e31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258242870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.4258242870
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3746671687
Short name T850
Test name
Test status
Simulation time 494306179 ps
CPU time 1.69 seconds
Started Jun 21 06:46:12 PM PDT 24
Finished Jun 21 06:46:30 PM PDT 24
Peak memory 201140 kb
Host smart-45a019dc-cb20-4897-9e95-0865119c764b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746671687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3746671687
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3012240885
Short name T57
Test name
Test status
Simulation time 4874671284 ps
CPU time 6.3 seconds
Started Jun 21 06:46:10 PM PDT 24
Finished Jun 21 06:46:33 PM PDT 24
Peak memory 201456 kb
Host smart-256ae448-f83b-42bb-8316-5cbc21d76d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012240885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3012240885
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3076427012
Short name T818
Test name
Test status
Simulation time 412728293 ps
CPU time 3.23 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:32 PM PDT 24
Peak memory 201444 kb
Host smart-650a0c4e-d400-4b6e-ae09-292383f5ce45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076427012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3076427012
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.246639729
Short name T60
Test name
Test status
Simulation time 4730086002 ps
CPU time 3.34 seconds
Started Jun 21 06:46:09 PM PDT 24
Finished Jun 21 06:46:29 PM PDT 24
Peak memory 201288 kb
Host smart-2e74d535-8efd-4331-9d74-0f80f1af7e36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246639729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.246639729
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1197256228
Short name T826
Test name
Test status
Simulation time 535797694 ps
CPU time 2.03 seconds
Started Jun 21 06:46:09 PM PDT 24
Finished Jun 21 06:46:28 PM PDT 24
Peak memory 201220 kb
Host smart-02c267ff-a5f0-4952-ae7b-02a6a81cbc9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197256228 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1197256228
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.50996122
Short name T59
Test name
Test status
Simulation time 365462712 ps
CPU time 1.68 seconds
Started Jun 21 06:46:09 PM PDT 24
Finished Jun 21 06:46:28 PM PDT 24
Peak memory 201152 kb
Host smart-8ce685ff-71b6-4731-81ff-4f4b50be6ab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50996122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.50996122
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2619325487
Short name T829
Test name
Test status
Simulation time 359809852 ps
CPU time 1.38 seconds
Started Jun 21 06:46:10 PM PDT 24
Finished Jun 21 06:46:28 PM PDT 24
Peak memory 201104 kb
Host smart-5767f410-db41-4b7c-92e2-99e3fd645f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619325487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2619325487
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2293651891
Short name T109
Test name
Test status
Simulation time 4113125315 ps
CPU time 5.42 seconds
Started Jun 21 06:46:18 PM PDT 24
Finished Jun 21 06:46:38 PM PDT 24
Peak memory 201424 kb
Host smart-0668d16e-e3c7-4415-a838-8e98d2d4421a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293651891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2293651891
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3983761510
Short name T893
Test name
Test status
Simulation time 575896306 ps
CPU time 2.44 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201404 kb
Host smart-a57048ab-0672-4b08-956b-d4dd3a8cbbf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983761510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3983761510
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3279143201
Short name T904
Test name
Test status
Simulation time 10459372301 ps
CPU time 7.8 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:36 PM PDT 24
Peak memory 201432 kb
Host smart-ac5609dc-7448-4048-bfea-3551f48db00d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279143201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3279143201
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2976862739
Short name T859
Test name
Test status
Simulation time 507069839 ps
CPU time 1.23 seconds
Started Jun 21 06:46:16 PM PDT 24
Finished Jun 21 06:46:32 PM PDT 24
Peak memory 201220 kb
Host smart-303a4f78-fa89-4d39-a479-ebdbfcbf6d38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976862739 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2976862739
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1292918981
Short name T99
Test name
Test status
Simulation time 322487721 ps
CPU time 1.26 seconds
Started Jun 21 06:46:12 PM PDT 24
Finished Jun 21 06:46:29 PM PDT 24
Peak memory 201164 kb
Host smart-ead3e87d-bf41-4afb-ad65-8a82f2c23f64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292918981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1292918981
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1779180971
Short name T797
Test name
Test status
Simulation time 314032911 ps
CPU time 1.26 seconds
Started Jun 21 06:46:19 PM PDT 24
Finished Jun 21 06:46:34 PM PDT 24
Peak memory 201152 kb
Host smart-6fb96232-db2a-4cb8-bae4-18b0047c3de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779180971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1779180971
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1977669659
Short name T857
Test name
Test status
Simulation time 2289463790 ps
CPU time 3.48 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:33 PM PDT 24
Peak memory 201208 kb
Host smart-9fb3a4de-d1d5-4a34-bd8c-61849cbb9465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977669659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1977669659
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2078245457
Short name T74
Test name
Test status
Simulation time 458682281 ps
CPU time 2.36 seconds
Started Jun 21 06:46:19 PM PDT 24
Finished Jun 21 06:46:35 PM PDT 24
Peak memory 201464 kb
Host smart-e96682a2-1c7c-4c73-b624-6016024b7df8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078245457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2078245457
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3098419845
Short name T843
Test name
Test status
Simulation time 4454815512 ps
CPU time 11.32 seconds
Started Jun 21 06:46:09 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201508 kb
Host smart-8c930f43-84a1-4c3a-affb-6ef867ef419f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098419845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3098419845
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3637782187
Short name T77
Test name
Test status
Simulation time 593533989 ps
CPU time 1.09 seconds
Started Jun 21 06:46:15 PM PDT 24
Finished Jun 21 06:46:32 PM PDT 24
Peak memory 201216 kb
Host smart-df24462b-7bc1-4190-b0f4-4128c0fc9003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637782187 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3637782187
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3154629386
Short name T875
Test name
Test status
Simulation time 337796718 ps
CPU time 1.23 seconds
Started Jun 21 06:46:10 PM PDT 24
Finished Jun 21 06:46:28 PM PDT 24
Peak memory 201156 kb
Host smart-213be19b-0b56-4afa-86e5-b6bf87dd7912
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154629386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3154629386
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1201848994
Short name T903
Test name
Test status
Simulation time 327284236 ps
CPU time 1.35 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201136 kb
Host smart-591e5c26-d245-41ef-b79f-873896a9425c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201848994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1201848994
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.610348758
Short name T885
Test name
Test status
Simulation time 5161426735 ps
CPU time 19.69 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:49 PM PDT 24
Peak memory 201456 kb
Host smart-9a5dce8b-33b8-4de4-9c94-6ec0471a430f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610348758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.610348758
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.832388351
Short name T873
Test name
Test status
Simulation time 670050854 ps
CPU time 1.67 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:30 PM PDT 24
Peak memory 201440 kb
Host smart-1b3395a8-8e3f-493d-ba9a-df9e376ac252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832388351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.832388351
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3839577583
Short name T830
Test name
Test status
Simulation time 4684140594 ps
CPU time 2.46 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201452 kb
Host smart-8d840983-5d20-4ce4-9365-51fab40f3074
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839577583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3839577583
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2474244778
Short name T901
Test name
Test status
Simulation time 595936542 ps
CPU time 1.55 seconds
Started Jun 21 06:46:15 PM PDT 24
Finished Jun 21 06:46:32 PM PDT 24
Peak memory 201248 kb
Host smart-2e2a26a6-6bdd-411a-be88-fc9816b29b6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474244778 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2474244778
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1825392844
Short name T101
Test name
Test status
Simulation time 514260835 ps
CPU time 1.99 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:30 PM PDT 24
Peak memory 201152 kb
Host smart-64467099-e912-4408-8d65-24f36c340607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825392844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1825392844
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1129892673
Short name T897
Test name
Test status
Simulation time 378084371 ps
CPU time 1.5 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201100 kb
Host smart-b2451f02-844a-4063-9930-ebd2e5d06735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129892673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1129892673
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3008147486
Short name T822
Test name
Test status
Simulation time 4850830939 ps
CPU time 3.58 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:33 PM PDT 24
Peak memory 201360 kb
Host smart-649acc8f-3b67-4280-ae31-72cba84d1118
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008147486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3008147486
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2513954079
Short name T890
Test name
Test status
Simulation time 405595185 ps
CPU time 2.85 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:33 PM PDT 24
Peak memory 209608 kb
Host smart-7bf70d1f-7598-49c6-b5c7-7aeb875bb152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513954079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2513954079
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.667850708
Short name T906
Test name
Test status
Simulation time 8322344019 ps
CPU time 12.18 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:42 PM PDT 24
Peak memory 201448 kb
Host smart-2fa1c5b5-bc0f-45d5-a947-6e40c4d6fd75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667850708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.667850708
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4036259074
Short name T892
Test name
Test status
Simulation time 457430984 ps
CPU time 1.23 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201236 kb
Host smart-ef638213-1580-4745-bd29-3665ad19b6cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036259074 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.4036259074
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1380150940
Short name T882
Test name
Test status
Simulation time 401092500 ps
CPU time 0.97 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:29 PM PDT 24
Peak memory 201148 kb
Host smart-af243039-4dc4-4b27-9cb0-8d8b3fb24efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380150940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1380150940
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3909866797
Short name T912
Test name
Test status
Simulation time 487184041 ps
CPU time 1.74 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:30 PM PDT 24
Peak memory 201112 kb
Host smart-7d189891-7bb0-4617-885f-e67f4a79958f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909866797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3909866797
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.623471831
Short name T825
Test name
Test status
Simulation time 3833588361 ps
CPU time 5.13 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:35 PM PDT 24
Peak memory 201416 kb
Host smart-8da8e8bc-5851-4d22-bee1-ae31cf4665c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623471831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.623471831
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4160873260
Short name T870
Test name
Test status
Simulation time 440864423 ps
CPU time 2.34 seconds
Started Jun 21 06:46:13 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201508 kb
Host smart-32c3c7a7-f36c-4a31-ada2-c8ebe6b022ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160873260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4160873260
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3667467588
Short name T334
Test name
Test status
Simulation time 4266679641 ps
CPU time 5.98 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:36 PM PDT 24
Peak memory 201356 kb
Host smart-83d44669-a0fe-4b6b-876d-0d4c1eb8acb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667467588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3667467588
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3152297120
Short name T910
Test name
Test status
Simulation time 1237791355 ps
CPU time 5.68 seconds
Started Jun 21 06:45:55 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201344 kb
Host smart-ff72e3dd-cdee-4dd4-9f46-f087a533adfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152297120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3152297120
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2494369280
Short name T874
Test name
Test status
Simulation time 26219754275 ps
CPU time 29.35 seconds
Started Jun 21 06:45:55 PM PDT 24
Finished Jun 21 06:46:43 PM PDT 24
Peak memory 201432 kb
Host smart-98d29d07-f492-4a91-b02a-1b9386c98f80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494369280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2494369280
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4053248216
Short name T96
Test name
Test status
Simulation time 852677771 ps
CPU time 1.58 seconds
Started Jun 21 06:46:00 PM PDT 24
Finished Jun 21 06:46:20 PM PDT 24
Peak memory 201144 kb
Host smart-5c3b6ab6-cc88-4b8a-88c6-9edf3c33836b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053248216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.4053248216
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.342938074
Short name T880
Test name
Test status
Simulation time 616265044 ps
CPU time 1.08 seconds
Started Jun 21 06:46:06 PM PDT 24
Finished Jun 21 06:46:25 PM PDT 24
Peak memory 201216 kb
Host smart-2b912a8c-2360-48c1-94a7-b5d693bd1633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342938074 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.342938074
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3005840239
Short name T97
Test name
Test status
Simulation time 447540712 ps
CPU time 1.3 seconds
Started Jun 21 06:45:57 PM PDT 24
Finished Jun 21 06:46:16 PM PDT 24
Peak memory 201184 kb
Host smart-7a50b690-6c4a-4ab4-834f-e63d3fb7e607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005840239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3005840239
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3466288271
Short name T845
Test name
Test status
Simulation time 393536281 ps
CPU time 0.91 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:46:19 PM PDT 24
Peak memory 201140 kb
Host smart-03d50898-bd65-4371-82c1-066d927bcbca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466288271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3466288271
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2717790555
Short name T110
Test name
Test status
Simulation time 2251530691 ps
CPU time 2.17 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:19 PM PDT 24
Peak memory 201212 kb
Host smart-5e5f21db-1987-4ec0-9883-5dafb84da30d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717790555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2717790555
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1479458955
Short name T908
Test name
Test status
Simulation time 8141790947 ps
CPU time 16.33 seconds
Started Jun 21 06:45:57 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201448 kb
Host smart-34debd7d-ccf9-40c7-b7fc-9322c0d5a070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479458955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1479458955
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1087303749
Short name T808
Test name
Test status
Simulation time 319323851 ps
CPU time 0.85 seconds
Started Jun 21 06:46:15 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201200 kb
Host smart-45d61262-ac6d-4564-83c7-0ae77ce10066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087303749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1087303749
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1493563766
Short name T868
Test name
Test status
Simulation time 541967761 ps
CPU time 0.96 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201128 kb
Host smart-2f7d3dfe-424d-4e69-8076-553eb5873a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493563766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1493563766
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3210679102
Short name T810
Test name
Test status
Simulation time 431649876 ps
CPU time 0.9 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201184 kb
Host smart-996e5d28-0dbd-4099-bc74-d42d2d6896ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210679102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3210679102
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.14834957
Short name T856
Test name
Test status
Simulation time 529904726 ps
CPU time 0.92 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201052 kb
Host smart-4edd317c-cb00-487a-b141-86f9adf144f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14834957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.14834957
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2180633105
Short name T878
Test name
Test status
Simulation time 490487377 ps
CPU time 1.72 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:32 PM PDT 24
Peak memory 201160 kb
Host smart-ac72e2e0-d282-4ade-8b77-75a86a98d3e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180633105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2180633105
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.599467997
Short name T883
Test name
Test status
Simulation time 337537901 ps
CPU time 1.02 seconds
Started Jun 21 06:46:15 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201140 kb
Host smart-21781822-c77e-4382-84c4-438112ccfb6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599467997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.599467997
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1360520037
Short name T886
Test name
Test status
Simulation time 320813873 ps
CPU time 0.84 seconds
Started Jun 21 06:46:14 PM PDT 24
Finished Jun 21 06:46:31 PM PDT 24
Peak memory 201132 kb
Host smart-68972bf4-c687-49d5-a35e-646ccec56729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360520037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1360520037
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3147931783
Short name T804
Test name
Test status
Simulation time 469382313 ps
CPU time 0.76 seconds
Started Jun 21 06:46:12 PM PDT 24
Finished Jun 21 06:46:29 PM PDT 24
Peak memory 201120 kb
Host smart-03075d6a-6ec0-408f-9c29-e7cc8e855cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147931783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3147931783
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2630451511
Short name T879
Test name
Test status
Simulation time 472759125 ps
CPU time 0.97 seconds
Started Jun 21 06:46:15 PM PDT 24
Finished Jun 21 06:46:32 PM PDT 24
Peak memory 201140 kb
Host smart-decb9415-b20b-4551-a6c3-bc4b1d119026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630451511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2630451511
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3457884756
Short name T801
Test name
Test status
Simulation time 529911917 ps
CPU time 1.28 seconds
Started Jun 21 06:46:28 PM PDT 24
Finished Jun 21 06:46:39 PM PDT 24
Peak memory 201112 kb
Host smart-64d21909-a729-4d76-b411-5484f0cedc42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457884756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3457884756
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2376494893
Short name T896
Test name
Test status
Simulation time 1868048064 ps
CPU time 2.74 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201352 kb
Host smart-1d4157ff-4f27-4f2c-b667-125d943026dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376494893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2376494893
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1348001257
Short name T104
Test name
Test status
Simulation time 28351057532 ps
CPU time 49.84 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:47:08 PM PDT 24
Peak memory 201376 kb
Host smart-05ff8138-fb39-48ec-8c94-91c43e29fc2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348001257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1348001257
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1365934318
Short name T95
Test name
Test status
Simulation time 1068348328 ps
CPU time 0.86 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:16 PM PDT 24
Peak memory 201144 kb
Host smart-154a6959-63f5-4e19-9c31-b0c71a7dccea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365934318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1365934318
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3925006575
Short name T819
Test name
Test status
Simulation time 597143318 ps
CPU time 0.91 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201216 kb
Host smart-ae25fec9-3f41-4d7d-a435-39fe3c55569d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925006575 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3925006575
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3271382239
Short name T105
Test name
Test status
Simulation time 385698357 ps
CPU time 1.55 seconds
Started Jun 21 06:45:55 PM PDT 24
Finished Jun 21 06:46:14 PM PDT 24
Peak memory 201148 kb
Host smart-3a7d0cb4-de53-4c9b-abdc-54d66972e0c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271382239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3271382239
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4066511125
Short name T798
Test name
Test status
Simulation time 420230906 ps
CPU time 0.89 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201136 kb
Host smart-9b7537a7-2b69-4c84-843f-5dcd881db987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066511125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4066511125
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1207143420
Short name T915
Test name
Test status
Simulation time 1735964582 ps
CPU time 3.91 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:19 PM PDT 24
Peak memory 201184 kb
Host smart-22cfef38-2b93-4448-a196-58253fe36f38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207143420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1207143420
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4271753100
Short name T911
Test name
Test status
Simulation time 560500260 ps
CPU time 1.9 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201412 kb
Host smart-f9140449-10fa-4a4c-a5c0-45f03b950ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271753100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4271753100
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3006169133
Short name T849
Test name
Test status
Simulation time 8486260490 ps
CPU time 7.59 seconds
Started Jun 21 06:45:55 PM PDT 24
Finished Jun 21 06:46:21 PM PDT 24
Peak memory 201456 kb
Host smart-dac6e1d6-5125-4bb7-9a21-1f3908078145
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006169133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3006169133
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2600534225
Short name T807
Test name
Test status
Simulation time 503508149 ps
CPU time 0.92 seconds
Started Jun 21 06:46:28 PM PDT 24
Finished Jun 21 06:46:38 PM PDT 24
Peak memory 201148 kb
Host smart-41f9a9ba-e0a7-44b5-830a-6973999c61c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600534225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2600534225
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.755904139
Short name T895
Test name
Test status
Simulation time 418153300 ps
CPU time 1.56 seconds
Started Jun 21 06:46:25 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201152 kb
Host smart-d6f0d30b-e5a7-4426-8421-4946f346957b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755904139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.755904139
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.239676766
Short name T796
Test name
Test status
Simulation time 436241770 ps
CPU time 0.85 seconds
Started Jun 21 06:46:26 PM PDT 24
Finished Jun 21 06:46:36 PM PDT 24
Peak memory 201140 kb
Host smart-b9ef2aa5-43c5-4460-a839-f69d0635f41a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239676766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.239676766
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3959473661
Short name T898
Test name
Test status
Simulation time 441302459 ps
CPU time 1.62 seconds
Started Jun 21 06:46:25 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201128 kb
Host smart-04e74eda-af86-4991-86eb-fb36e2c0fd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959473661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3959473661
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1469686503
Short name T839
Test name
Test status
Simulation time 329059509 ps
CPU time 1.32 seconds
Started Jun 21 06:46:26 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201200 kb
Host smart-e55da4d5-76b2-424a-ae3c-026df6c9c671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469686503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1469686503
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.300601401
Short name T800
Test name
Test status
Simulation time 473041985 ps
CPU time 1.5 seconds
Started Jun 21 06:46:25 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201136 kb
Host smart-86e4dcde-0bdf-48ec-8b8e-f92b7819c076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300601401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.300601401
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3192353284
Short name T861
Test name
Test status
Simulation time 446880410 ps
CPU time 0.9 seconds
Started Jun 21 06:46:24 PM PDT 24
Finished Jun 21 06:46:35 PM PDT 24
Peak memory 201140 kb
Host smart-8efba925-fc81-4394-b77e-0fa1e3562a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192353284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3192353284
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.114153457
Short name T872
Test name
Test status
Simulation time 405070263 ps
CPU time 0.99 seconds
Started Jun 21 06:46:25 PM PDT 24
Finished Jun 21 06:46:36 PM PDT 24
Peak memory 201148 kb
Host smart-7a09dc40-0c51-44db-89be-bafb22a2c762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114153457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.114153457
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1556601906
Short name T860
Test name
Test status
Simulation time 500626445 ps
CPU time 0.78 seconds
Started Jun 21 06:46:24 PM PDT 24
Finished Jun 21 06:46:35 PM PDT 24
Peak memory 201136 kb
Host smart-275f32d1-836a-4750-a801-541efd80833d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556601906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1556601906
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1890540171
Short name T851
Test name
Test status
Simulation time 541375877 ps
CPU time 0.73 seconds
Started Jun 21 06:46:27 PM PDT 24
Finished Jun 21 06:46:38 PM PDT 24
Peak memory 201100 kb
Host smart-5b622136-e400-4971-8e3c-26bd02fe9020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890540171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1890540171
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4140853220
Short name T869
Test name
Test status
Simulation time 539426312 ps
CPU time 2.89 seconds
Started Jun 21 06:46:00 PM PDT 24
Finished Jun 21 06:46:21 PM PDT 24
Peak memory 201352 kb
Host smart-fcf62374-98d1-4c65-b2be-c9167202a83a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140853220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.4140853220
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2462339728
Short name T902
Test name
Test status
Simulation time 26563457211 ps
CPU time 55.16 seconds
Started Jun 21 06:46:00 PM PDT 24
Finished Jun 21 06:47:14 PM PDT 24
Peak memory 201416 kb
Host smart-aafa2a1d-379d-47b8-8608-cc1db16f7da9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462339728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2462339728
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1744667913
Short name T111
Test name
Test status
Simulation time 764285079 ps
CPU time 1.56 seconds
Started Jun 21 06:45:57 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201148 kb
Host smart-82585b97-6cd1-4a4c-8068-4f4cb3ee51f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744667913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1744667913
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3244580236
Short name T815
Test name
Test status
Simulation time 518533468 ps
CPU time 2.09 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201220 kb
Host smart-4fffa038-359b-4f4f-837d-171d442e8dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244580236 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3244580236
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3503813159
Short name T809
Test name
Test status
Simulation time 351025399 ps
CPU time 1.48 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:15 PM PDT 24
Peak memory 201152 kb
Host smart-c437e555-d048-4be7-86ee-817311bd8605
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503813159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3503813159
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.497290114
Short name T794
Test name
Test status
Simulation time 441594061 ps
CPU time 1.23 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201140 kb
Host smart-c8a1666d-e1c7-427b-92f8-f1546a82e9ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497290114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.497290114
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.283138414
Short name T894
Test name
Test status
Simulation time 4947947644 ps
CPU time 7.67 seconds
Started Jun 21 06:45:57 PM PDT 24
Finished Jun 21 06:46:23 PM PDT 24
Peak memory 201448 kb
Host smart-a08facdb-cd20-454f-bf80-f25e49a3e58f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283138414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.283138414
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2927330586
Short name T855
Test name
Test status
Simulation time 576256702 ps
CPU time 2.6 seconds
Started Jun 21 06:45:55 PM PDT 24
Finished Jun 21 06:46:16 PM PDT 24
Peak memory 201360 kb
Host smart-883b7950-c81a-4316-b91b-1eba35789038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927330586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2927330586
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2958360615
Short name T877
Test name
Test status
Simulation time 4765350864 ps
CPU time 12.56 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:28 PM PDT 24
Peak memory 201436 kb
Host smart-b8517658-2375-4662-9160-c69cbc85cbc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958360615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2958360615
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1251554683
Short name T858
Test name
Test status
Simulation time 411007390 ps
CPU time 0.88 seconds
Started Jun 21 06:46:27 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201136 kb
Host smart-222e0cbe-0f7f-4740-a8fb-28ecc9b11477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251554683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1251554683
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3199302349
Short name T793
Test name
Test status
Simulation time 455529618 ps
CPU time 1.16 seconds
Started Jun 21 06:46:26 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201144 kb
Host smart-82773567-d3a0-4012-ad2f-f142ad692c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199302349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3199302349
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2898547667
Short name T799
Test name
Test status
Simulation time 307852282 ps
CPU time 0.8 seconds
Started Jun 21 06:46:25 PM PDT 24
Finished Jun 21 06:46:36 PM PDT 24
Peak memory 201096 kb
Host smart-761c9e54-7896-4cbd-a2a5-3d0c77a833c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898547667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2898547667
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2413882784
Short name T909
Test name
Test status
Simulation time 507215974 ps
CPU time 1.23 seconds
Started Jun 21 06:46:26 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201120 kb
Host smart-8c95c0ef-cab9-41ec-8d4d-c0561c6fc43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413882784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2413882784
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.285669989
Short name T821
Test name
Test status
Simulation time 510361618 ps
CPU time 1.84 seconds
Started Jun 21 06:46:25 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201180 kb
Host smart-1de8b3ce-6f61-413c-bc1f-bca5da48f188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285669989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.285669989
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2465689627
Short name T876
Test name
Test status
Simulation time 312711793 ps
CPU time 1.34 seconds
Started Jun 21 06:46:26 PM PDT 24
Finished Jun 21 06:46:38 PM PDT 24
Peak memory 201148 kb
Host smart-07a648bb-0a0c-4f39-8972-78387e4a4bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465689627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2465689627
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2918181520
Short name T803
Test name
Test status
Simulation time 509547944 ps
CPU time 1.86 seconds
Started Jun 21 06:46:25 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201140 kb
Host smart-2e3897ae-2087-493e-986c-c50d861658e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918181520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2918181520
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.529381002
Short name T811
Test name
Test status
Simulation time 293698999 ps
CPU time 1.33 seconds
Started Jun 21 06:46:26 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201140 kb
Host smart-f8faa5bc-798e-444c-995c-4b5cb6f9a0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529381002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.529381002
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2983399734
Short name T913
Test name
Test status
Simulation time 516241343 ps
CPU time 0.93 seconds
Started Jun 21 06:46:25 PM PDT 24
Finished Jun 21 06:46:37 PM PDT 24
Peak memory 201140 kb
Host smart-42f3dd25-7d10-40e4-b36b-097d1a275928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983399734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2983399734
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4210297615
Short name T805
Test name
Test status
Simulation time 494960481 ps
CPU time 0.95 seconds
Started Jun 21 06:46:29 PM PDT 24
Finished Jun 21 06:46:39 PM PDT 24
Peak memory 201124 kb
Host smart-ad7956e8-475e-4d09-b48b-e77c6eb8a852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210297615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.4210297615
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3610501434
Short name T871
Test name
Test status
Simulation time 569578459 ps
CPU time 1.94 seconds
Started Jun 21 06:45:55 PM PDT 24
Finished Jun 21 06:46:15 PM PDT 24
Peak memory 201208 kb
Host smart-2d0d230b-d784-47c1-bcfc-e4b600e553ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610501434 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3610501434
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2680416470
Short name T884
Test name
Test status
Simulation time 542316049 ps
CPU time 1.79 seconds
Started Jun 21 06:46:05 PM PDT 24
Finished Jun 21 06:46:25 PM PDT 24
Peak memory 201156 kb
Host smart-d405f0bd-ae5b-4cf1-9217-9c372f226e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680416470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2680416470
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2668280694
Short name T802
Test name
Test status
Simulation time 545541741 ps
CPU time 0.92 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:16 PM PDT 24
Peak memory 201136 kb
Host smart-e1a4475e-6da7-4b3e-aa84-0f8ed3aea355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668280694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2668280694
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3731419386
Short name T108
Test name
Test status
Simulation time 4932002307 ps
CPU time 12.29 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:46:29 PM PDT 24
Peak memory 201440 kb
Host smart-6e86deae-d025-4fd1-ad39-0d9bde366bad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731419386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3731419386
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3712920177
Short name T848
Test name
Test status
Simulation time 543836711 ps
CPU time 2.95 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201488 kb
Host smart-2cd29c07-dfee-48eb-9460-f52fbb475a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712920177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3712920177
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.922705661
Short name T62
Test name
Test status
Simulation time 4754378571 ps
CPU time 4.18 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:20 PM PDT 24
Peak memory 201428 kb
Host smart-210a94cc-9654-4199-b810-36dc033b7115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922705661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.922705661
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3737371483
Short name T864
Test name
Test status
Simulation time 701005284 ps
CPU time 1.34 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201216 kb
Host smart-50ed519b-6439-491d-a2ca-88a0472da8e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737371483 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3737371483
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3594841253
Short name T862
Test name
Test status
Simulation time 423870114 ps
CPU time 1.7 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:16 PM PDT 24
Peak memory 201164 kb
Host smart-dd87f9e2-f2a0-4867-aed2-7b61032ee215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594841253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3594841253
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.234672248
Short name T806
Test name
Test status
Simulation time 331531010 ps
CPU time 0.8 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:15 PM PDT 24
Peak memory 201132 kb
Host smart-42f53dd7-8b4d-4da1-92b8-cfa12cbadaa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234672248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.234672248
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3182525281
Short name T899
Test name
Test status
Simulation time 2711381798 ps
CPU time 8.99 seconds
Started Jun 21 06:45:57 PM PDT 24
Finished Jun 21 06:46:24 PM PDT 24
Peak memory 201412 kb
Host smart-d901b37e-c29c-4fd3-ad9e-c5168354627c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182525281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3182525281
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3605903232
Short name T834
Test name
Test status
Simulation time 464908316 ps
CPU time 2.96 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201420 kb
Host smart-03512468-1f01-4f17-b56c-27a825cc41e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605903232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3605903232
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2350875280
Short name T80
Test name
Test status
Simulation time 8504233159 ps
CPU time 23.14 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:39 PM PDT 24
Peak memory 201412 kb
Host smart-11a7cd79-c852-480c-8a3b-cd3ff00899d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350875280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2350875280
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1134241432
Short name T812
Test name
Test status
Simulation time 537541701 ps
CPU time 1.1 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201212 kb
Host smart-3ce98ec3-9106-4c8d-91e5-863d5e4f5615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134241432 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1134241432
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.220844598
Short name T102
Test name
Test status
Simulation time 361782302 ps
CPU time 1.19 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:46:19 PM PDT 24
Peak memory 201152 kb
Host smart-b762ff7a-033f-4fe4-ae6f-c5d1e39ee339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220844598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.220844598
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3532760744
Short name T833
Test name
Test status
Simulation time 538344853 ps
CPU time 0.92 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:17 PM PDT 24
Peak memory 201100 kb
Host smart-28eaab12-bfc9-48df-99d3-5a94af607ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532760744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3532760744
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.466254010
Short name T914
Test name
Test status
Simulation time 4141303677 ps
CPU time 4.97 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:21 PM PDT 24
Peak memory 201344 kb
Host smart-56ea9edd-da30-41b7-8ef1-6c729b2ce130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466254010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.466254010
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.430530965
Short name T844
Test name
Test status
Simulation time 1129240685 ps
CPU time 1.84 seconds
Started Jun 21 06:46:00 PM PDT 24
Finished Jun 21 06:46:20 PM PDT 24
Peak memory 201416 kb
Host smart-8476660a-3d7b-4f29-80db-f6b6d3434091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430530965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.430530965
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1785153287
Short name T881
Test name
Test status
Simulation time 4702502270 ps
CPU time 4.21 seconds
Started Jun 21 06:46:06 PM PDT 24
Finished Jun 21 06:46:28 PM PDT 24
Peak memory 201376 kb
Host smart-bee3b53e-59e3-4fa9-aac3-da67ce1e10ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785153287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1785153287
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.348473536
Short name T836
Test name
Test status
Simulation time 483666420 ps
CPU time 1.93 seconds
Started Jun 21 06:46:08 PM PDT 24
Finished Jun 21 06:46:27 PM PDT 24
Peak memory 201216 kb
Host smart-d635c2c0-a4b3-4400-85ee-6422c12d6006
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348473536 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.348473536
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2459176894
Short name T814
Test name
Test status
Simulation time 418330915 ps
CPU time 1.63 seconds
Started Jun 21 06:45:59 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201152 kb
Host smart-5bcf9929-16e8-462f-ad85-1ad7ead67c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459176894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2459176894
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.609499005
Short name T866
Test name
Test status
Simulation time 346384066 ps
CPU time 1.34 seconds
Started Jun 21 06:45:56 PM PDT 24
Finished Jun 21 06:46:15 PM PDT 24
Peak memory 201052 kb
Host smart-667c6f20-ca34-43df-badb-0bcd44692c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609499005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.609499005
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2666474331
Short name T823
Test name
Test status
Simulation time 2393399842 ps
CPU time 4.6 seconds
Started Jun 21 06:46:06 PM PDT 24
Finished Jun 21 06:46:28 PM PDT 24
Peak memory 201208 kb
Host smart-45a942bb-385f-4623-891a-2a21aaa9cc82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666474331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2666474331
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.593789091
Short name T70
Test name
Test status
Simulation time 1029622370 ps
CPU time 1.51 seconds
Started Jun 21 06:46:05 PM PDT 24
Finished Jun 21 06:46:24 PM PDT 24
Peak memory 201448 kb
Host smart-7337dca3-fdf0-480c-b85d-bd80c8d5c7ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593789091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.593789091
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3550987856
Short name T865
Test name
Test status
Simulation time 8641752725 ps
CPU time 7.22 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:23 PM PDT 24
Peak memory 201448 kb
Host smart-a3d3dd12-2bb9-4a54-b6d4-1c3bd001a08a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550987856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3550987856
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2664466862
Short name T91
Test name
Test status
Simulation time 573068373 ps
CPU time 2.12 seconds
Started Jun 21 06:46:07 PM PDT 24
Finished Jun 21 06:46:26 PM PDT 24
Peak memory 201220 kb
Host smart-c6977ee2-2e64-4dda-ae4b-186969f25f71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664466862 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2664466862
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.885676263
Short name T889
Test name
Test status
Simulation time 328256160 ps
CPU time 1.55 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201152 kb
Host smart-ed430bf6-4c9f-46e8-89dd-7816bfcca1b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885676263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.885676263
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4212559593
Short name T813
Test name
Test status
Simulation time 283155779 ps
CPU time 1.27 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201140 kb
Host smart-0a10034d-9c74-4a80-99a9-3cc055a586dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212559593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4212559593
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2598307277
Short name T835
Test name
Test status
Simulation time 4531615646 ps
CPU time 8.25 seconds
Started Jun 21 06:46:06 PM PDT 24
Finished Jun 21 06:46:32 PM PDT 24
Peak memory 201384 kb
Host smart-9c20099d-44e3-41be-a995-9c8448e84027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598307277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2598307277
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1044997927
Short name T69
Test name
Test status
Simulation time 550735861 ps
CPU time 2.03 seconds
Started Jun 21 06:45:58 PM PDT 24
Finished Jun 21 06:46:18 PM PDT 24
Peak memory 201420 kb
Host smart-d0823368-58ba-46d0-b2b1-e7583864ee71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044997927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1044997927
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2506392960
Short name T502
Test name
Test status
Simulation time 480476558 ps
CPU time 0.8 seconds
Started Jun 21 06:50:53 PM PDT 24
Finished Jun 21 06:51:00 PM PDT 24
Peak memory 201984 kb
Host smart-4886b5c2-616c-4839-897f-9482137c3c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506392960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2506392960
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3638901298
Short name T253
Test name
Test status
Simulation time 510679249466 ps
CPU time 598.45 seconds
Started Jun 21 06:50:55 PM PDT 24
Finished Jun 21 07:00:59 PM PDT 24
Peak memory 202248 kb
Host smart-e1da9b9d-3592-4285-8d9e-2ab1a487d7d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638901298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3638901298
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3606670731
Short name T318
Test name
Test status
Simulation time 518930773260 ps
CPU time 596.38 seconds
Started Jun 21 06:50:57 PM PDT 24
Finished Jun 21 07:00:58 PM PDT 24
Peak memory 202192 kb
Host smart-ca4ce312-b7c2-4e38-ba00-78f46bc5b200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606670731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3606670731
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2743435069
Short name T675
Test name
Test status
Simulation time 333129820972 ps
CPU time 164.39 seconds
Started Jun 21 06:50:49 PM PDT 24
Finished Jun 21 06:53:38 PM PDT 24
Peak memory 202260 kb
Host smart-159426c5-cde4-435f-b278-7d1120f1e730
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743435069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2743435069
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1622055896
Short name T673
Test name
Test status
Simulation time 160425781459 ps
CPU time 99.96 seconds
Started Jun 21 06:50:45 PM PDT 24
Finished Jun 21 06:52:30 PM PDT 24
Peak memory 202240 kb
Host smart-18ba4a9f-227f-4bc5-8625-55f1361941fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622055896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1622055896
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2398275816
Short name T425
Test name
Test status
Simulation time 317342472472 ps
CPU time 186.39 seconds
Started Jun 21 06:50:48 PM PDT 24
Finished Jun 21 06:53:59 PM PDT 24
Peak memory 202280 kb
Host smart-0c80ed4d-b43c-4644-90db-c78088e91b10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398275816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2398275816
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1824686237
Short name T726
Test name
Test status
Simulation time 97608699317 ps
CPU time 334.16 seconds
Started Jun 21 06:50:55 PM PDT 24
Finished Jun 21 06:56:35 PM PDT 24
Peak memory 202596 kb
Host smart-731d7422-5aa8-49e1-9188-d8743c24462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824686237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1824686237
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3238932089
Short name T426
Test name
Test status
Simulation time 41493365799 ps
CPU time 94.08 seconds
Started Jun 21 06:50:57 PM PDT 24
Finished Jun 21 06:52:36 PM PDT 24
Peak memory 202056 kb
Host smart-61b9a82c-a5e8-4422-9215-83c3dc8f00ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238932089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3238932089
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3115942170
Short name T506
Test name
Test status
Simulation time 4996192112 ps
CPU time 3.94 seconds
Started Jun 21 06:50:55 PM PDT 24
Finished Jun 21 06:51:04 PM PDT 24
Peak memory 202088 kb
Host smart-e0d481d8-2af6-435f-8c37-851a4a5e926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115942170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3115942170
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.819090734
Short name T82
Test name
Test status
Simulation time 7955999333 ps
CPU time 19.1 seconds
Started Jun 21 06:50:55 PM PDT 24
Finished Jun 21 06:51:20 PM PDT 24
Peak memory 218820 kb
Host smart-8259ea1f-fda0-455e-a5da-128d5deb20ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819090734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.819090734
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2057143260
Short name T575
Test name
Test status
Simulation time 5501214996 ps
CPU time 3.97 seconds
Started Jun 21 06:50:43 PM PDT 24
Finished Jun 21 06:50:48 PM PDT 24
Peak memory 202048 kb
Host smart-b6155d40-4895-49b4-9f6a-330ac3895bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057143260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2057143260
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1252865509
Short name T788
Test name
Test status
Simulation time 56510350556 ps
CPU time 112.72 seconds
Started Jun 21 06:50:57 PM PDT 24
Finished Jun 21 06:52:55 PM PDT 24
Peak memory 218988 kb
Host smart-e3ed971e-eb47-4d14-9f03-395d9c2f744b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252865509 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1252865509
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1154388767
Short name T743
Test name
Test status
Simulation time 557225887 ps
CPU time 0.86 seconds
Started Jun 21 06:50:53 PM PDT 24
Finished Jun 21 06:51:00 PM PDT 24
Peak memory 202048 kb
Host smart-cbaa93ee-b477-4f05-a4f9-b7a4d63a804a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154388767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1154388767
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1401630944
Short name T177
Test name
Test status
Simulation time 168472087916 ps
CPU time 104.31 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 06:52:44 PM PDT 24
Peak memory 202248 kb
Host smart-9182b2b8-d97c-4f85-ab7e-a09c24f16544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401630944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1401630944
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3458830449
Short name T144
Test name
Test status
Simulation time 316980921583 ps
CPU time 143.59 seconds
Started Jun 21 06:51:02 PM PDT 24
Finished Jun 21 06:53:29 PM PDT 24
Peak memory 202252 kb
Host smart-36b48fb1-1b38-4844-aa16-cc863d4da2ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458830449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3458830449
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.364388931
Short name T195
Test name
Test status
Simulation time 160809198969 ps
CPU time 386.5 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 06:57:27 PM PDT 24
Peak memory 202320 kb
Host smart-db9e5521-dad0-4605-adc3-b09d0b959eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364388931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.364388931
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1630933839
Short name T571
Test name
Test status
Simulation time 495617684223 ps
CPU time 587.17 seconds
Started Jun 21 06:51:01 PM PDT 24
Finished Jun 21 07:00:52 PM PDT 24
Peak memory 202188 kb
Host smart-da7a712c-cbea-4736-89da-46c652bfd5e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630933839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1630933839
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.848529658
Short name T492
Test name
Test status
Simulation time 312138091653 ps
CPU time 43.76 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 06:51:44 PM PDT 24
Peak memory 202304 kb
Host smart-f690992c-0b04-4d41-a9d2-e652792c8605
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848529658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.848529658
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3436610884
Short name T586
Test name
Test status
Simulation time 577409046723 ps
CPU time 1313.85 seconds
Started Jun 21 06:51:00 PM PDT 24
Finished Jun 21 07:12:58 PM PDT 24
Peak memory 202280 kb
Host smart-8ebd9e78-997a-4f71-a767-7e32c8a99aae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436610884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3436610884
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3295876215
Short name T494
Test name
Test status
Simulation time 128500648390 ps
CPU time 488.04 seconds
Started Jun 21 06:50:56 PM PDT 24
Finished Jun 21 06:59:09 PM PDT 24
Peak memory 202556 kb
Host smart-24cc32d2-bd25-4589-ba4c-4ca4d0d6eab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295876215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3295876215
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3584709078
Short name T53
Test name
Test status
Simulation time 22605085111 ps
CPU time 12.17 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 06:51:12 PM PDT 24
Peak memory 202060 kb
Host smart-0b3a902b-8c83-4c1e-b5ab-550b57344e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584709078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3584709078
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1235932585
Short name T384
Test name
Test status
Simulation time 3152916210 ps
CPU time 9.05 seconds
Started Jun 21 06:50:55 PM PDT 24
Finished Jun 21 06:51:10 PM PDT 24
Peak memory 202052 kb
Host smart-d7a4abc8-174a-413e-ae1b-88e93ecc4be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235932585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1235932585
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.285814611
Short name T83
Test name
Test status
Simulation time 8444662476 ps
CPU time 5.86 seconds
Started Jun 21 06:50:58 PM PDT 24
Finished Jun 21 06:51:08 PM PDT 24
Peak memory 218880 kb
Host smart-74738a06-9791-42b1-87d8-d69b8afb2a0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285814611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.285814611
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.756332697
Short name T355
Test name
Test status
Simulation time 5881726486 ps
CPU time 4.08 seconds
Started Jun 21 06:51:01 PM PDT 24
Finished Jun 21 06:51:08 PM PDT 24
Peak memory 202072 kb
Host smart-d67dddcb-21a6-405e-96c3-1d985fc45c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756332697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.756332697
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.822930843
Short name T774
Test name
Test status
Simulation time 473030046 ps
CPU time 0.71 seconds
Started Jun 21 06:51:32 PM PDT 24
Finished Jun 21 06:51:40 PM PDT 24
Peak memory 201936 kb
Host smart-51b2bc06-5f66-486b-baf1-064f1beeb322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822930843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.822930843
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.4092090824
Short name T638
Test name
Test status
Simulation time 166929833936 ps
CPU time 196.62 seconds
Started Jun 21 06:51:25 PM PDT 24
Finished Jun 21 06:54:48 PM PDT 24
Peak memory 202240 kb
Host smart-61f41d74-392b-4c21-9022-8a8a0cfb8405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092090824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.4092090824
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.783461079
Short name T761
Test name
Test status
Simulation time 329174821738 ps
CPU time 208.9 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:54:58 PM PDT 24
Peak memory 202288 kb
Host smart-aa980f3b-82b4-43ee-89ac-dec452d75fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783461079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.783461079
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1408829876
Short name T750
Test name
Test status
Simulation time 489979890161 ps
CPU time 296.09 seconds
Started Jun 21 06:51:26 PM PDT 24
Finished Jun 21 06:56:29 PM PDT 24
Peak memory 202264 kb
Host smart-b5b25efa-76a0-48ba-a5c6-8dd540d98925
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408829876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1408829876
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.386811412
Short name T611
Test name
Test status
Simulation time 488355789060 ps
CPU time 299.05 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:56:28 PM PDT 24
Peak memory 202264 kb
Host smart-17f80eda-d554-4c04-aefa-88d8c467eabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386811412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.386811412
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.13384584
Short name T370
Test name
Test status
Simulation time 169849114036 ps
CPU time 97.84 seconds
Started Jun 21 06:51:30 PM PDT 24
Finished Jun 21 06:53:14 PM PDT 24
Peak memory 202284 kb
Host smart-eeadea8e-86a3-485e-add3-5601c2bfcad9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=13384584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed
.13384584
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2192226213
Short name T662
Test name
Test status
Simulation time 352346412777 ps
CPU time 319.59 seconds
Started Jun 21 06:51:30 PM PDT 24
Finished Jun 21 06:56:56 PM PDT 24
Peak memory 202236 kb
Host smart-187e2750-2538-4ee1-8c40-bd801514a8eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192226213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2192226213
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2650179750
Short name T596
Test name
Test status
Simulation time 198311779119 ps
CPU time 436.17 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:58:45 PM PDT 24
Peak memory 202212 kb
Host smart-3762e065-1529-47fc-b600-06465789b186
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650179750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2650179750
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.353103683
Short name T786
Test name
Test status
Simulation time 76008022629 ps
CPU time 326.35 seconds
Started Jun 21 06:51:25 PM PDT 24
Finished Jun 21 06:56:58 PM PDT 24
Peak memory 202500 kb
Host smart-77ebf3fd-b137-48db-8681-b067448b103c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353103683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.353103683
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2330319339
Short name T373
Test name
Test status
Simulation time 42106088723 ps
CPU time 98.11 seconds
Started Jun 21 06:51:23 PM PDT 24
Finished Jun 21 06:53:05 PM PDT 24
Peak memory 202016 kb
Host smart-5b83a8d9-67e4-4610-8849-a70331f14649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330319339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2330319339
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3102701336
Short name T621
Test name
Test status
Simulation time 3277045668 ps
CPU time 2.73 seconds
Started Jun 21 06:51:27 PM PDT 24
Finished Jun 21 06:51:37 PM PDT 24
Peak memory 202036 kb
Host smart-3e032f94-9b02-4687-82fd-474f9cd0ad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102701336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3102701336
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2584651362
Short name T364
Test name
Test status
Simulation time 5782329146 ps
CPU time 6.21 seconds
Started Jun 21 06:51:27 PM PDT 24
Finished Jun 21 06:51:41 PM PDT 24
Peak memory 202064 kb
Host smart-6e7727d5-d8f1-4baa-8725-af90184a613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584651362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2584651362
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.545261888
Short name T510
Test name
Test status
Simulation time 254137915187 ps
CPU time 176.87 seconds
Started Jun 21 06:51:34 PM PDT 24
Finished Jun 21 06:54:38 PM PDT 24
Peak memory 202196 kb
Host smart-c648d953-8ec6-4fc3-96a3-7d28296cc56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545261888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
545261888
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3276008440
Short name T535
Test name
Test status
Simulation time 71859776204 ps
CPU time 175.11 seconds
Started Jun 21 06:51:34 PM PDT 24
Finished Jun 21 06:54:36 PM PDT 24
Peak memory 202156 kb
Host smart-2408943d-f6ad-4a4b-b6c5-c89fa6182a45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276008440 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3276008440
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3169619434
Short name T412
Test name
Test status
Simulation time 494925776 ps
CPU time 0.91 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 06:51:42 PM PDT 24
Peak memory 201912 kb
Host smart-57e9011d-f50f-49f0-900c-a09a1ef002a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169619434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3169619434
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.675781252
Short name T158
Test name
Test status
Simulation time 165959211251 ps
CPU time 399.61 seconds
Started Jun 21 06:51:32 PM PDT 24
Finished Jun 21 06:58:19 PM PDT 24
Peak memory 202292 kb
Host smart-29d67ae1-6305-4beb-bcc4-43c8a9463469
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675781252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.675781252
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2933939195
Short name T625
Test name
Test status
Simulation time 175960392079 ps
CPU time 422.09 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 06:58:42 PM PDT 24
Peak memory 202220 kb
Host smart-b2750cde-663a-4977-a4c3-0f028ec8cf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933939195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2933939195
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1459218773
Short name T268
Test name
Test status
Simulation time 321981475645 ps
CPU time 768.83 seconds
Started Jun 21 06:51:32 PM PDT 24
Finished Jun 21 07:04:28 PM PDT 24
Peak memory 202244 kb
Host smart-e7ae8e5f-7bfe-48a4-a548-f967035bd7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459218773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1459218773
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2097241692
Short name T349
Test name
Test status
Simulation time 497313708644 ps
CPU time 557.78 seconds
Started Jun 21 06:51:34 PM PDT 24
Finished Jun 21 07:00:59 PM PDT 24
Peak memory 202196 kb
Host smart-3a28bde0-3ef6-413c-afd0-f005e32cd918
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097241692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2097241692
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1283105539
Short name T450
Test name
Test status
Simulation time 167608448551 ps
CPU time 44.9 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 06:52:24 PM PDT 24
Peak memory 202324 kb
Host smart-583de42b-bf9b-4ea1-917d-88e70c4c0884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283105539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1283105539
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2295474558
Short name T500
Test name
Test status
Simulation time 167324428839 ps
CPU time 352.88 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 06:57:32 PM PDT 24
Peak memory 202288 kb
Host smart-9891c117-cfc8-4b2c-b84d-cd7fb6affc5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295474558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2295474558
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1692347240
Short name T504
Test name
Test status
Simulation time 179873580658 ps
CPU time 88.71 seconds
Started Jun 21 06:51:34 PM PDT 24
Finished Jun 21 06:53:10 PM PDT 24
Peak memory 202328 kb
Host smart-45f5bfee-9349-4edd-9393-f8bcfca4a891
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692347240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1692347240
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.940484386
Short name T442
Test name
Test status
Simulation time 633435568573 ps
CPU time 299.74 seconds
Started Jun 21 06:51:36 PM PDT 24
Finished Jun 21 06:56:42 PM PDT 24
Peak memory 202204 kb
Host smart-6c1019ed-3abd-401c-98be-cdbb46a4d886
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940484386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.940484386
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.703291975
Short name T746
Test name
Test status
Simulation time 128171335426 ps
CPU time 523.06 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 07:00:23 PM PDT 24
Peak memory 202620 kb
Host smart-216d1872-05b9-4cb7-9c11-f9d0cf66a6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703291975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.703291975
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3586910817
Short name T351
Test name
Test status
Simulation time 36981640102 ps
CPU time 21.65 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 06:52:02 PM PDT 24
Peak memory 202056 kb
Host smart-477c38d2-37be-47be-9327-70a1a3c5f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586910817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3586910817
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1578083035
Short name T377
Test name
Test status
Simulation time 4820469265 ps
CPU time 3.83 seconds
Started Jun 21 06:51:32 PM PDT 24
Finished Jun 21 06:51:42 PM PDT 24
Peak memory 202060 kb
Host smart-f4b05d95-b2eb-4ded-9048-9c8a2d952df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578083035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1578083035
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.266826056
Short name T399
Test name
Test status
Simulation time 5549346350 ps
CPU time 7.02 seconds
Started Jun 21 06:51:30 PM PDT 24
Finished Jun 21 06:51:44 PM PDT 24
Peak memory 202056 kb
Host smart-ac923445-b0f6-4dde-b354-28caa069f4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266826056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.266826056
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4081248967
Short name T734
Test name
Test status
Simulation time 93459638509 ps
CPU time 219.56 seconds
Started Jun 21 06:51:32 PM PDT 24
Finished Jun 21 06:55:18 PM PDT 24
Peak memory 202056 kb
Host smart-d18f0b10-2810-41d7-b767-62816e73852f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081248967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4081248967
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1961784091
Short name T22
Test name
Test status
Simulation time 231058265086 ps
CPU time 41.32 seconds
Started Jun 21 06:51:31 PM PDT 24
Finished Jun 21 06:52:19 PM PDT 24
Peak memory 210548 kb
Host smart-72fecab3-ddfb-4ab1-863c-8f804e0adbac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961784091 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1961784091
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3427140989
Short name T395
Test name
Test status
Simulation time 367946971 ps
CPU time 1.46 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 06:51:41 PM PDT 24
Peak memory 201944 kb
Host smart-db339f79-8c6d-474e-b0ce-bba27813333f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427140989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3427140989
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3885204084
Short name T550
Test name
Test status
Simulation time 172194930004 ps
CPU time 90.41 seconds
Started Jun 21 06:51:32 PM PDT 24
Finished Jun 21 06:53:09 PM PDT 24
Peak memory 202316 kb
Host smart-c0a56a56-f604-44db-8da9-9b8213ea159b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885204084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3885204084
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1288015734
Short name T232
Test name
Test status
Simulation time 166792294754 ps
CPU time 362.82 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 06:57:42 PM PDT 24
Peak memory 202304 kb
Host smart-d904d415-ed0f-476c-8b98-a9661b6f4716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288015734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1288015734
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1053344692
Short name T166
Test name
Test status
Simulation time 493696501788 ps
CPU time 120.47 seconds
Started Jun 21 06:51:35 PM PDT 24
Finished Jun 21 06:53:42 PM PDT 24
Peak memory 202248 kb
Host smart-33d4b082-a562-4a9b-ac44-ee7d1ffeb88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053344692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1053344692
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2557236125
Short name T642
Test name
Test status
Simulation time 162342046334 ps
CPU time 172.47 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 06:54:32 PM PDT 24
Peak memory 202208 kb
Host smart-fe1dbf15-977b-430d-9cd6-f20450897c1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557236125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2557236125
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3729000750
Short name T754
Test name
Test status
Simulation time 322076212326 ps
CPU time 389.71 seconds
Started Jun 21 06:51:33 PM PDT 24
Finished Jun 21 06:58:09 PM PDT 24
Peak memory 202280 kb
Host smart-045329db-0b45-487f-94b0-e989ef005e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729000750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3729000750
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.770095861
Short name T792
Test name
Test status
Simulation time 325995473059 ps
CPU time 84.37 seconds
Started Jun 21 06:51:32 PM PDT 24
Finished Jun 21 06:53:04 PM PDT 24
Peak memory 202160 kb
Host smart-1fa57d31-3b5b-4e16-acc7-57fce683ef87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=770095861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.770095861
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3277330394
Short name T588
Test name
Test status
Simulation time 572563690505 ps
CPU time 325.35 seconds
Started Jun 21 06:51:32 PM PDT 24
Finished Jun 21 06:57:05 PM PDT 24
Peak memory 202296 kb
Host smart-c2caf4cf-4dcf-4f2f-a464-f7dd9b52b611
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277330394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3277330394
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.899588934
Short name T767
Test name
Test status
Simulation time 598371487148 ps
CPU time 722.13 seconds
Started Jun 21 06:51:34 PM PDT 24
Finished Jun 21 07:03:43 PM PDT 24
Peak memory 201980 kb
Host smart-4cf71a31-ba9f-4161-974c-34f908a28f69
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899588934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.899588934
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.854221586
Short name T789
Test name
Test status
Simulation time 115239562904 ps
CPU time 608.95 seconds
Started Jun 21 06:51:34 PM PDT 24
Finished Jun 21 07:01:50 PM PDT 24
Peak memory 202564 kb
Host smart-5862d101-7b04-444e-9bbc-31e56ebe4429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854221586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.854221586
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1715534816
Short name T385
Test name
Test status
Simulation time 32037118796 ps
CPU time 17.91 seconds
Started Jun 21 06:51:32 PM PDT 24
Finished Jun 21 06:51:56 PM PDT 24
Peak memory 202080 kb
Host smart-1b66ad0f-cb72-4170-86a6-5f039e9431b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715534816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1715534816
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2048823823
Short name T362
Test name
Test status
Simulation time 4683831606 ps
CPU time 3.4 seconds
Started Jun 21 06:51:31 PM PDT 24
Finished Jun 21 06:51:41 PM PDT 24
Peak memory 202048 kb
Host smart-e2b710c9-262e-417c-9971-d4e110db6463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048823823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2048823823
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3764328039
Short name T345
Test name
Test status
Simulation time 5943585262 ps
CPU time 3.79 seconds
Started Jun 21 06:51:31 PM PDT 24
Finished Jun 21 06:51:42 PM PDT 24
Peak memory 202052 kb
Host smart-e50291cd-99ff-4a6b-96d4-8deacdac9d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764328039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3764328039
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.872275655
Short name T622
Test name
Test status
Simulation time 544113819487 ps
CPU time 1805.33 seconds
Started Jun 21 06:51:36 PM PDT 24
Finished Jun 21 07:21:48 PM PDT 24
Peak memory 202540 kb
Host smart-dee6a0bd-1ce4-4393-b710-33e413759410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872275655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
872275655
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3679059961
Short name T576
Test name
Test status
Simulation time 454701246 ps
CPU time 1.7 seconds
Started Jun 21 06:51:41 PM PDT 24
Finished Jun 21 06:51:47 PM PDT 24
Peak memory 201940 kb
Host smart-490840e0-45a3-4c7d-87fa-ec05ce90997d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679059961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3679059961
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2898755596
Short name T196
Test name
Test status
Simulation time 547594079275 ps
CPU time 302.4 seconds
Started Jun 21 06:51:45 PM PDT 24
Finished Jun 21 06:56:52 PM PDT 24
Peak memory 201952 kb
Host smart-d18dcd31-51d1-428c-93ac-aeed02dd938d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898755596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2898755596
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3387361879
Short name T398
Test name
Test status
Simulation time 327955781282 ps
CPU time 409.07 seconds
Started Jun 21 06:51:42 PM PDT 24
Finished Jun 21 06:58:35 PM PDT 24
Peak memory 202208 kb
Host smart-6e07893d-a05f-4899-a6c7-0bb2b6add64e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387361879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3387361879
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3796527218
Short name T512
Test name
Test status
Simulation time 160862657220 ps
CPU time 64.61 seconds
Started Jun 21 06:51:48 PM PDT 24
Finished Jun 21 06:52:57 PM PDT 24
Peak memory 202324 kb
Host smart-fa5598ef-f24b-4c17-b252-2fedcb924f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796527218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3796527218
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2851648830
Short name T340
Test name
Test status
Simulation time 170542519231 ps
CPU time 349.59 seconds
Started Jun 21 06:51:41 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 202296 kb
Host smart-ce860eb2-72b6-4e9e-b5d4-7008bfdc0ccc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851648830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2851648830
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2077626888
Short name T643
Test name
Test status
Simulation time 202855716716 ps
CPU time 468.24 seconds
Started Jun 21 06:51:43 PM PDT 24
Finished Jun 21 06:59:37 PM PDT 24
Peak memory 202244 kb
Host smart-3278c4e9-55b8-4395-81a5-fdedd77597d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077626888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2077626888
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2031867357
Short name T133
Test name
Test status
Simulation time 596143745503 ps
CPU time 267.07 seconds
Started Jun 21 06:51:43 PM PDT 24
Finished Jun 21 06:56:16 PM PDT 24
Peak memory 202212 kb
Host smart-4577f738-b133-4df7-8e33-750062f95b95
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031867357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2031867357
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1485804372
Short name T703
Test name
Test status
Simulation time 110522439201 ps
CPU time 608.13 seconds
Started Jun 21 06:51:41 PM PDT 24
Finished Jun 21 07:01:53 PM PDT 24
Peak memory 202620 kb
Host smart-cbff11d8-d875-4f7c-90c4-64265bce0a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485804372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1485804372
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3561542526
Short name T390
Test name
Test status
Simulation time 30654312489 ps
CPU time 17.02 seconds
Started Jun 21 06:51:43 PM PDT 24
Finished Jun 21 06:52:06 PM PDT 24
Peak memory 202052 kb
Host smart-7ef35432-0dff-48c1-94d7-128ef1a18177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561542526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3561542526
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3551068459
Short name T437
Test name
Test status
Simulation time 2701775640 ps
CPU time 7.75 seconds
Started Jun 21 06:51:46 PM PDT 24
Finished Jun 21 06:51:59 PM PDT 24
Peak memory 202032 kb
Host smart-21d7100f-8ae4-4a43-8464-dd19b5ce1e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551068459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3551068459
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2946332302
Short name T497
Test name
Test status
Simulation time 5930030728 ps
CPU time 4.45 seconds
Started Jun 21 06:51:31 PM PDT 24
Finished Jun 21 06:51:42 PM PDT 24
Peak memory 202000 kb
Host smart-5b458ecf-208a-4d3d-88ee-50302456ff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946332302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2946332302
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3238224094
Short name T13
Test name
Test status
Simulation time 38635873958 ps
CPU time 59.27 seconds
Started Jun 21 06:51:43 PM PDT 24
Finished Jun 21 06:52:46 PM PDT 24
Peak memory 211548 kb
Host smart-1a83255a-d9f6-440d-80f8-7f5b23e08f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238224094 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3238224094
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.588307375
Short name T641
Test name
Test status
Simulation time 458285082 ps
CPU time 1.61 seconds
Started Jun 21 06:51:46 PM PDT 24
Finished Jun 21 06:51:52 PM PDT 24
Peak memory 201932 kb
Host smart-eb093681-fe7f-4384-a867-01743cbb6ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588307375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.588307375
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.4172176563
Short name T296
Test name
Test status
Simulation time 165983539605 ps
CPU time 368.08 seconds
Started Jun 21 06:51:43 PM PDT 24
Finished Jun 21 06:57:56 PM PDT 24
Peak memory 202352 kb
Host smart-34de7ce6-a2ec-46bf-a315-d1f4b790e4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172176563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.4172176563
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.74726290
Short name T379
Test name
Test status
Simulation time 500808205227 ps
CPU time 1169.92 seconds
Started Jun 21 06:51:45 PM PDT 24
Finished Jun 21 07:11:20 PM PDT 24
Peak memory 201756 kb
Host smart-4f250a4c-d71d-4944-beb6-f79f32a79648
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=74726290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt
_fixed.74726290
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1345592504
Short name T215
Test name
Test status
Simulation time 494588109011 ps
CPU time 589.59 seconds
Started Jun 21 06:51:41 PM PDT 24
Finished Jun 21 07:01:35 PM PDT 24
Peak memory 202320 kb
Host smart-fa7d785d-0434-41a5-82c8-33923e201a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345592504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1345592504
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.62357496
Short name T474
Test name
Test status
Simulation time 497787908302 ps
CPU time 294.87 seconds
Started Jun 21 06:51:43 PM PDT 24
Finished Jun 21 06:56:42 PM PDT 24
Peak memory 202204 kb
Host smart-37bff2fa-c89c-45f7-b718-cfc34c098b56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=62357496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed
.62357496
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1746362386
Short name T251
Test name
Test status
Simulation time 164747227586 ps
CPU time 389.46 seconds
Started Jun 21 06:51:46 PM PDT 24
Finished Jun 21 06:58:20 PM PDT 24
Peak memory 202208 kb
Host smart-16c41005-11dc-4591-be3a-9f2fc6fcd06d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746362386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1746362386
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2989581706
Short name T714
Test name
Test status
Simulation time 617146629290 ps
CPU time 723.58 seconds
Started Jun 21 06:51:45 PM PDT 24
Finished Jun 21 07:03:54 PM PDT 24
Peak memory 202188 kb
Host smart-80f9b2a7-8c15-48e9-9f4a-aa681af24069
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989581706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2989581706
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1793877285
Short name T678
Test name
Test status
Simulation time 109366159858 ps
CPU time 473.66 seconds
Started Jun 21 06:51:45 PM PDT 24
Finished Jun 21 06:59:44 PM PDT 24
Peak memory 202556 kb
Host smart-ae10e1c4-8de1-4f10-b9c4-65502e822db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793877285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1793877285
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3578317764
Short name T710
Test name
Test status
Simulation time 23072369845 ps
CPU time 10.42 seconds
Started Jun 21 06:51:45 PM PDT 24
Finished Jun 21 06:52:00 PM PDT 24
Peak memory 202056 kb
Host smart-4fc6eea9-fd98-4230-ae07-a291a7e0455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578317764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3578317764
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2870219501
Short name T720
Test name
Test status
Simulation time 3912789754 ps
CPU time 2.67 seconds
Started Jun 21 06:51:45 PM PDT 24
Finished Jun 21 06:51:53 PM PDT 24
Peak memory 202072 kb
Host smart-536d9b97-59ca-4965-908c-c8c64ec5dbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870219501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2870219501
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1113716661
Short name T753
Test name
Test status
Simulation time 5640156140 ps
CPU time 4.15 seconds
Started Jun 21 06:51:42 PM PDT 24
Finished Jun 21 06:51:51 PM PDT 24
Peak memory 202008 kb
Host smart-a83fd59c-39e9-47b4-92dd-9f210bceb3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113716661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1113716661
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2280541402
Short name T288
Test name
Test status
Simulation time 413998910886 ps
CPU time 742.36 seconds
Started Jun 21 06:51:45 PM PDT 24
Finished Jun 21 07:04:12 PM PDT 24
Peak memory 202536 kb
Host smart-be056776-69bd-46f7-85b8-05b4730ec082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280541402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2280541402
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3709052811
Short name T269
Test name
Test status
Simulation time 85042496182 ps
CPU time 54.43 seconds
Started Jun 21 06:51:46 PM PDT 24
Finished Jun 21 06:52:45 PM PDT 24
Peak memory 210624 kb
Host smart-bf2dcbf5-ac03-4f7e-a340-e57f423e1b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709052811 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3709052811
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2861792979
Short name T548
Test name
Test status
Simulation time 452663432 ps
CPU time 1.2 seconds
Started Jun 21 06:51:51 PM PDT 24
Finished Jun 21 06:51:58 PM PDT 24
Peak memory 201944 kb
Host smart-c997a688-4124-4333-af7a-31795142e184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861792979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2861792979
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2011881267
Short name T331
Test name
Test status
Simulation time 328433516740 ps
CPU time 181.1 seconds
Started Jun 21 06:51:53 PM PDT 24
Finished Jun 21 06:55:00 PM PDT 24
Peak memory 202244 kb
Host smart-7580e6c5-f312-4ec0-8710-9be4bea96cb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011881267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2011881267
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3636313495
Short name T519
Test name
Test status
Simulation time 161701286565 ps
CPU time 94.36 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 06:53:32 PM PDT 24
Peak memory 202332 kb
Host smart-90716592-8ee8-4a67-98b2-e368057dd213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636313495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3636313495
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3862877887
Short name T182
Test name
Test status
Simulation time 491723591434 ps
CPU time 269.8 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 06:56:27 PM PDT 24
Peak memory 202240 kb
Host smart-0db9a584-53eb-41f9-b092-b01f47d50a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862877887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3862877887
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3915893502
Short name T472
Test name
Test status
Simulation time 496117885558 ps
CPU time 1170.08 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 07:11:29 PM PDT 24
Peak memory 202196 kb
Host smart-a504498d-59f9-4a75-8b8d-7c82970a4890
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915893502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3915893502
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1905906150
Short name T126
Test name
Test status
Simulation time 496823663503 ps
CPU time 262.79 seconds
Started Jun 21 06:51:50 PM PDT 24
Finished Jun 21 06:56:18 PM PDT 24
Peak memory 202320 kb
Host smart-cdf3e323-adc9-4c57-b74b-ce80f3c9a7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905906150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1905906150
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.4056473484
Short name T30
Test name
Test status
Simulation time 332212646716 ps
CPU time 417.11 seconds
Started Jun 21 06:51:51 PM PDT 24
Finished Jun 21 06:58:54 PM PDT 24
Peak memory 202328 kb
Host smart-b3bb5fa6-0dee-4ffc-beb1-f4c6550bf224
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056473484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.4056473484
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.792899865
Short name T12
Test name
Test status
Simulation time 169570332350 ps
CPU time 190.56 seconds
Started Jun 21 06:51:51 PM PDT 24
Finished Jun 21 06:55:07 PM PDT 24
Peak memory 202164 kb
Host smart-4f818bb8-a549-4139-95f1-7007c3ad993e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792899865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.792899865
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3288078851
Short name T777
Test name
Test status
Simulation time 200128582311 ps
CPU time 108.35 seconds
Started Jun 21 06:51:51 PM PDT 24
Finished Jun 21 06:53:45 PM PDT 24
Peak memory 202296 kb
Host smart-ba759260-2fae-4217-af8e-14074700f66a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288078851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3288078851
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1334890994
Short name T206
Test name
Test status
Simulation time 133566704687 ps
CPU time 669.25 seconds
Started Jun 21 06:51:53 PM PDT 24
Finished Jun 21 07:03:08 PM PDT 24
Peak memory 202628 kb
Host smart-a63055eb-5372-4284-b187-12fd435e2715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334890994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1334890994
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3163989135
Short name T595
Test name
Test status
Simulation time 44532212608 ps
CPU time 26.07 seconds
Started Jun 21 06:51:50 PM PDT 24
Finished Jun 21 06:52:21 PM PDT 24
Peak memory 202068 kb
Host smart-be86edc1-d1e5-4649-8c31-079d8e58890c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163989135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3163989135
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3598011773
Short name T618
Test name
Test status
Simulation time 5361428015 ps
CPU time 4.09 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 06:52:02 PM PDT 24
Peak memory 202048 kb
Host smart-0144fd20-119c-448b-8b91-4ca7ea20ae47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598011773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3598011773
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2737600224
Short name T580
Test name
Test status
Simulation time 5973599993 ps
CPU time 4.44 seconds
Started Jun 21 06:51:43 PM PDT 24
Finished Jun 21 06:51:53 PM PDT 24
Peak memory 202168 kb
Host smart-031c220d-2019-46ac-ae1e-17d7b4a9b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737600224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2737600224
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.746098638
Short name T649
Test name
Test status
Simulation time 171934380492 ps
CPU time 104.03 seconds
Started Jun 21 06:51:51 PM PDT 24
Finished Jun 21 06:53:41 PM PDT 24
Peak memory 202220 kb
Host smart-3c934968-d1d6-444a-b1c9-b0829843f247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746098638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
746098638
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.827721623
Short name T261
Test name
Test status
Simulation time 94552326305 ps
CPU time 223.09 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 06:55:41 PM PDT 24
Peak memory 219012 kb
Host smart-978e988e-7d73-4d64-bb74-45905df8b01e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827721623 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.827721623
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1289617652
Short name T573
Test name
Test status
Simulation time 348750639 ps
CPU time 0.83 seconds
Started Jun 21 06:52:00 PM PDT 24
Finished Jun 21 06:52:04 PM PDT 24
Peak memory 201900 kb
Host smart-f295743f-3451-4b04-83b3-ba9ad043f909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289617652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1289617652
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.952422450
Short name T257
Test name
Test status
Simulation time 337688942332 ps
CPU time 273.9 seconds
Started Jun 21 06:51:53 PM PDT 24
Finished Jun 21 06:56:33 PM PDT 24
Peak memory 202320 kb
Host smart-7bca5022-d660-4d1f-98c3-9cd47ae5311d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952422450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.952422450
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1492790481
Short name T605
Test name
Test status
Simulation time 324604535417 ps
CPU time 781.12 seconds
Started Jun 21 06:51:53 PM PDT 24
Finished Jun 21 07:05:00 PM PDT 24
Peak memory 202344 kb
Host smart-ac61bb4d-85a0-4b1c-a39a-c0bb62673bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492790481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1492790481
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1531579592
Short name T314
Test name
Test status
Simulation time 160001706274 ps
CPU time 174.18 seconds
Started Jun 21 06:51:50 PM PDT 24
Finished Jun 21 06:54:50 PM PDT 24
Peak memory 202240 kb
Host smart-c395b1da-7146-42ea-92ef-53435fe35e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531579592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1531579592
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3296815364
Short name T414
Test name
Test status
Simulation time 330255962682 ps
CPU time 205.81 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 06:55:24 PM PDT 24
Peak memory 202268 kb
Host smart-c1f50cda-804a-40c3-91ec-4f1bd330b560
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296815364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3296815364
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2989134631
Short name T304
Test name
Test status
Simulation time 492576937909 ps
CPU time 542.9 seconds
Started Jun 21 06:51:50 PM PDT 24
Finished Jun 21 07:00:58 PM PDT 24
Peak memory 202240 kb
Host smart-99be39ca-b2d8-4600-8b05-1a9ace2ffbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989134631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2989134631
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3485575377
Short name T490
Test name
Test status
Simulation time 322965370415 ps
CPU time 151.38 seconds
Started Jun 21 06:51:51 PM PDT 24
Finished Jun 21 06:54:28 PM PDT 24
Peak memory 202292 kb
Host smart-1bdb8045-f3a7-4e5a-86b0-445e95d4a25f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485575377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3485575377
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.829220179
Short name T308
Test name
Test status
Simulation time 431608375668 ps
CPU time 199.34 seconds
Started Jun 21 06:51:51 PM PDT 24
Finished Jun 21 06:55:16 PM PDT 24
Peak memory 202304 kb
Host smart-2ecf4864-9905-4db5-8d07-57e8fdc10f44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829220179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.829220179
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2013042082
Short name T557
Test name
Test status
Simulation time 586724884904 ps
CPU time 360.03 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 06:57:57 PM PDT 24
Peak memory 202188 kb
Host smart-3fc2e63b-167d-4f7e-9c83-ce87816ba83a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013042082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2013042082
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3757795298
Short name T559
Test name
Test status
Simulation time 101007452868 ps
CPU time 292.65 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 06:56:51 PM PDT 24
Peak memory 202552 kb
Host smart-a1a98829-1416-429c-83d8-772d1010c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757795298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3757795298
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1764364334
Short name T440
Test name
Test status
Simulation time 37869789290 ps
CPU time 21.73 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 06:52:20 PM PDT 24
Peak memory 202040 kb
Host smart-33d5d41c-269c-494c-8720-6e74a9d17a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764364334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1764364334
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1037088553
Short name T729
Test name
Test status
Simulation time 4783950750 ps
CPU time 12.37 seconds
Started Jun 21 06:51:51 PM PDT 24
Finished Jun 21 06:52:09 PM PDT 24
Peak memory 201996 kb
Host smart-cb6f354f-880d-4466-b5cf-ccbc0a223a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037088553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1037088553
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1665043744
Short name T435
Test name
Test status
Simulation time 5999040016 ps
CPU time 8 seconds
Started Jun 21 06:51:52 PM PDT 24
Finished Jun 21 06:52:07 PM PDT 24
Peak memory 202052 kb
Host smart-b4de096e-4b6a-4b94-a33f-4a5161adf1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665043744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1665043744
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.759603825
Short name T180
Test name
Test status
Simulation time 208802118173 ps
CPU time 150.01 seconds
Started Jun 21 06:51:51 PM PDT 24
Finished Jun 21 06:54:27 PM PDT 24
Peak memory 202236 kb
Host smart-ff500c34-9c43-4998-a073-47fc96794c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759603825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
759603825
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.567346560
Short name T368
Test name
Test status
Simulation time 348454045 ps
CPU time 1.41 seconds
Started Jun 21 06:52:00 PM PDT 24
Finished Jun 21 06:52:05 PM PDT 24
Peak memory 201980 kb
Host smart-a31587d6-df76-4d77-9a72-94c504dbe1e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567346560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.567346560
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1378495183
Short name T285
Test name
Test status
Simulation time 179563175117 ps
CPU time 109.89 seconds
Started Jun 21 06:52:01 PM PDT 24
Finished Jun 21 06:53:54 PM PDT 24
Peak memory 202288 kb
Host smart-4459a85f-1440-4c21-a0f4-79f224b38176
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378495183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1378495183
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3776348943
Short name T624
Test name
Test status
Simulation time 159433489581 ps
CPU time 388.85 seconds
Started Jun 21 06:52:00 PM PDT 24
Finished Jun 21 06:58:32 PM PDT 24
Peak memory 202324 kb
Host smart-bcd612af-7f4f-4da6-a41b-f212f2504fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776348943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3776348943
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4058908702
Short name T591
Test name
Test status
Simulation time 332989740511 ps
CPU time 706.98 seconds
Started Jun 21 06:52:03 PM PDT 24
Finished Jun 21 07:03:54 PM PDT 24
Peak memory 202204 kb
Host smart-b2d02795-d59c-4790-a0bf-fe5d01381154
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058908702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4058908702
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2652730066
Short name T387
Test name
Test status
Simulation time 329380267639 ps
CPU time 201.1 seconds
Started Jun 21 06:51:59 PM PDT 24
Finished Jun 21 06:55:24 PM PDT 24
Peak memory 202284 kb
Host smart-8a1f9b0e-048a-4431-bffc-1efc9800be7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652730066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2652730066
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3272872151
Short name T393
Test name
Test status
Simulation time 166316101743 ps
CPU time 26.91 seconds
Started Jun 21 06:51:58 PM PDT 24
Finished Jun 21 06:52:30 PM PDT 24
Peak memory 202136 kb
Host smart-43ab8820-32cb-4f7a-8552-0676618b932e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272872151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3272872151
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2960965966
Short name T657
Test name
Test status
Simulation time 173382748971 ps
CPU time 368.74 seconds
Started Jun 21 06:51:59 PM PDT 24
Finished Jun 21 06:58:12 PM PDT 24
Peak memory 202312 kb
Host smart-c8fdbba4-81ad-4750-b539-cac3d002cc5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960965966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2960965966
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1031843121
Short name T29
Test name
Test status
Simulation time 197084278540 ps
CPU time 110.03 seconds
Started Jun 21 06:51:59 PM PDT 24
Finished Jun 21 06:53:53 PM PDT 24
Peak memory 202248 kb
Host smart-959ffeca-52fe-46b7-bfc8-a3c8db1acd6e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031843121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1031843121
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2710251628
Short name T55
Test name
Test status
Simulation time 78894259844 ps
CPU time 303.16 seconds
Started Jun 21 06:52:00 PM PDT 24
Finished Jun 21 06:57:06 PM PDT 24
Peak memory 202600 kb
Host smart-068075e2-3f2d-4b0d-8285-7eb35de6691d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710251628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2710251628
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1791372419
Short name T598
Test name
Test status
Simulation time 43311904676 ps
CPU time 99.05 seconds
Started Jun 21 06:51:58 PM PDT 24
Finished Jun 21 06:53:42 PM PDT 24
Peak memory 202096 kb
Host smart-72090c71-d6a7-437d-af32-34d3806c1ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791372419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1791372419
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3623918151
Short name T542
Test name
Test status
Simulation time 3611905854 ps
CPU time 1.09 seconds
Started Jun 21 06:52:02 PM PDT 24
Finished Jun 21 06:52:07 PM PDT 24
Peak memory 202056 kb
Host smart-b28404f3-beb1-4ec1-9fde-1e640d64b9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623918151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3623918151
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.77380410
Short name T24
Test name
Test status
Simulation time 5791419755 ps
CPU time 4.04 seconds
Started Jun 21 06:51:59 PM PDT 24
Finished Jun 21 06:52:07 PM PDT 24
Peak memory 202052 kb
Host smart-d849d5e1-1e46-4e60-9bee-55a8415645ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77380410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.77380410
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1641484839
Short name T530
Test name
Test status
Simulation time 441518768970 ps
CPU time 1333.05 seconds
Started Jun 21 06:52:01 PM PDT 24
Finished Jun 21 07:14:17 PM PDT 24
Peak memory 212600 kb
Host smart-abfa1460-2d5f-4f44-8001-b834253e0413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641484839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1641484839
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.814975346
Short name T732
Test name
Test status
Simulation time 322882425 ps
CPU time 1.03 seconds
Started Jun 21 06:52:09 PM PDT 24
Finished Jun 21 06:52:13 PM PDT 24
Peak memory 201928 kb
Host smart-56343a67-5055-4897-8458-9a3d6f36840f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814975346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.814975346
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.889414171
Short name T778
Test name
Test status
Simulation time 537221521277 ps
CPU time 808.36 seconds
Started Jun 21 06:52:12 PM PDT 24
Finished Jun 21 07:05:43 PM PDT 24
Peak memory 202240 kb
Host smart-c7e0c2ed-b1d6-47c4-bc54-d5e3d1b77e50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889414171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.889414171
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1512035991
Short name T317
Test name
Test status
Simulation time 166293338607 ps
CPU time 82.47 seconds
Started Jun 21 06:52:10 PM PDT 24
Finished Jun 21 06:53:35 PM PDT 24
Peak memory 202240 kb
Host smart-cd5909d1-2fa6-4c3a-a8c0-99ee6da69f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512035991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1512035991
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2451100541
Short name T756
Test name
Test status
Simulation time 162022847457 ps
CPU time 78.9 seconds
Started Jun 21 06:52:00 PM PDT 24
Finished Jun 21 06:53:22 PM PDT 24
Peak memory 202176 kb
Host smart-ae0e2abd-7aca-4631-b12c-821342b7a7f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451100541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2451100541
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3144361070
Short name T606
Test name
Test status
Simulation time 328162757374 ps
CPU time 192.06 seconds
Started Jun 21 06:52:01 PM PDT 24
Finished Jun 21 06:55:17 PM PDT 24
Peak memory 202292 kb
Host smart-709e6113-2b71-4f2d-84c7-f3bed48c36c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144361070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3144361070
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1528940402
Short name T540
Test name
Test status
Simulation time 197300093722 ps
CPU time 124.24 seconds
Started Jun 21 06:52:10 PM PDT 24
Finished Jun 21 06:54:17 PM PDT 24
Peak memory 202312 kb
Host smart-a4eef7b2-979e-4006-9b82-077c45252077
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528940402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1528940402
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.512395012
Short name T739
Test name
Test status
Simulation time 193682151139 ps
CPU time 411.53 seconds
Started Jun 21 06:52:10 PM PDT 24
Finished Jun 21 06:59:04 PM PDT 24
Peak memory 202344 kb
Host smart-04baab14-6e51-49e5-a886-1a1a4dc72a14
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512395012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.512395012
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1585005969
Short name T199
Test name
Test status
Simulation time 86891053479 ps
CPU time 449.94 seconds
Started Jun 21 06:52:10 PM PDT 24
Finished Jun 21 06:59:43 PM PDT 24
Peak memory 202544 kb
Host smart-4872ad8d-c63f-4d6d-b0ea-f547f5c2b334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585005969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1585005969
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2759238276
Short name T408
Test name
Test status
Simulation time 25773853462 ps
CPU time 55.1 seconds
Started Jun 21 06:52:09 PM PDT 24
Finished Jun 21 06:53:07 PM PDT 24
Peak memory 202084 kb
Host smart-d3b245b3-38df-4c06-a032-1f0c755778ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759238276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2759238276
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3446629309
Short name T487
Test name
Test status
Simulation time 3214496248 ps
CPU time 2.25 seconds
Started Jun 21 06:52:09 PM PDT 24
Finished Jun 21 06:52:14 PM PDT 24
Peak memory 202036 kb
Host smart-848b82b3-aa6d-4c9f-90ec-08ee2ceb0387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446629309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3446629309
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2286599393
Short name T631
Test name
Test status
Simulation time 5734165034 ps
CPU time 4.01 seconds
Started Jun 21 06:52:04 PM PDT 24
Finished Jun 21 06:52:12 PM PDT 24
Peak memory 202048 kb
Host smart-6ad5fb1a-6fa8-4ec3-ad34-de94b602093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286599393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2286599393
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1881965156
Short name T513
Test name
Test status
Simulation time 174060907760 ps
CPU time 208.58 seconds
Started Jun 21 06:52:11 PM PDT 24
Finished Jun 21 06:55:42 PM PDT 24
Peak memory 202284 kb
Host smart-02e02cb2-7560-48a9-a893-3df2a6d70b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881965156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1881965156
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.522472359
Short name T42
Test name
Test status
Simulation time 28480082082 ps
CPU time 60.79 seconds
Started Jun 21 06:52:08 PM PDT 24
Finished Jun 21 06:53:12 PM PDT 24
Peak memory 210608 kb
Host smart-2069ba95-f2c1-47b9-87f5-0555a77de00b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522472359 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.522472359
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.674341121
Short name T686
Test name
Test status
Simulation time 552628525 ps
CPU time 0.92 seconds
Started Jun 21 06:52:19 PM PDT 24
Finished Jun 21 06:52:23 PM PDT 24
Peak memory 201944 kb
Host smart-b9742de0-5473-4710-8d80-3dd7811012de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674341121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.674341121
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2877347166
Short name T560
Test name
Test status
Simulation time 170212525736 ps
CPU time 108.67 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:54:12 PM PDT 24
Peak memory 202208 kb
Host smart-8dcb5902-22db-4914-ad97-eda7671fd359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877347166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2877347166
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.604936509
Short name T545
Test name
Test status
Simulation time 163380149910 ps
CPU time 398.12 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:59:02 PM PDT 24
Peak memory 202124 kb
Host smart-a6a2a178-2154-4968-a2c0-a9d0ba932b5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=604936509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.604936509
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2262025824
Short name T129
Test name
Test status
Simulation time 489568228447 ps
CPU time 163.33 seconds
Started Jun 21 06:52:12 PM PDT 24
Finished Jun 21 06:54:57 PM PDT 24
Peak memory 202244 kb
Host smart-5be9d790-8c68-4f55-bfbc-2f2b8aa63009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262025824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2262025824
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.694256147
Short name T549
Test name
Test status
Simulation time 170108130661 ps
CPU time 109.9 seconds
Started Jun 21 06:52:19 PM PDT 24
Finished Jun 21 06:54:12 PM PDT 24
Peak memory 202204 kb
Host smart-aec5ad38-6456-4736-a83c-68e7dd405a36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=694256147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.694256147
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3502344148
Short name T299
Test name
Test status
Simulation time 373120024430 ps
CPU time 206.01 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:55:49 PM PDT 24
Peak memory 202300 kb
Host smart-90b086a5-1d7e-4846-80bb-03ec7e2091cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502344148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3502344148
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2980366095
Short name T687
Test name
Test status
Simulation time 405117995945 ps
CPU time 832.01 seconds
Started Jun 21 06:52:19 PM PDT 24
Finished Jun 21 07:06:14 PM PDT 24
Peak memory 202276 kb
Host smart-a54d62cb-0d02-4fe9-9742-660177882698
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980366095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2980366095
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2721142938
Short name T207
Test name
Test status
Simulation time 88449071981 ps
CPU time 478.02 seconds
Started Jun 21 06:52:18 PM PDT 24
Finished Jun 21 07:00:19 PM PDT 24
Peak memory 202600 kb
Host smart-fe8e153b-a4ad-4a71-9d01-6dd54c27fcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721142938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2721142938
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1123662387
Short name T419
Test name
Test status
Simulation time 26885499926 ps
CPU time 33.38 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:52:56 PM PDT 24
Peak memory 202156 kb
Host smart-80b3ff5f-3906-4eb2-9fc8-0d05b8268e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123662387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1123662387
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.212867511
Short name T484
Test name
Test status
Simulation time 4833510046 ps
CPU time 2.04 seconds
Started Jun 21 06:52:21 PM PDT 24
Finished Jun 21 06:52:27 PM PDT 24
Peak memory 202060 kb
Host smart-ec253cea-037e-4724-b0c0-682830aa732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212867511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.212867511
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3476135656
Short name T454
Test name
Test status
Simulation time 6065336007 ps
CPU time 1.6 seconds
Started Jun 21 06:52:08 PM PDT 24
Finished Jun 21 06:52:13 PM PDT 24
Peak memory 202040 kb
Host smart-429fd264-964b-4bbd-a933-7ba9d318a436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476135656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3476135656
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2342003551
Short name T424
Test name
Test status
Simulation time 204612002530 ps
CPU time 471.76 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 07:00:15 PM PDT 24
Peak memory 202292 kb
Host smart-66886752-5295-457b-a20b-0a72ef16b4d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342003551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2342003551
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1197148125
Short name T604
Test name
Test status
Simulation time 122186346141 ps
CPU time 196.51 seconds
Started Jun 21 06:52:19 PM PDT 24
Finished Jun 21 06:55:39 PM PDT 24
Peak memory 202764 kb
Host smart-193d126f-3b19-4af1-90bb-760f8bde59bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197148125 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1197148125
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1482369132
Short name T447
Test name
Test status
Simulation time 300342541 ps
CPU time 1.02 seconds
Started Jun 21 06:50:58 PM PDT 24
Finished Jun 21 06:51:03 PM PDT 24
Peak memory 201892 kb
Host smart-2f345c19-53bc-420a-bb49-c10c4df3f0b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482369132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1482369132
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3252535684
Short name T765
Test name
Test status
Simulation time 350252569732 ps
CPU time 441.4 seconds
Started Jun 21 06:50:53 PM PDT 24
Finished Jun 21 06:58:20 PM PDT 24
Peak memory 202184 kb
Host smart-8dc7b40e-85d3-4ed2-8792-aa81897721fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252535684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3252535684
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1037089266
Short name T279
Test name
Test status
Simulation time 495041043140 ps
CPU time 897.67 seconds
Started Jun 21 06:51:02 PM PDT 24
Finished Jun 21 07:06:03 PM PDT 24
Peak memory 202304 kb
Host smart-1d1fb58e-7b32-431f-90ab-82e5d9e402c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037089266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1037089266
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1133555405
Short name T499
Test name
Test status
Simulation time 486643755749 ps
CPU time 285.73 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 06:55:46 PM PDT 24
Peak memory 202192 kb
Host smart-62902486-04c3-4aac-9ba8-2cc12cf75963
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133555405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1133555405
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1111367528
Short name T301
Test name
Test status
Simulation time 506018769108 ps
CPU time 959.15 seconds
Started Jun 21 06:50:58 PM PDT 24
Finished Jun 21 07:07:02 PM PDT 24
Peak memory 202168 kb
Host smart-4f8a3fbb-a0c5-4246-b742-3ddada739511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111367528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1111367528
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.355416040
Short name T636
Test name
Test status
Simulation time 335031417513 ps
CPU time 96.41 seconds
Started Jun 21 06:50:55 PM PDT 24
Finished Jun 21 06:52:37 PM PDT 24
Peak memory 202192 kb
Host smart-b47dfdc6-c7ad-4962-9c09-1597d7cc8848
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=355416040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.355416040
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.697449918
Short name T768
Test name
Test status
Simulation time 349298004192 ps
CPU time 820.01 seconds
Started Jun 21 06:51:03 PM PDT 24
Finished Jun 21 07:04:46 PM PDT 24
Peak memory 202220 kb
Host smart-1ce64846-1c2a-487c-a751-ffd06ef4819f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697449918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.697449918
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3765627629
Short name T602
Test name
Test status
Simulation time 196158470019 ps
CPU time 435.14 seconds
Started Jun 21 06:50:53 PM PDT 24
Finished Jun 21 06:58:14 PM PDT 24
Peak memory 202200 kb
Host smart-80ecbb15-ff8b-4c90-a8c0-71497c096b3a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765627629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3765627629
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1922229211
Short name T773
Test name
Test status
Simulation time 108906162554 ps
CPU time 564.85 seconds
Started Jun 21 06:51:03 PM PDT 24
Finished Jun 21 07:00:31 PM PDT 24
Peak memory 202532 kb
Host smart-6f7c2183-8d03-4077-aa9f-5e75c7b1a357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922229211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1922229211
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1867136704
Short name T381
Test name
Test status
Simulation time 42227106416 ps
CPU time 25.38 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 06:51:25 PM PDT 24
Peak memory 202028 kb
Host smart-5ef777c0-635a-4788-97fe-aaf4f19db303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867136704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1867136704
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3618917453
Short name T740
Test name
Test status
Simulation time 4109424383 ps
CPU time 2.76 seconds
Started Jun 21 06:50:56 PM PDT 24
Finished Jun 21 06:51:04 PM PDT 24
Peak memory 202048 kb
Host smart-f4adc951-1e8d-4a7d-97a5-db6e1f2cb46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618917453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3618917453
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1397072907
Short name T66
Test name
Test status
Simulation time 7525621981 ps
CPU time 5.31 seconds
Started Jun 21 06:50:57 PM PDT 24
Finished Jun 21 06:51:07 PM PDT 24
Peak memory 218828 kb
Host smart-b327dab8-5994-4cf2-8059-326b60b599a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397072907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1397072907
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4177022849
Short name T192
Test name
Test status
Simulation time 6081568364 ps
CPU time 7.64 seconds
Started Jun 21 06:50:53 PM PDT 24
Finished Jun 21 06:51:06 PM PDT 24
Peak memory 202036 kb
Host smart-f0812f8a-7786-446f-9a2b-1bd07421a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177022849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4177022849
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3633221659
Short name T34
Test name
Test status
Simulation time 396921578366 ps
CPU time 132.9 seconds
Started Jun 21 06:50:53 PM PDT 24
Finished Jun 21 06:53:11 PM PDT 24
Peak memory 202308 kb
Host smart-1053c8a0-9db9-49cf-8720-9226238d91c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633221659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3633221659
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1456425835
Short name T63
Test name
Test status
Simulation time 179937127220 ps
CPU time 278.33 seconds
Started Jun 21 06:50:55 PM PDT 24
Finished Jun 21 06:55:39 PM PDT 24
Peak memory 210916 kb
Host smart-9374dbd1-60c5-415e-83ef-c2492ad94015
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456425835 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1456425835
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3638045137
Short name T302
Test name
Test status
Simulation time 493691282348 ps
CPU time 847.49 seconds
Started Jun 21 06:52:19 PM PDT 24
Finished Jun 21 07:06:30 PM PDT 24
Peak memory 202324 kb
Host smart-4e81c31f-2a9e-4fd2-bef0-8f900a1e8040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638045137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3638045137
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3657516531
Short name T353
Test name
Test status
Simulation time 333075841874 ps
CPU time 426.89 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:59:31 PM PDT 24
Peak memory 202228 kb
Host smart-f8028257-37a4-497a-a034-b87eba4eae5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657516531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3657516531
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.235161580
Short name T667
Test name
Test status
Simulation time 328901435636 ps
CPU time 708.3 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 07:04:12 PM PDT 24
Peak memory 202196 kb
Host smart-9b89c00a-17aa-4a54-a4af-41b826a81e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235161580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.235161580
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.35100521
Short name T676
Test name
Test status
Simulation time 332924449205 ps
CPU time 730.92 seconds
Started Jun 21 06:52:19 PM PDT 24
Finished Jun 21 07:04:33 PM PDT 24
Peak memory 202300 kb
Host smart-d4221855-51f9-4114-a693-666005a517fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=35100521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed
.35100521
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2275665490
Short name T324
Test name
Test status
Simulation time 421020881426 ps
CPU time 461.32 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 07:00:04 PM PDT 24
Peak memory 202236 kb
Host smart-1632bf74-0894-40f9-8ece-6f9fce3551cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275665490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2275665490
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3437164923
Short name T409
Test name
Test status
Simulation time 202060947017 ps
CPU time 231.63 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:56:15 PM PDT 24
Peak memory 202224 kb
Host smart-fe2be76e-5c21-4489-929d-4fe19dd3887c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437164923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3437164923
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2924701757
Short name T751
Test name
Test status
Simulation time 106127554884 ps
CPU time 512.25 seconds
Started Jun 21 06:52:17 PM PDT 24
Finished Jun 21 07:00:52 PM PDT 24
Peak memory 202544 kb
Host smart-091f981e-42ad-4c10-9276-9c005c975c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924701757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2924701757
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.492526143
Short name T396
Test name
Test status
Simulation time 25929647612 ps
CPU time 29.08 seconds
Started Jun 21 06:52:18 PM PDT 24
Finished Jun 21 06:52:49 PM PDT 24
Peak memory 201992 kb
Host smart-f4f6e430-3c22-4d7e-a8b0-da35d69e8c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492526143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.492526143
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2867670073
Short name T752
Test name
Test status
Simulation time 4417473384 ps
CPU time 6.3 seconds
Started Jun 21 06:52:20 PM PDT 24
Finished Jun 21 06:52:30 PM PDT 24
Peak memory 202060 kb
Host smart-bba052d7-3323-4364-aa0e-2c0e927235dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867670073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2867670073
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.98533717
Short name T429
Test name
Test status
Simulation time 5895488860 ps
CPU time 8.85 seconds
Started Jun 21 06:52:19 PM PDT 24
Finished Jun 21 06:52:31 PM PDT 24
Peak memory 202068 kb
Host smart-53072427-774b-4f52-9e52-8370278276ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98533717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.98533717
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3709925419
Short name T139
Test name
Test status
Simulation time 190477468470 ps
CPU time 121.61 seconds
Started Jun 21 06:52:17 PM PDT 24
Finished Jun 21 06:54:21 PM PDT 24
Peak memory 202304 kb
Host smart-ec61e497-b64b-4e77-a914-455f1e8f96a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709925419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3709925419
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2281435912
Short name T14
Test name
Test status
Simulation time 24477371286 ps
CPU time 29.86 seconds
Started Jun 21 06:52:18 PM PDT 24
Finished Jun 21 06:52:51 PM PDT 24
Peak memory 202352 kb
Host smart-46391d29-8b30-4b2f-9461-730d8c089ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281435912 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2281435912
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.308203913
Short name T471
Test name
Test status
Simulation time 528207470 ps
CPU time 0.71 seconds
Started Jun 21 06:52:34 PM PDT 24
Finished Jun 21 06:52:36 PM PDT 24
Peak memory 201928 kb
Host smart-ab0c6e46-4f77-4a8c-b3d0-498022aa71ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308203913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.308203913
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.89474148
Short name T579
Test name
Test status
Simulation time 245654621619 ps
CPU time 28.93 seconds
Started Jun 21 06:52:28 PM PDT 24
Finished Jun 21 06:52:59 PM PDT 24
Peak memory 202304 kb
Host smart-de41bd62-dd37-4427-8055-44091b3ed31b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89474148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gatin
g.89474148
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3010006296
Short name T724
Test name
Test status
Simulation time 507766003458 ps
CPU time 295.5 seconds
Started Jun 21 06:52:29 PM PDT 24
Finished Jun 21 06:57:27 PM PDT 24
Peak memory 202308 kb
Host smart-9fc960b2-4c8b-4374-9843-8e59c2d0cbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010006296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3010006296
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1619103915
Short name T413
Test name
Test status
Simulation time 163322766625 ps
CPU time 113.3 seconds
Started Jun 21 06:52:27 PM PDT 24
Finished Jun 21 06:54:22 PM PDT 24
Peak memory 202268 kb
Host smart-609e1d68-b853-435d-839d-5cf374ce9432
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619103915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1619103915
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3830725761
Short name T9
Test name
Test status
Simulation time 160380849721 ps
CPU time 97.31 seconds
Started Jun 21 06:52:31 PM PDT 24
Finished Jun 21 06:54:10 PM PDT 24
Peak memory 202404 kb
Host smart-7d12ec32-ff6d-417f-8eff-06e6a1da6333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830725761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3830725761
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.322478185
Short name T186
Test name
Test status
Simulation time 320285698839 ps
CPU time 197.64 seconds
Started Jun 21 06:52:35 PM PDT 24
Finished Jun 21 06:55:54 PM PDT 24
Peak memory 202192 kb
Host smart-2161665e-180b-4644-99c6-5b2c4bd7825b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=322478185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.322478185
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2091521838
Short name T485
Test name
Test status
Simulation time 340509645502 ps
CPU time 807.92 seconds
Started Jun 21 06:52:28 PM PDT 24
Finished Jun 21 07:05:59 PM PDT 24
Peak memory 202236 kb
Host smart-9dacece4-a7b5-4130-b299-153c7d53219f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091521838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2091521838
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1902881194
Short name T455
Test name
Test status
Simulation time 191751506815 ps
CPU time 97.57 seconds
Started Jun 21 06:52:31 PM PDT 24
Finished Jun 21 06:54:10 PM PDT 24
Peak memory 202236 kb
Host smart-159946a5-0356-480b-9826-0a9724c13737
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902881194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1902881194
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1324650738
Short name T337
Test name
Test status
Simulation time 112626105878 ps
CPU time 492.83 seconds
Started Jun 21 06:52:27 PM PDT 24
Finished Jun 21 07:00:42 PM PDT 24
Peak memory 202548 kb
Host smart-4459107c-1ab1-4e20-b259-0a03c7ef0fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324650738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1324650738
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1562422749
Short name T136
Test name
Test status
Simulation time 27629315337 ps
CPU time 15.12 seconds
Started Jun 21 06:52:29 PM PDT 24
Finished Jun 21 06:52:46 PM PDT 24
Peak memory 202068 kb
Host smart-38e59a1d-30a7-4d61-9e1c-95f313724d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562422749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1562422749
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1745671220
Short name T749
Test name
Test status
Simulation time 5065469244 ps
CPU time 12 seconds
Started Jun 21 06:52:30 PM PDT 24
Finished Jun 21 06:52:44 PM PDT 24
Peak memory 202056 kb
Host smart-5a53fcbb-850b-4f3d-9607-c942a7950a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745671220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1745671220
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3192142921
Short name T782
Test name
Test status
Simulation time 5748811029 ps
CPU time 7.48 seconds
Started Jun 21 06:52:28 PM PDT 24
Finished Jun 21 06:52:37 PM PDT 24
Peak memory 202024 kb
Host smart-9f73495b-12f0-49af-b28b-f0c5ceed1879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192142921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3192142921
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.656918561
Short name T698
Test name
Test status
Simulation time 755893518415 ps
CPU time 728.93 seconds
Started Jun 21 06:52:29 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 210732 kb
Host smart-d77e1870-72f4-4dfa-983d-bb6f4d37330d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656918561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
656918561
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2257645917
Short name T270
Test name
Test status
Simulation time 65354033772 ps
CPU time 165.83 seconds
Started Jun 21 06:52:29 PM PDT 24
Finished Jun 21 06:55:17 PM PDT 24
Peak memory 210936 kb
Host smart-574d1296-42a8-4f1d-9a6d-f60f4d36798d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257645917 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2257645917
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1178238263
Short name T172
Test name
Test status
Simulation time 434884489 ps
CPU time 1.58 seconds
Started Jun 21 06:52:43 PM PDT 24
Finished Jun 21 06:52:48 PM PDT 24
Peak memory 201932 kb
Host smart-cd429c70-bb6a-4bde-a204-9644f1b8186c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178238263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1178238263
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3090151582
Short name T682
Test name
Test status
Simulation time 332395505044 ps
CPU time 142.67 seconds
Started Jun 21 06:52:44 PM PDT 24
Finished Jun 21 06:55:10 PM PDT 24
Peak memory 202312 kb
Host smart-45fb6426-001b-4dfd-b9f5-79528333fb5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090151582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3090151582
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3798146359
Short name T315
Test name
Test status
Simulation time 164846595596 ps
CPU time 84.18 seconds
Started Jun 21 06:52:42 PM PDT 24
Finished Jun 21 06:54:09 PM PDT 24
Peak memory 202276 kb
Host smart-3a9ac72d-c78f-4e87-b2cc-e0a6e4843ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798146359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3798146359
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2248673296
Short name T691
Test name
Test status
Simulation time 161687098945 ps
CPU time 62.4 seconds
Started Jun 21 06:52:34 PM PDT 24
Finished Jun 21 06:53:38 PM PDT 24
Peak memory 202312 kb
Host smart-78548d11-521b-425e-99b0-3651576eab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248673296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2248673296
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3719440291
Short name T780
Test name
Test status
Simulation time 327748410122 ps
CPU time 282.89 seconds
Started Jun 21 06:52:29 PM PDT 24
Finished Jun 21 06:57:14 PM PDT 24
Peak memory 202204 kb
Host smart-9560a5bd-00de-40be-9703-4219fd184e3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719440291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3719440291
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.4150278600
Short name T254
Test name
Test status
Simulation time 324050165609 ps
CPU time 378.94 seconds
Started Jun 21 06:52:33 PM PDT 24
Finished Jun 21 06:58:53 PM PDT 24
Peak memory 202312 kb
Host smart-07e286be-32fe-4ffc-888b-eb37ef0beec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150278600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.4150278600
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1341457164
Short name T783
Test name
Test status
Simulation time 332144037305 ps
CPU time 776.16 seconds
Started Jun 21 06:52:28 PM PDT 24
Finished Jun 21 07:05:27 PM PDT 24
Peak memory 202228 kb
Host smart-6c9aec97-0548-4df0-abab-c9721b464d7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341457164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1341457164
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2382301646
Short name T784
Test name
Test status
Simulation time 564759524709 ps
CPU time 141.89 seconds
Started Jun 21 06:52:43 PM PDT 24
Finished Jun 21 06:55:09 PM PDT 24
Peak memory 202404 kb
Host smart-35184a55-b34f-469e-a25b-cc3ae4291f71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382301646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2382301646
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1194363088
Short name T418
Test name
Test status
Simulation time 596362127219 ps
CPU time 699.8 seconds
Started Jun 21 06:52:44 PM PDT 24
Finished Jun 21 07:04:27 PM PDT 24
Peak memory 202216 kb
Host smart-cd6b1289-be7a-4f3d-aed8-5ffe058b1d4e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194363088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1194363088
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3253082400
Short name T521
Test name
Test status
Simulation time 63480713404 ps
CPU time 243.45 seconds
Started Jun 21 06:52:43 PM PDT 24
Finished Jun 21 06:56:50 PM PDT 24
Peak memory 202564 kb
Host smart-f6656d84-4019-4b17-ba9a-573ef0dd0a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253082400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3253082400
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3074190641
Short name T378
Test name
Test status
Simulation time 35754256413 ps
CPU time 6.48 seconds
Started Jun 21 06:52:42 PM PDT 24
Finished Jun 21 06:52:51 PM PDT 24
Peak memory 202064 kb
Host smart-ea2d0c00-9003-4767-a296-015b775131b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074190641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3074190641
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1210860227
Short name T343
Test name
Test status
Simulation time 4117780485 ps
CPU time 9.86 seconds
Started Jun 21 06:52:43 PM PDT 24
Finished Jun 21 06:52:56 PM PDT 24
Peak memory 202060 kb
Host smart-63f432a2-87c2-4dad-83a0-02580b14cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210860227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1210860227
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.974634267
Short name T436
Test name
Test status
Simulation time 6105772948 ps
CPU time 4.31 seconds
Started Jun 21 06:52:28 PM PDT 24
Finished Jun 21 06:52:34 PM PDT 24
Peak memory 201992 kb
Host smart-9866796e-2c37-40c3-bf48-8360a8b69800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974634267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.974634267
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3354557838
Short name T776
Test name
Test status
Simulation time 169077314166 ps
CPU time 208.1 seconds
Started Jun 21 06:52:43 PM PDT 24
Finished Jun 21 06:56:14 PM PDT 24
Peak memory 202272 kb
Host smart-66099b50-7996-4e2c-926d-a51ee380034f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354557838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3354557838
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.379266107
Short name T197
Test name
Test status
Simulation time 91853136108 ps
CPU time 183.51 seconds
Started Jun 21 06:52:43 PM PDT 24
Finished Jun 21 06:55:50 PM PDT 24
Peak memory 218292 kb
Host smart-7ea10434-eaf1-4ed6-9094-fce6cbb5cced
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379266107 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.379266107
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1145014306
Short name T700
Test name
Test status
Simulation time 464887209 ps
CPU time 0.89 seconds
Started Jun 21 06:52:56 PM PDT 24
Finished Jun 21 06:53:00 PM PDT 24
Peak memory 201884 kb
Host smart-d5b69f11-efaf-4971-9d73-af3290c33aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145014306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1145014306
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.654844607
Short name T323
Test name
Test status
Simulation time 346450522468 ps
CPU time 188.85 seconds
Started Jun 21 06:52:54 PM PDT 24
Finished Jun 21 06:56:07 PM PDT 24
Peak memory 202152 kb
Host smart-c4f66e07-6b89-4dff-ad03-61a010a44a33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654844607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.654844607
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1083321143
Short name T329
Test name
Test status
Simulation time 518678368214 ps
CPU time 80.87 seconds
Started Jun 21 06:52:51 PM PDT 24
Finished Jun 21 06:54:14 PM PDT 24
Peak memory 202184 kb
Host smart-07bcbe7f-ebe0-4fec-8730-245c85c5ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083321143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1083321143
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.4131787885
Short name T470
Test name
Test status
Simulation time 321369318844 ps
CPU time 203.24 seconds
Started Jun 21 06:52:42 PM PDT 24
Finished Jun 21 06:56:09 PM PDT 24
Peak memory 202272 kb
Host smart-8c7f64a4-3db8-42f4-9f5a-e17f0c09ba48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131787885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.4131787885
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1376742134
Short name T699
Test name
Test status
Simulation time 490813724401 ps
CPU time 1147.5 seconds
Started Jun 21 06:52:42 PM PDT 24
Finished Jun 21 07:11:53 PM PDT 24
Peak memory 202256 kb
Host smart-09c3c832-95cc-4a48-adec-77a5d41ac7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376742134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1376742134
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2816256761
Short name T692
Test name
Test status
Simulation time 487686227504 ps
CPU time 169.11 seconds
Started Jun 21 06:52:43 PM PDT 24
Finished Jun 21 06:55:35 PM PDT 24
Peak memory 202288 kb
Host smart-b22e29d5-5513-4a13-abd1-cd60a5b97260
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816256761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2816256761
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3574278449
Short name T590
Test name
Test status
Simulation time 165105155811 ps
CPU time 386.55 seconds
Started Jun 21 06:52:43 PM PDT 24
Finished Jun 21 06:59:13 PM PDT 24
Peak memory 202248 kb
Host smart-9c79c792-a0cf-4e2a-817b-a43d5d8681d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574278449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3574278449
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2462697925
Short name T568
Test name
Test status
Simulation time 201787569562 ps
CPU time 223.64 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 06:56:40 PM PDT 24
Peak memory 202212 kb
Host smart-318dc880-5cab-481a-b079-40e57aa8595c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462697925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2462697925
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.511487213
Short name T358
Test name
Test status
Simulation time 32913914073 ps
CPU time 59.27 seconds
Started Jun 21 06:52:54 PM PDT 24
Finished Jun 21 06:53:57 PM PDT 24
Peak memory 201908 kb
Host smart-e73995c9-8d9f-4f55-8cfe-f21965a3e5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511487213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.511487213
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.4121623266
Short name T790
Test name
Test status
Simulation time 3930275753 ps
CPU time 10.21 seconds
Started Jun 21 06:52:52 PM PDT 24
Finished Jun 21 06:53:05 PM PDT 24
Peak memory 202048 kb
Host smart-397f8f25-b082-4359-a854-b145c8f0fbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121623266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4121623266
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2869788854
Short name T346
Test name
Test status
Simulation time 5986864869 ps
CPU time 8.49 seconds
Started Jun 21 06:52:44 PM PDT 24
Finished Jun 21 06:52:56 PM PDT 24
Peak memory 202028 kb
Host smart-5568aaf2-65d8-4796-8826-42cdf2fc3af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869788854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2869788854
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1957723704
Short name T546
Test name
Test status
Simulation time 203994502763 ps
CPU time 30.97 seconds
Started Jun 21 06:52:55 PM PDT 24
Finished Jun 21 06:53:30 PM PDT 24
Peak memory 202172 kb
Host smart-ba2e60bb-e39d-470f-b565-2afe238ac6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957723704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1957723704
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1498990158
Short name T292
Test name
Test status
Simulation time 31341053741 ps
CPU time 100.83 seconds
Started Jun 21 06:52:52 PM PDT 24
Finished Jun 21 06:54:36 PM PDT 24
Peak memory 218368 kb
Host smart-ee9bea22-d2f5-4408-9517-c96e94abfcf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498990158 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1498990158
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1178556972
Short name T25
Test name
Test status
Simulation time 418454493 ps
CPU time 0.86 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 06:52:57 PM PDT 24
Peak memory 201944 kb
Host smart-4996bf4b-7735-402e-9893-b987f8f1be00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178556972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1178556972
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1651659441
Short name T124
Test name
Test status
Simulation time 423186606791 ps
CPU time 911.26 seconds
Started Jun 21 06:52:54 PM PDT 24
Finished Jun 21 07:08:08 PM PDT 24
Peak memory 202176 kb
Host smart-0611c74e-c77a-4a06-a17d-331e7c925894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651659441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1651659441
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3531265250
Short name T239
Test name
Test status
Simulation time 489087157385 ps
CPU time 1009.69 seconds
Started Jun 21 06:52:56 PM PDT 24
Finished Jun 21 07:09:49 PM PDT 24
Peak memory 202216 kb
Host smart-65d677db-5168-4e45-ba3d-ccd0d2f2d7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531265250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3531265250
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.403310453
Short name T473
Test name
Test status
Simulation time 160694768024 ps
CPU time 171.32 seconds
Started Jun 21 06:52:55 PM PDT 24
Finished Jun 21 06:55:50 PM PDT 24
Peak memory 202204 kb
Host smart-f94adc65-8d93-4ad0-adfd-80e83cb3f0a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=403310453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.403310453
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.695328411
Short name T121
Test name
Test status
Simulation time 489068716589 ps
CPU time 288.18 seconds
Started Jun 21 06:52:54 PM PDT 24
Finished Jun 21 06:57:45 PM PDT 24
Peak memory 202216 kb
Host smart-33977a17-8837-4610-80b2-b70629225e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695328411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.695328411
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.533297960
Short name T609
Test name
Test status
Simulation time 164848928722 ps
CPU time 187.64 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 06:56:04 PM PDT 24
Peak memory 202308 kb
Host smart-4b393c2b-6bdb-4476-bdbe-5b8af4f0482b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=533297960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.533297960
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.357797307
Short name T140
Test name
Test status
Simulation time 555910035783 ps
CPU time 325.45 seconds
Started Jun 21 06:52:56 PM PDT 24
Finished Jun 21 06:58:26 PM PDT 24
Peak memory 202180 kb
Host smart-c68ed331-1f99-4260-89b4-54dc7795be28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357797307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.357797307
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.736468952
Short name T477
Test name
Test status
Simulation time 194506357697 ps
CPU time 218.68 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 06:56:34 PM PDT 24
Peak memory 202320 kb
Host smart-d5f799fb-2c59-4dfe-b07d-adef3fa90cc0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736468952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.736468952
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4288269415
Short name T427
Test name
Test status
Simulation time 46108469244 ps
CPU time 24.81 seconds
Started Jun 21 06:52:51 PM PDT 24
Finished Jun 21 06:53:18 PM PDT 24
Peak memory 202044 kb
Host smart-bd05e8db-3e6c-47d1-bd35-3f1c1fbf60de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288269415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4288269415
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2388070407
Short name T8
Test name
Test status
Simulation time 4425117510 ps
CPU time 11.55 seconds
Started Jun 21 06:52:54 PM PDT 24
Finished Jun 21 06:53:08 PM PDT 24
Peak memory 202052 kb
Host smart-941955fa-c4b7-4ea0-a4b7-06a8d0b3a52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388070407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2388070407
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1890102168
Short name T744
Test name
Test status
Simulation time 5842480024 ps
CPU time 4.4 seconds
Started Jun 21 06:52:55 PM PDT 24
Finished Jun 21 06:53:03 PM PDT 24
Peak memory 202020 kb
Host smart-0f170166-4d97-4ace-b274-d26d48897ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890102168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1890102168
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.548021551
Short name T339
Test name
Test status
Simulation time 434230051705 ps
CPU time 1331.67 seconds
Started Jun 21 06:52:51 PM PDT 24
Finished Jun 21 07:15:05 PM PDT 24
Peak memory 210792 kb
Host smart-2d694ea8-89e5-4906-b1ca-2dc05de47371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548021551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
548021551
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1958973034
Short name T543
Test name
Test status
Simulation time 493198203 ps
CPU time 1.42 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 06:53:08 PM PDT 24
Peak memory 201932 kb
Host smart-3546648c-b51f-45f9-88f1-683bc109ef83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958973034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1958973034
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.218844026
Short name T663
Test name
Test status
Simulation time 203085201128 ps
CPU time 339.28 seconds
Started Jun 21 06:52:56 PM PDT 24
Finished Jun 21 06:58:39 PM PDT 24
Peak memory 202272 kb
Host smart-5ebc43b0-5ee1-4d81-a617-30a9bba005ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218844026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.218844026
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3958200791
Short name T509
Test name
Test status
Simulation time 318588219507 ps
CPU time 771.83 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 07:05:48 PM PDT 24
Peak memory 202232 kb
Host smart-764163f2-f75f-4bce-af14-199e91bfd6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958200791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3958200791
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1387879878
Short name T449
Test name
Test status
Simulation time 159041365744 ps
CPU time 96.07 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 06:54:32 PM PDT 24
Peak memory 202276 kb
Host smart-69288320-4fe5-4987-a98c-d9117876ba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387879878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1387879878
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3565110358
Short name T361
Test name
Test status
Simulation time 326534119282 ps
CPU time 355.55 seconds
Started Jun 21 06:52:54 PM PDT 24
Finished Jun 21 06:58:53 PM PDT 24
Peak memory 202208 kb
Host smart-e119efed-a952-4e3f-8824-5beac039cd99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565110358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3565110358
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.563001185
Short name T171
Test name
Test status
Simulation time 165638075476 ps
CPU time 196.73 seconds
Started Jun 21 06:52:57 PM PDT 24
Finished Jun 21 06:56:17 PM PDT 24
Peak memory 202276 kb
Host smart-3d8ac409-2db8-4baa-8e1b-24f04ebb29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563001185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.563001185
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4178842911
Short name T392
Test name
Test status
Simulation time 337339320254 ps
CPU time 813.73 seconds
Started Jun 21 06:52:55 PM PDT 24
Finished Jun 21 07:06:33 PM PDT 24
Peak memory 202268 kb
Host smart-18970e0c-db50-401d-b182-a67e1e7f9d18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178842911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.4178842911
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.622874149
Short name T601
Test name
Test status
Simulation time 190876880403 ps
CPU time 104.54 seconds
Started Jun 21 06:52:52 PM PDT 24
Finished Jun 21 06:54:39 PM PDT 24
Peak memory 202264 kb
Host smart-24389352-fb4f-4527-b165-ade79b05be04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622874149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.622874149
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1668401383
Short name T383
Test name
Test status
Simulation time 104256637682 ps
CPU time 393.23 seconds
Started Jun 21 06:52:56 PM PDT 24
Finished Jun 21 06:59:33 PM PDT 24
Peak memory 202520 kb
Host smart-120e219c-0f3e-4842-99e5-0b5fd1c6fbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668401383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1668401383
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2006342804
Short name T722
Test name
Test status
Simulation time 25595632198 ps
CPU time 16.87 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 06:53:14 PM PDT 24
Peak memory 202020 kb
Host smart-df5e9b79-a2aa-4eba-b624-8aa3edd54cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006342804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2006342804
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3237802289
Short name T457
Test name
Test status
Simulation time 4465538376 ps
CPU time 3.2 seconds
Started Jun 21 06:52:52 PM PDT 24
Finished Jun 21 06:52:58 PM PDT 24
Peak memory 202048 kb
Host smart-d2a7781b-44bc-4b40-b20b-dde2256110ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237802289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3237802289
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2703447304
Short name T174
Test name
Test status
Simulation time 6015099377 ps
CPU time 15.37 seconds
Started Jun 21 06:52:53 PM PDT 24
Finished Jun 21 06:53:12 PM PDT 24
Peak memory 202056 kb
Host smart-e85cfdbe-b1da-44a3-91df-f5530a8dc57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703447304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2703447304
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3534095474
Short name T522
Test name
Test status
Simulation time 286429369523 ps
CPU time 671.55 seconds
Started Jun 21 06:53:02 PM PDT 24
Finished Jun 21 07:04:16 PM PDT 24
Peak memory 202616 kb
Host smart-c55796e8-f26c-4442-834b-51813ddf24f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534095474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3534095474
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.146806052
Short name T565
Test name
Test status
Simulation time 112511565720 ps
CPU time 137.5 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 06:55:24 PM PDT 24
Peak memory 210540 kb
Host smart-57a1c672-053f-4df2-a665-64ae9392f226
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146806052 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.146806052
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.784007970
Short name T653
Test name
Test status
Simulation time 353293915 ps
CPU time 0.79 seconds
Started Jun 21 06:53:04 PM PDT 24
Finished Jun 21 06:53:08 PM PDT 24
Peak memory 201940 kb
Host smart-643d89b8-0c4a-4ec4-9487-ae5fb49bb38b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784007970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.784007970
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2621434051
Short name T453
Test name
Test status
Simulation time 171969312649 ps
CPU time 110.23 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 06:54:56 PM PDT 24
Peak memory 202184 kb
Host smart-2e24f0f5-5273-4266-8479-4eee1212a2e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621434051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2621434051
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1662583566
Short name T652
Test name
Test status
Simulation time 356316207933 ps
CPU time 806.06 seconds
Started Jun 21 06:53:01 PM PDT 24
Finished Jun 21 07:06:29 PM PDT 24
Peak memory 202244 kb
Host smart-864b484b-8db5-4d87-9137-62242d853249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662583566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1662583566
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3695526801
Short name T185
Test name
Test status
Simulation time 327919449684 ps
CPU time 192.78 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 06:56:19 PM PDT 24
Peak memory 202244 kb
Host smart-a54c07fa-ba30-4e2f-be81-8dd488d82290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695526801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3695526801
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.38315826
Short name T360
Test name
Test status
Simulation time 163192245164 ps
CPU time 224.36 seconds
Started Jun 21 06:53:04 PM PDT 24
Finished Jun 21 06:56:51 PM PDT 24
Peak memory 202296 kb
Host smart-48bd4e56-d752-47af-84b8-2345b8a24415
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=38315826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt
_fixed.38315826
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.4191398516
Short name T515
Test name
Test status
Simulation time 488415670487 ps
CPU time 332.05 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 06:58:38 PM PDT 24
Peak memory 202228 kb
Host smart-0300f3d5-43f9-4ba9-b4de-2c5a0ddb4917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191398516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.4191398516
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.294203862
Short name T1
Test name
Test status
Simulation time 334607893853 ps
CPU time 182.7 seconds
Started Jun 21 06:53:05 PM PDT 24
Finished Jun 21 06:56:11 PM PDT 24
Peak memory 201888 kb
Host smart-0f8bbf17-0805-4cf6-9614-502ea9bb5222
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=294203862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.294203862
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.186103500
Short name T684
Test name
Test status
Simulation time 198021948078 ps
CPU time 458.01 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 07:00:43 PM PDT 24
Peak memory 202224 kb
Host smart-4a5f39e4-8180-4665-a809-057d512ee239
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186103500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.186103500
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.4054357535
Short name T211
Test name
Test status
Simulation time 146596324545 ps
CPU time 709.08 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 07:04:55 PM PDT 24
Peak memory 202540 kb
Host smart-6503129d-17e1-46b8-a5b5-da596e879def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054357535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4054357535
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2290287776
Short name T466
Test name
Test status
Simulation time 26118485962 ps
CPU time 15.05 seconds
Started Jun 21 06:53:02 PM PDT 24
Finished Jun 21 06:53:18 PM PDT 24
Peak memory 202076 kb
Host smart-b48b9498-5d73-4fd6-bfd9-eaf7a13a3517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290287776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2290287776
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.180419354
Short name T600
Test name
Test status
Simulation time 4555848162 ps
CPU time 2.62 seconds
Started Jun 21 06:53:04 PM PDT 24
Finished Jun 21 06:53:09 PM PDT 24
Peak memory 202044 kb
Host smart-0c60e385-9dd7-4617-ad2e-741b2226d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180419354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.180419354
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1141166982
Short name T463
Test name
Test status
Simulation time 5971855794 ps
CPU time 1.6 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 06:53:07 PM PDT 24
Peak memory 202064 kb
Host smart-827cbbe0-b991-436a-8656-61c9c2a4ebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141166982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1141166982
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1678949587
Short name T309
Test name
Test status
Simulation time 467376614110 ps
CPU time 1257.95 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 07:14:04 PM PDT 24
Peak memory 213724 kb
Host smart-eef32c30-4b0a-42f9-840f-6bc47ac5a7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678949587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1678949587
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3334196178
Short name T38
Test name
Test status
Simulation time 188376955415 ps
CPU time 553.71 seconds
Started Jun 21 06:53:02 PM PDT 24
Finished Jun 21 07:02:19 PM PDT 24
Peak memory 218384 kb
Host smart-9001c189-db73-415c-bd9d-40aa1497f5e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334196178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3334196178
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.785800174
Short name T489
Test name
Test status
Simulation time 481186592 ps
CPU time 1.7 seconds
Started Jun 21 06:53:12 PM PDT 24
Finished Jun 21 06:53:16 PM PDT 24
Peak memory 201924 kb
Host smart-14376b22-2050-4d30-aed0-15b5496327a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785800174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.785800174
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2633070779
Short name T286
Test name
Test status
Simulation time 336147988792 ps
CPU time 403.92 seconds
Started Jun 21 06:53:15 PM PDT 24
Finished Jun 21 07:00:01 PM PDT 24
Peak memory 202296 kb
Host smart-3c9c9c64-c507-4534-b338-a87027b973df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633070779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2633070779
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1633427679
Short name T170
Test name
Test status
Simulation time 343100637944 ps
CPU time 781.06 seconds
Started Jun 21 06:53:13 PM PDT 24
Finished Jun 21 07:06:16 PM PDT 24
Peak memory 202236 kb
Host smart-594056d0-c84b-43df-a95b-c565802cfecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633427679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1633427679
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2000837644
Short name T737
Test name
Test status
Simulation time 168774655653 ps
CPU time 68.43 seconds
Started Jun 21 06:53:03 PM PDT 24
Finished Jun 21 06:54:15 PM PDT 24
Peak memory 202240 kb
Host smart-d7192d52-bbab-4a79-89f6-3f4af4bd5e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000837644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2000837644
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3782951682
Short name T359
Test name
Test status
Simulation time 329843470820 ps
CPU time 708.53 seconds
Started Jun 21 06:53:11 PM PDT 24
Finished Jun 21 07:05:02 PM PDT 24
Peak memory 202280 kb
Host smart-997a916f-2471-45c0-b19e-2671709d0208
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782951682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3782951682
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3475543621
Short name T405
Test name
Test status
Simulation time 164983311679 ps
CPU time 293.64 seconds
Started Jun 21 06:53:01 PM PDT 24
Finished Jun 21 06:57:56 PM PDT 24
Peak memory 202192 kb
Host smart-b4be7e6a-ef31-4fea-afcf-c1cfebdc3a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475543621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3475543621
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2762022260
Short name T481
Test name
Test status
Simulation time 495566946844 ps
CPU time 537.82 seconds
Started Jun 21 06:53:05 PM PDT 24
Finished Jun 21 07:02:06 PM PDT 24
Peak memory 202212 kb
Host smart-e8df217f-9d92-481f-b03f-68b2d4051088
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762022260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2762022260
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2950907031
Short name T775
Test name
Test status
Simulation time 408622194352 ps
CPU time 962.74 seconds
Started Jun 21 06:53:15 PM PDT 24
Finished Jun 21 07:09:20 PM PDT 24
Peak memory 202224 kb
Host smart-0b482db8-d296-4e13-9339-4ed2dd88db1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950907031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2950907031
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1444911248
Short name T562
Test name
Test status
Simulation time 97103233794 ps
CPU time 516.21 seconds
Started Jun 21 06:53:13 PM PDT 24
Finished Jun 21 07:01:51 PM PDT 24
Peak memory 202548 kb
Host smart-6922eae9-d4f8-4ed4-a3e0-533ddfdaea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444911248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1444911248
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.697619690
Short name T677
Test name
Test status
Simulation time 36282915859 ps
CPU time 41.34 seconds
Started Jun 21 06:53:12 PM PDT 24
Finished Jun 21 06:53:55 PM PDT 24
Peak memory 202072 kb
Host smart-5282b334-e61e-486c-a3f6-176997f3cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697619690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.697619690
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1270220323
Short name T415
Test name
Test status
Simulation time 4968148764 ps
CPU time 12.49 seconds
Started Jun 21 06:53:12 PM PDT 24
Finished Jun 21 06:53:27 PM PDT 24
Peak memory 202056 kb
Host smart-8bd04fb0-5b91-415a-9f8c-df5c295efb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270220323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1270220323
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2163580020
Short name T666
Test name
Test status
Simulation time 5906160801 ps
CPU time 14.04 seconds
Started Jun 21 06:53:02 PM PDT 24
Finished Jun 21 06:53:18 PM PDT 24
Peak memory 202052 kb
Host smart-2fa345cc-52dd-4261-bd9f-dae40c92c7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163580020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2163580020
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1697264059
Short name T660
Test name
Test status
Simulation time 384729185 ps
CPU time 0.76 seconds
Started Jun 21 06:53:24 PM PDT 24
Finished Jun 21 06:53:33 PM PDT 24
Peak memory 201900 kb
Host smart-d7fec7fe-e16c-404c-ac50-0f80788b039d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697264059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1697264059
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1273181586
Short name T234
Test name
Test status
Simulation time 327855581614 ps
CPU time 172.9 seconds
Started Jun 21 06:53:14 PM PDT 24
Finished Jun 21 06:56:10 PM PDT 24
Peak memory 202316 kb
Host smart-fa9db659-a523-4c55-b613-932e91075dba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273181586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1273181586
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.288672468
Short name T163
Test name
Test status
Simulation time 344708466469 ps
CPU time 204.98 seconds
Started Jun 21 06:53:23 PM PDT 24
Finished Jun 21 06:56:57 PM PDT 24
Peak memory 202212 kb
Host smart-2cc6a96e-3636-4806-ac26-67f52ed0db98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288672468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.288672468
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4150710369
Short name T244
Test name
Test status
Simulation time 328815769103 ps
CPU time 394.17 seconds
Started Jun 21 06:53:14 PM PDT 24
Finished Jun 21 06:59:51 PM PDT 24
Peak memory 202420 kb
Host smart-84a99561-4797-4a10-b8fd-9dd9a109a91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150710369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4150710369
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.366638866
Short name T344
Test name
Test status
Simulation time 169108186327 ps
CPU time 205.6 seconds
Started Jun 21 06:53:13 PM PDT 24
Finished Jun 21 06:56:41 PM PDT 24
Peak memory 202176 kb
Host smart-d050b47e-c10f-46e9-bfee-3387454138eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=366638866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.366638866
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1543376409
Short name T736
Test name
Test status
Simulation time 163582727023 ps
CPU time 68.55 seconds
Started Jun 21 06:53:13 PM PDT 24
Finished Jun 21 06:54:24 PM PDT 24
Peak memory 202208 kb
Host smart-013ffb98-fa41-4256-914c-994754476ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543376409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1543376409
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3882465714
Short name T536
Test name
Test status
Simulation time 163325090540 ps
CPU time 96.3 seconds
Started Jun 21 06:53:16 PM PDT 24
Finished Jun 21 06:54:54 PM PDT 24
Peak memory 202160 kb
Host smart-c5f154f4-a929-41ad-8746-b6d6c3a000b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882465714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3882465714
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.4258298453
Short name T648
Test name
Test status
Simulation time 529979399489 ps
CPU time 328.07 seconds
Started Jun 21 06:53:16 PM PDT 24
Finished Jun 21 06:58:46 PM PDT 24
Peak memory 202168 kb
Host smart-ff144f04-b622-4db8-b83a-c4f0814ee4d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258298453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.4258298453
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1215739624
Short name T599
Test name
Test status
Simulation time 198023351753 ps
CPU time 46.63 seconds
Started Jun 21 06:53:12 PM PDT 24
Finished Jun 21 06:54:00 PM PDT 24
Peak memory 202204 kb
Host smart-9b226049-5923-430c-b2a7-17a420e1d796
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215739624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1215739624
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1826132254
Short name T748
Test name
Test status
Simulation time 107942159328 ps
CPU time 354.1 seconds
Started Jun 21 06:53:22 PM PDT 24
Finished Jun 21 06:59:23 PM PDT 24
Peak memory 202572 kb
Host smart-35d934de-5e2a-40da-9edd-9f89183f2d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826132254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1826132254
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4294927784
Short name T372
Test name
Test status
Simulation time 23630775181 ps
CPU time 13.38 seconds
Started Jun 21 06:53:23 PM PDT 24
Finished Jun 21 06:53:45 PM PDT 24
Peak memory 202092 kb
Host smart-92db1ffe-fb8c-4573-b6bc-556f2c7af267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294927784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4294927784
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1663396394
Short name T459
Test name
Test status
Simulation time 5516852952 ps
CPU time 6.8 seconds
Started Jun 21 06:53:23 PM PDT 24
Finished Jun 21 06:53:37 PM PDT 24
Peak memory 202184 kb
Host smart-ab766883-e172-4607-b503-3c62dd6ef644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663396394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1663396394
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2473222823
Short name T173
Test name
Test status
Simulation time 6112330482 ps
CPU time 15.67 seconds
Started Jun 21 06:53:13 PM PDT 24
Finished Jun 21 06:53:31 PM PDT 24
Peak memory 202052 kb
Host smart-f81626d9-1d50-4a42-9fea-140decd51865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473222823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2473222823
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.77676608
Short name T719
Test name
Test status
Simulation time 366117179188 ps
CPU time 559.06 seconds
Started Jun 21 06:53:20 PM PDT 24
Finished Jun 21 07:02:43 PM PDT 24
Peak memory 202212 kb
Host smart-ec4c8117-b333-46f8-be71-6ca754fcf6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77676608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.77676608
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2769803522
Short name T313
Test name
Test status
Simulation time 164696242084 ps
CPU time 346.56 seconds
Started Jun 21 06:53:23 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 210920 kb
Host smart-3adf9322-7051-4a96-bebd-a6483f46373b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769803522 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2769803522
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.127003599
Short name T524
Test name
Test status
Simulation time 339014008 ps
CPU time 0.8 seconds
Started Jun 21 06:53:23 PM PDT 24
Finished Jun 21 06:53:31 PM PDT 24
Peak memory 202040 kb
Host smart-fd9dd5b1-2ffb-4284-bf86-dbf328fb3388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127003599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.127003599
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3704809876
Short name T779
Test name
Test status
Simulation time 165824982444 ps
CPU time 72.54 seconds
Started Jun 21 06:53:21 PM PDT 24
Finished Jun 21 06:54:40 PM PDT 24
Peak memory 202232 kb
Host smart-773a7993-766b-4813-8934-c0ddad18b3c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704809876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3704809876
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1430974982
Short name T451
Test name
Test status
Simulation time 168187102646 ps
CPU time 70.49 seconds
Started Jun 21 06:53:23 PM PDT 24
Finished Jun 21 06:54:41 PM PDT 24
Peak memory 202236 kb
Host smart-a8218061-a286-450a-b6b9-2e20d5b7a230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430974982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1430974982
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.463452824
Short name T179
Test name
Test status
Simulation time 330098980068 ps
CPU time 157.15 seconds
Started Jun 21 06:53:24 PM PDT 24
Finished Jun 21 06:56:10 PM PDT 24
Peak memory 202212 kb
Host smart-0e83b047-834e-41a7-a7a5-881af4766ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463452824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.463452824
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1772643027
Short name T438
Test name
Test status
Simulation time 503992468411 ps
CPU time 288.05 seconds
Started Jun 21 06:53:21 PM PDT 24
Finished Jun 21 06:58:14 PM PDT 24
Peak memory 202172 kb
Host smart-e2836483-b67e-451a-849d-3f900c44bdc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772643027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1772643027
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3408115991
Short name T422
Test name
Test status
Simulation time 330508871046 ps
CPU time 772.04 seconds
Started Jun 21 06:53:20 PM PDT 24
Finished Jun 21 07:06:15 PM PDT 24
Peak memory 202296 kb
Host smart-c6ac28cd-e752-41cf-ab17-15b0bbd8aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408115991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3408115991
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2601140336
Short name T769
Test name
Test status
Simulation time 334501043426 ps
CPU time 212.87 seconds
Started Jun 21 06:53:21 PM PDT 24
Finished Jun 21 06:56:59 PM PDT 24
Peak memory 202216 kb
Host smart-bf3352fa-bea0-4156-8828-301f0279d5c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601140336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2601140336
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2520909736
Short name T176
Test name
Test status
Simulation time 199969529565 ps
CPU time 85.45 seconds
Started Jun 21 06:53:21 PM PDT 24
Finished Jun 21 06:54:54 PM PDT 24
Peak memory 202204 kb
Host smart-23a16c8c-cbd9-455c-959c-b72236a9c133
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520909736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2520909736
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4177103620
Short name T411
Test name
Test status
Simulation time 118404831198 ps
CPU time 476.73 seconds
Started Jun 21 06:53:21 PM PDT 24
Finished Jun 21 07:01:23 PM PDT 24
Peak memory 202628 kb
Host smart-d9a1841a-12ef-4f9d-9c84-3d3659f295b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177103620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4177103620
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2007345125
Short name T421
Test name
Test status
Simulation time 38422487906 ps
CPU time 17.26 seconds
Started Jun 21 06:53:23 PM PDT 24
Finished Jun 21 06:53:49 PM PDT 24
Peak memory 202068 kb
Host smart-4ab209f9-5f67-46dd-978e-92ec2676d974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007345125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2007345125
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3700735687
Short name T520
Test name
Test status
Simulation time 4042525920 ps
CPU time 10.35 seconds
Started Jun 21 06:53:27 PM PDT 24
Finished Jun 21 06:53:47 PM PDT 24
Peak memory 202072 kb
Host smart-355ac61f-d204-4de7-9294-d8e25283df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700735687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3700735687
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.40058105
Short name T584
Test name
Test status
Simulation time 5754957265 ps
CPU time 3.94 seconds
Started Jun 21 06:53:21 PM PDT 24
Finished Jun 21 06:53:32 PM PDT 24
Peak memory 202064 kb
Host smart-102d162e-9ee1-4471-8c15-6d6b16d20654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40058105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.40058105
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3279384915
Short name T120
Test name
Test status
Simulation time 173818631371 ps
CPU time 380.4 seconds
Started Jun 21 06:53:21 PM PDT 24
Finished Jun 21 06:59:47 PM PDT 24
Peak memory 202220 kb
Host smart-fe264d1d-2b47-442b-8d78-0897cbd284c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279384915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3279384915
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2304847846
Short name T92
Test name
Test status
Simulation time 329269409987 ps
CPU time 324.77 seconds
Started Jun 21 06:53:18 PM PDT 24
Finished Jun 21 06:58:45 PM PDT 24
Peak memory 210864 kb
Host smart-695c5b19-686f-4c8c-934f-d23485ed5bd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304847846 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2304847846
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1672441416
Short name T356
Test name
Test status
Simulation time 340278590 ps
CPU time 0.82 seconds
Started Jun 21 06:51:08 PM PDT 24
Finished Jun 21 06:51:12 PM PDT 24
Peak memory 201940 kb
Host smart-8cb00c23-4da0-4a9b-aa72-13bd5c7115b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672441416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1672441416
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2683834947
Short name T125
Test name
Test status
Simulation time 523025395834 ps
CPU time 1318.47 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 07:13:08 PM PDT 24
Peak memory 202236 kb
Host smart-72375027-0ff3-4f29-be47-5b74e895a443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683834947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2683834947
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2921809746
Short name T194
Test name
Test status
Simulation time 161656905997 ps
CPU time 69.76 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 06:52:10 PM PDT 24
Peak memory 202188 kb
Host smart-4acaab6e-5d83-4c46-81a3-fb7454c03485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921809746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2921809746
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3315946158
Short name T577
Test name
Test status
Simulation time 166467639369 ps
CPU time 24.07 seconds
Started Jun 21 06:50:56 PM PDT 24
Finished Jun 21 06:51:26 PM PDT 24
Peak memory 202240 kb
Host smart-e9029148-48d0-48de-a7a4-e268162cfcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315946158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3315946158
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3374629516
Short name T446
Test name
Test status
Simulation time 164074347341 ps
CPU time 46.36 seconds
Started Jun 21 06:50:54 PM PDT 24
Finished Jun 21 06:51:46 PM PDT 24
Peak memory 202212 kb
Host smart-af9fd03c-2403-4d44-8dc7-f6d81b1d3b35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374629516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3374629516
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1103128614
Short name T311
Test name
Test status
Simulation time 415847448678 ps
CPU time 255.18 seconds
Started Jun 21 06:51:01 PM PDT 24
Finished Jun 21 06:55:19 PM PDT 24
Peak memory 202236 kb
Host smart-6a5d6e82-a12f-4faa-9acf-7e3c06766f6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103128614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1103128614
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.959224377
Short name T717
Test name
Test status
Simulation time 595653097230 ps
CPU time 332.04 seconds
Started Jun 21 06:51:02 PM PDT 24
Finished Jun 21 06:56:38 PM PDT 24
Peak memory 202240 kb
Host smart-f39e4246-1899-4e61-b8a4-158ccebfa7ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959224377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.959224377
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1175722844
Short name T766
Test name
Test status
Simulation time 89523363438 ps
CPU time 407.27 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 06:57:57 PM PDT 24
Peak memory 202480 kb
Host smart-45155522-7899-4ecb-9643-dd8adbe877eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175722844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1175722844
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.975758971
Short name T342
Test name
Test status
Simulation time 25911782611 ps
CPU time 61.97 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 06:52:10 PM PDT 24
Peak memory 202060 kb
Host smart-ed49a6dc-15b3-425b-b4ba-0c61c1d0038e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975758971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.975758971
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.4103205786
Short name T589
Test name
Test status
Simulation time 3167390498 ps
CPU time 2.25 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 06:51:11 PM PDT 24
Peak memory 202060 kb
Host smart-cce3cb85-c555-49b2-ae6c-9949e050ad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103205786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.4103205786
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1996911099
Short name T67
Test name
Test status
Simulation time 4453005321 ps
CPU time 3.28 seconds
Started Jun 21 06:51:06 PM PDT 24
Finished Jun 21 06:51:13 PM PDT 24
Peak memory 217740 kb
Host smart-2aab47a4-b68e-4dc8-968b-16b09efa94b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996911099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1996911099
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2829812059
Short name T523
Test name
Test status
Simulation time 5993597953 ps
CPU time 6.83 seconds
Started Jun 21 06:50:56 PM PDT 24
Finished Jun 21 06:51:08 PM PDT 24
Peak memory 202072 kb
Host smart-85c14e6f-daa1-486c-b9c6-2ed5b382d9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829812059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2829812059
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1499434950
Short name T153
Test name
Test status
Simulation time 802827067968 ps
CPU time 559.95 seconds
Started Jun 21 06:51:04 PM PDT 24
Finished Jun 21 07:00:27 PM PDT 24
Peak memory 202252 kb
Host smart-b783b6d0-ce9c-43d2-b6c2-196c2c841d61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499434950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1499434950
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.288612930
Short name T764
Test name
Test status
Simulation time 9628722928 ps
CPU time 23.47 seconds
Started Jun 21 06:51:09 PM PDT 24
Finished Jun 21 06:51:36 PM PDT 24
Peak memory 211036 kb
Host smart-bd3cc895-1e5a-4330-9e6d-0a3b06b7726f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288612930 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.288612930
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1650670252
Short name T526
Test name
Test status
Simulation time 444532958 ps
CPU time 1.4 seconds
Started Jun 21 06:53:32 PM PDT 24
Finished Jun 21 06:53:46 PM PDT 24
Peak memory 201892 kb
Host smart-db3450e5-a3f1-44e7-b5d2-a970ca3d45b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650670252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1650670252
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1493028253
Short name T262
Test name
Test status
Simulation time 326077603816 ps
CPU time 188.25 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 06:56:52 PM PDT 24
Peak memory 202296 kb
Host smart-80b079d4-cd75-4dce-866c-050c5fe87147
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493028253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1493028253
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.392351705
Short name T90
Test name
Test status
Simulation time 169884107390 ps
CPU time 107.39 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 06:55:31 PM PDT 24
Peak memory 202244 kb
Host smart-df7a4cee-59aa-4a68-93ac-9b2141823a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392351705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.392351705
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3357175391
Short name T187
Test name
Test status
Simulation time 163315709074 ps
CPU time 96.23 seconds
Started Jun 21 06:53:32 PM PDT 24
Finished Jun 21 06:55:21 PM PDT 24
Peak memory 202276 kb
Host smart-404ec08c-1f65-453c-afb2-a17d83faa779
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357175391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3357175391
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.997219226
Short name T255
Test name
Test status
Simulation time 494116580976 ps
CPU time 529.37 seconds
Started Jun 21 06:53:22 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 202268 kb
Host smart-8fa9770f-f260-4aba-a77b-f844ff400800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997219226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.997219226
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2596218492
Short name T770
Test name
Test status
Simulation time 333737132339 ps
CPU time 399.91 seconds
Started Jun 21 06:53:23 PM PDT 24
Finished Jun 21 07:00:11 PM PDT 24
Peak memory 202192 kb
Host smart-314a1b5f-4cdf-4807-84d2-3c3ced7c8682
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596218492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2596218492
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.281980943
Short name T164
Test name
Test status
Simulation time 346414893980 ps
CPU time 202.75 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 06:57:06 PM PDT 24
Peak memory 202328 kb
Host smart-2ffd3e36-18d2-492d-b993-77df0d071696
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281980943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.281980943
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.767809630
Short name T713
Test name
Test status
Simulation time 389618722798 ps
CPU time 862.25 seconds
Started Jun 21 06:53:30 PM PDT 24
Finished Jun 21 07:08:06 PM PDT 24
Peak memory 202272 kb
Host smart-47edfa14-9c70-49c8-97ba-a4c937e8f514
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767809630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.767809630
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.4109291767
Short name T200
Test name
Test status
Simulation time 130245330201 ps
CPU time 437.99 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 07:01:02 PM PDT 24
Peak memory 202496 kb
Host smart-6e64e66f-e255-4859-adb9-529747d5a0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109291767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.4109291767
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1806253734
Short name T561
Test name
Test status
Simulation time 22853383338 ps
CPU time 51.65 seconds
Started Jun 21 06:53:32 PM PDT 24
Finished Jun 21 06:54:37 PM PDT 24
Peak memory 202184 kb
Host smart-d2d83eee-66c1-43a6-bc00-4f62d7fba27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806253734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1806253734
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1128356188
Short name T690
Test name
Test status
Simulation time 3164802838 ps
CPU time 2.12 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 06:53:46 PM PDT 24
Peak memory 202084 kb
Host smart-be17d14a-6311-43c2-ba1d-eba05b79a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128356188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1128356188
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3588636421
Short name T178
Test name
Test status
Simulation time 6011791018 ps
CPU time 15.51 seconds
Started Jun 21 06:53:23 PM PDT 24
Finished Jun 21 06:53:47 PM PDT 24
Peak memory 202056 kb
Host smart-5ee75333-b231-4161-8576-471067339127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588636421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3588636421
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.647837379
Short name T250
Test name
Test status
Simulation time 235253113164 ps
CPU time 554.04 seconds
Started Jun 21 06:53:30 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 202300 kb
Host smart-7e4d27a2-c086-4a23-b23a-207622430d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647837379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
647837379
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2322884018
Short name T20
Test name
Test status
Simulation time 119100356426 ps
CPU time 43.73 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 06:54:27 PM PDT 24
Peak memory 217444 kb
Host smart-f149620e-eaf4-4716-a5ed-a0cc7be2690d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322884018 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2322884018
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.855524
Short name T374
Test name
Test status
Simulation time 502115099 ps
CPU time 1.79 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 06:53:58 PM PDT 24
Peak memory 201944 kb
Host smart-bc5f135f-1c55-4533-971b-c356e6009ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.855524
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1355073022
Short name T223
Test name
Test status
Simulation time 451624622531 ps
CPU time 942.73 seconds
Started Jun 21 06:53:32 PM PDT 24
Finished Jun 21 07:09:28 PM PDT 24
Peak memory 202180 kb
Host smart-9b377ee4-cc05-48a3-94a4-7e86368c1695
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355073022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1355073022
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2020967942
Short name T695
Test name
Test status
Simulation time 344157028130 ps
CPU time 158.98 seconds
Started Jun 21 06:53:44 PM PDT 24
Finished Jun 21 06:56:34 PM PDT 24
Peak memory 202240 kb
Host smart-d4c45c1f-5f77-493a-8071-555307b7314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020967942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2020967942
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2494561340
Short name T31
Test name
Test status
Simulation time 489208376226 ps
CPU time 1150.31 seconds
Started Jun 21 06:53:32 PM PDT 24
Finished Jun 21 07:12:55 PM PDT 24
Peak memory 202204 kb
Host smart-f3cf0ccb-e589-4504-9af9-9c7914849c6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494561340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2494561340
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3000812139
Short name T277
Test name
Test status
Simulation time 166630929357 ps
CPU time 63.63 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 06:54:48 PM PDT 24
Peak memory 202216 kb
Host smart-432cfcfe-36a7-4230-b438-bd77ebe1b348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000812139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3000812139
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.921024988
Short name T132
Test name
Test status
Simulation time 165236921132 ps
CPU time 21.96 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 06:54:06 PM PDT 24
Peak memory 202204 kb
Host smart-85efe033-0354-4343-aa5c-4ac49f4cd4cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=921024988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.921024988
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3977889552
Short name T297
Test name
Test status
Simulation time 171585953216 ps
CPU time 269.74 seconds
Started Jun 21 06:53:29 PM PDT 24
Finished Jun 21 06:58:10 PM PDT 24
Peak memory 202304 kb
Host smart-ae2f6ca9-5cc7-4a5f-aa44-3967be805839
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977889552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3977889552
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3825458605
Short name T461
Test name
Test status
Simulation time 596726317647 ps
CPU time 625.5 seconds
Started Jun 21 06:53:31 PM PDT 24
Finished Jun 21 07:04:09 PM PDT 24
Peak memory 202212 kb
Host smart-8cbb1860-99d2-43b0-8f46-782cfb4f00bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825458605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3825458605
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3331731686
Short name T758
Test name
Test status
Simulation time 94994041599 ps
CPU time 491.98 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 07:02:08 PM PDT 24
Peak memory 202628 kb
Host smart-6e45c0fc-9b59-4c40-affd-1cf91087d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331731686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3331731686
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.64820681
Short name T518
Test name
Test status
Simulation time 34027056487 ps
CPU time 37.08 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 06:54:33 PM PDT 24
Peak memory 202028 kb
Host smart-398648d4-a0a5-4904-b69e-07f6548c3060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64820681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.64820681
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1530169388
Short name T113
Test name
Test status
Simulation time 3635472497 ps
CPU time 9.49 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 06:54:06 PM PDT 24
Peak memory 202048 kb
Host smart-5e63ef1b-4142-4684-84c7-7becf6ea5f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530169388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1530169388
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2329965698
Short name T458
Test name
Test status
Simulation time 5500216233 ps
CPU time 7.02 seconds
Started Jun 21 06:53:32 PM PDT 24
Finished Jun 21 06:53:52 PM PDT 24
Peak memory 202004 kb
Host smart-ed60c48b-e905-4ce4-bff6-4e9fe3ad437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329965698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2329965698
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2131124877
Short name T306
Test name
Test status
Simulation time 212553775599 ps
CPU time 114.73 seconds
Started Jun 21 06:53:46 PM PDT 24
Finished Jun 21 06:55:52 PM PDT 24
Peak memory 202232 kb
Host smart-718c6438-f8ed-419f-b83c-8e1ec10f1c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131124877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2131124877
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.4266009189
Short name T763
Test name
Test status
Simulation time 28309890137 ps
CPU time 98.5 seconds
Started Jun 21 06:53:44 PM PDT 24
Finished Jun 21 06:55:34 PM PDT 24
Peak memory 210808 kb
Host smart-ae016788-0383-4ed5-818e-176d37de3e0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266009189 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.4266009189
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2199515674
Short name T538
Test name
Test status
Simulation time 435805642 ps
CPU time 0.93 seconds
Started Jun 21 06:53:57 PM PDT 24
Finished Jun 21 06:54:05 PM PDT 24
Peak memory 201892 kb
Host smart-85602800-d87a-4fa9-adf8-818608850388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199515674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2199515674
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.241549614
Short name T235
Test name
Test status
Simulation time 495857008974 ps
CPU time 778.62 seconds
Started Jun 21 06:53:43 PM PDT 24
Finished Jun 21 07:06:54 PM PDT 24
Peak memory 202300 kb
Host smart-b2c63f39-4afd-4ab5-b265-1137639a6215
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241549614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.241549614
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3518649206
Short name T28
Test name
Test status
Simulation time 360013359017 ps
CPU time 827.09 seconds
Started Jun 21 06:53:46 PM PDT 24
Finished Jun 21 07:07:44 PM PDT 24
Peak memory 202180 kb
Host smart-4a8aed8f-4f2d-4422-8fb4-9d64e81ab0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518649206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3518649206
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3072808966
Short name T4
Test name
Test status
Simulation time 161665576432 ps
CPU time 94.36 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 06:55:31 PM PDT 24
Peak memory 202200 kb
Host smart-04d34fd1-9d2c-4dc9-8379-58d2565d4337
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072808966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3072808966
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2138326978
Short name T715
Test name
Test status
Simulation time 162728405131 ps
CPU time 355.23 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 06:59:52 PM PDT 24
Peak memory 202228 kb
Host smart-5d691902-ec9f-413f-8b58-3a91bc4ce012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138326978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2138326978
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.235028342
Short name T148
Test name
Test status
Simulation time 167074698638 ps
CPU time 99.59 seconds
Started Jun 21 06:53:44 PM PDT 24
Finished Jun 21 06:55:35 PM PDT 24
Peak memory 202152 kb
Host smart-bfa5e201-4eb0-4b10-a6b2-13f7226ccd54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=235028342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.235028342
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.828640452
Short name T711
Test name
Test status
Simulation time 541955927249 ps
CPU time 311.72 seconds
Started Jun 21 06:53:44 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 202268 kb
Host smart-5dd808bb-7402-4f22-8b2b-425afc2f8d53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828640452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.828640452
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2497204267
Short name T376
Test name
Test status
Simulation time 198713253182 ps
CPU time 50.04 seconds
Started Jun 21 06:53:46 PM PDT 24
Finished Jun 21 06:54:48 PM PDT 24
Peak memory 202316 kb
Host smart-943c5fc7-07ca-41cb-83cf-17ae9cd2c2c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497204267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2497204267
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3890455892
Short name T52
Test name
Test status
Simulation time 94899750100 ps
CPU time 377.09 seconds
Started Jun 21 06:53:44 PM PDT 24
Finished Jun 21 07:00:13 PM PDT 24
Peak memory 202624 kb
Host smart-93a99e49-6628-4aa2-b222-8dee13c52366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890455892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3890455892
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1812066161
Short name T725
Test name
Test status
Simulation time 35225929786 ps
CPU time 39.19 seconds
Started Jun 21 06:53:44 PM PDT 24
Finished Jun 21 06:54:35 PM PDT 24
Peak memory 202060 kb
Host smart-9dd5fc3c-2869-4f50-b03a-0f557549921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812066161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1812066161
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1693746941
Short name T3
Test name
Test status
Simulation time 3179340910 ps
CPU time 6.57 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 06:54:03 PM PDT 24
Peak memory 202060 kb
Host smart-9cc0a37b-6784-4df1-8afd-47e0f1f8ee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693746941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1693746941
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3080122910
Short name T539
Test name
Test status
Simulation time 5939863570 ps
CPU time 14.77 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 06:54:12 PM PDT 24
Peak memory 202168 kb
Host smart-3588d9d3-dd79-4d40-b323-8e3bc9947c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080122910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3080122910
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1546856423
Short name T593
Test name
Test status
Simulation time 226987518574 ps
CPU time 540.96 seconds
Started Jun 21 06:53:44 PM PDT 24
Finished Jun 21 07:02:57 PM PDT 24
Peak memory 202232 kb
Host smart-128f672a-6a42-470f-9b92-389c12ee1757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546856423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1546856423
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2079779784
Short name T16
Test name
Test status
Simulation time 49422815566 ps
CPU time 147.44 seconds
Started Jun 21 06:53:45 PM PDT 24
Finished Jun 21 06:56:24 PM PDT 24
Peak memory 210848 kb
Host smart-7f51b3f7-ed4c-4f31-a20d-76a8a38ea7f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079779784 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2079779784
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1065981054
Short name T615
Test name
Test status
Simulation time 343887597 ps
CPU time 0.78 seconds
Started Jun 21 06:53:53 PM PDT 24
Finished Jun 21 06:54:03 PM PDT 24
Peak memory 201932 kb
Host smart-49f19680-09a6-48b6-bc32-4b22796fcb05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065981054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1065981054
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2477663498
Short name T116
Test name
Test status
Simulation time 490653629087 ps
CPU time 301.64 seconds
Started Jun 21 06:53:51 PM PDT 24
Finished Jun 21 06:59:03 PM PDT 24
Peak memory 202244 kb
Host smart-3794f730-07bd-4091-8a18-abb6677a5247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477663498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2477663498
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.146126675
Short name T402
Test name
Test status
Simulation time 328725404178 ps
CPU time 402.82 seconds
Started Jun 21 06:53:52 PM PDT 24
Finished Jun 21 07:00:44 PM PDT 24
Peak memory 202196 kb
Host smart-41380dcc-9db6-42ff-9b31-391857f2d777
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=146126675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.146126675
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3227044432
Short name T508
Test name
Test status
Simulation time 330539666793 ps
CPU time 798.12 seconds
Started Jun 21 06:53:52 PM PDT 24
Finished Jun 21 07:07:19 PM PDT 24
Peak memory 202228 kb
Host smart-2379659d-a59e-4b11-9bee-f186f8c277bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227044432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3227044432
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3958686105
Short name T348
Test name
Test status
Simulation time 492068477375 ps
CPU time 1111.43 seconds
Started Jun 21 06:53:51 PM PDT 24
Finished Jun 21 07:12:32 PM PDT 24
Peak memory 202224 kb
Host smart-61d8bf6b-d854-4370-ab0b-8a649f347d07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958686105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3958686105
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2718467825
Short name T617
Test name
Test status
Simulation time 211609297973 ps
CPU time 125.31 seconds
Started Jun 21 06:53:51 PM PDT 24
Finished Jun 21 06:56:06 PM PDT 24
Peak memory 202160 kb
Host smart-83845686-e299-482c-8936-f67b619d9688
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718467825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2718467825
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1241645643
Short name T762
Test name
Test status
Simulation time 99034079496 ps
CPU time 292.07 seconds
Started Jun 21 06:53:54 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 202636 kb
Host smart-f5e36d89-4192-4ba4-91dc-4ab7de2b0035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241645643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1241645643
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1216550498
Short name T672
Test name
Test status
Simulation time 39652017799 ps
CPU time 92.03 seconds
Started Jun 21 06:53:52 PM PDT 24
Finished Jun 21 06:55:33 PM PDT 24
Peak memory 202064 kb
Host smart-f03db05e-92dc-4f55-a174-52b0b15446bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216550498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1216550498
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2193593824
Short name T628
Test name
Test status
Simulation time 4515960848 ps
CPU time 3.01 seconds
Started Jun 21 06:53:55 PM PDT 24
Finished Jun 21 06:54:06 PM PDT 24
Peak memory 202056 kb
Host smart-cce02592-92b6-42c9-a7bb-9f9effece421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193593824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2193593824
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4159289241
Short name T350
Test name
Test status
Simulation time 6096188221 ps
CPU time 14.84 seconds
Started Jun 21 06:53:53 PM PDT 24
Finished Jun 21 06:54:17 PM PDT 24
Peak memory 202052 kb
Host smart-736ad3ef-6cf8-4687-85dc-aae06b817df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159289241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4159289241
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.410365658
Short name T608
Test name
Test status
Simulation time 359777073083 ps
CPU time 220.05 seconds
Started Jun 21 06:53:53 PM PDT 24
Finished Jun 21 06:57:42 PM PDT 24
Peak memory 202300 kb
Host smart-5f2f63e5-9e94-4374-8196-655a701080e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410365658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
410365658
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1496353505
Short name T462
Test name
Test status
Simulation time 381624704 ps
CPU time 1.5 seconds
Started Jun 21 06:53:52 PM PDT 24
Finished Jun 21 06:54:03 PM PDT 24
Peak memory 201924 kb
Host smart-44372d1d-c924-483a-9ec1-a49c2bf264c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496353505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1496353505
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2413435760
Short name T707
Test name
Test status
Simulation time 486149749572 ps
CPU time 278.61 seconds
Started Jun 21 06:53:53 PM PDT 24
Finished Jun 21 06:58:41 PM PDT 24
Peak memory 202264 kb
Host smart-5dffbed0-751c-41bc-a92d-09389b8b3722
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413435760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2413435760
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.893159268
Short name T157
Test name
Test status
Simulation time 162805657424 ps
CPU time 155.6 seconds
Started Jun 21 06:53:54 PM PDT 24
Finished Jun 21 06:56:38 PM PDT 24
Peak memory 202232 kb
Host smart-ee480608-6c9a-4246-bdaa-a2aa8fe7674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893159268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.893159268
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.4114886194
Short name T410
Test name
Test status
Simulation time 489209179768 ps
CPU time 298.21 seconds
Started Jun 21 06:53:53 PM PDT 24
Finished Jun 21 06:59:00 PM PDT 24
Peak memory 202204 kb
Host smart-cdcd6208-3fa6-4ff3-8a3f-e9fda83dbb07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114886194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.4114886194
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2063368682
Short name T735
Test name
Test status
Simulation time 180717014393 ps
CPU time 213.25 seconds
Started Jun 21 06:53:54 PM PDT 24
Finished Jun 21 06:57:36 PM PDT 24
Peak memory 202156 kb
Host smart-838786fb-7ad6-4c8c-9aae-8d6fb551adb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063368682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2063368682
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1750499802
Short name T597
Test name
Test status
Simulation time 616752168282 ps
CPU time 166.11 seconds
Started Jun 21 06:53:53 PM PDT 24
Finished Jun 21 06:56:48 PM PDT 24
Peak memory 202208 kb
Host smart-d9bd19dc-344c-4700-9df1-7837d7176a0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750499802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1750499802
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4249831240
Short name T787
Test name
Test status
Simulation time 99180138347 ps
CPU time 406.62 seconds
Started Jun 21 06:53:53 PM PDT 24
Finished Jun 21 07:00:49 PM PDT 24
Peak memory 202624 kb
Host smart-6a6e59a6-8f5d-425f-927a-25397468529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249831240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4249831240
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2079301227
Short name T498
Test name
Test status
Simulation time 26090189797 ps
CPU time 62.85 seconds
Started Jun 21 06:53:52 PM PDT 24
Finished Jun 21 06:55:04 PM PDT 24
Peak memory 202084 kb
Host smart-161aaeb1-f2db-4d03-97b0-42ab1eb4c105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079301227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2079301227
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3225232997
Short name T655
Test name
Test status
Simulation time 4595215807 ps
CPU time 11.37 seconds
Started Jun 21 06:53:52 PM PDT 24
Finished Jun 21 06:54:13 PM PDT 24
Peak memory 202036 kb
Host smart-c7acac5d-de55-4f74-a9db-99d17beaedfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225232997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3225232997
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3532235753
Short name T781
Test name
Test status
Simulation time 5532410599 ps
CPU time 7.46 seconds
Started Jun 21 06:53:50 PM PDT 24
Finished Jun 21 06:54:07 PM PDT 24
Peak memory 202052 kb
Host smart-312d08a8-4560-45c4-bae1-538942615dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532235753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3532235753
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1040427024
Short name T531
Test name
Test status
Simulation time 6720696158 ps
CPU time 10.08 seconds
Started Jun 21 06:53:55 PM PDT 24
Finished Jun 21 06:54:13 PM PDT 24
Peak memory 201980 kb
Host smart-a859295f-5778-4512-9657-989150f5db49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040427024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1040427024
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3917972626
Short name T21
Test name
Test status
Simulation time 32665745572 ps
CPU time 66.03 seconds
Started Jun 21 06:53:55 PM PDT 24
Finished Jun 21 06:55:09 PM PDT 24
Peak memory 202344 kb
Host smart-57b702ea-21ae-4da1-a308-47e410debbd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917972626 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3917972626
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3246290446
Short name T354
Test name
Test status
Simulation time 382538844 ps
CPU time 0.83 seconds
Started Jun 21 06:54:03 PM PDT 24
Finished Jun 21 06:54:07 PM PDT 24
Peak memory 201944 kb
Host smart-60b5f9ee-5567-4dcf-a93c-f69648fd6741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246290446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3246290446
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3702291563
Short name T616
Test name
Test status
Simulation time 493165003056 ps
CPU time 1215.55 seconds
Started Jun 21 06:54:01 PM PDT 24
Finished Jun 21 07:14:21 PM PDT 24
Peak memory 202228 kb
Host smart-de155ea3-6302-486c-ac4b-b83c616d2f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702291563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3702291563
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.336330443
Short name T547
Test name
Test status
Simulation time 326874523015 ps
CPU time 369.44 seconds
Started Jun 21 06:54:01 PM PDT 24
Finished Jun 21 07:00:14 PM PDT 24
Peak memory 202268 kb
Host smart-07cdee9c-a026-4182-9b13-1270c8342c94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=336330443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.336330443
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2526289086
Short name T167
Test name
Test status
Simulation time 490103531127 ps
CPU time 297.21 seconds
Started Jun 21 06:53:55 PM PDT 24
Finished Jun 21 06:59:00 PM PDT 24
Peak memory 202288 kb
Host smart-972a3f06-53d9-41e7-aa4d-cc881efc02d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526289086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2526289086
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1636473555
Short name T143
Test name
Test status
Simulation time 162910308989 ps
CPU time 27.36 seconds
Started Jun 21 06:54:06 PM PDT 24
Finished Jun 21 06:54:35 PM PDT 24
Peak memory 202204 kb
Host smart-4da805d1-e915-411b-bedc-c3c24787fdb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636473555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1636473555
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3242500456
Short name T639
Test name
Test status
Simulation time 607196409116 ps
CPU time 348.11 seconds
Started Jun 21 06:54:07 PM PDT 24
Finished Jun 21 06:59:56 PM PDT 24
Peak memory 202204 kb
Host smart-fbff0160-3e97-4608-aea2-303210d80fef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242500456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3242500456
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3510910896
Short name T757
Test name
Test status
Simulation time 101793776858 ps
CPU time 355.1 seconds
Started Jun 21 06:54:04 PM PDT 24
Finished Jun 21 07:00:02 PM PDT 24
Peak memory 202548 kb
Host smart-03234fd4-1037-4d7f-86dd-afc3fc3c779a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510910896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3510910896
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3121566691
Short name T397
Test name
Test status
Simulation time 24721623283 ps
CPU time 13.9 seconds
Started Jun 21 06:54:03 PM PDT 24
Finished Jun 21 06:54:20 PM PDT 24
Peak memory 202080 kb
Host smart-62ff7d33-aa36-427f-9ce9-5030b56ead01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121566691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3121566691
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1480123734
Short name T626
Test name
Test status
Simulation time 3204471642 ps
CPU time 8.12 seconds
Started Jun 21 06:54:06 PM PDT 24
Finished Jun 21 06:54:16 PM PDT 24
Peak memory 202048 kb
Host smart-5f9a8266-54f1-47db-a037-e6f9b2e6db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480123734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1480123734
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.74471738
Short name T420
Test name
Test status
Simulation time 5591062365 ps
CPU time 6.41 seconds
Started Jun 21 06:53:55 PM PDT 24
Finished Jun 21 06:54:10 PM PDT 24
Peak memory 202060 kb
Host smart-3bcb0113-2b5c-49f5-9671-bd4ae5cd1967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74471738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.74471738
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3097961014
Short name T718
Test name
Test status
Simulation time 385148061742 ps
CPU time 440.69 seconds
Started Jun 21 06:54:04 PM PDT 24
Finished Jun 21 07:01:27 PM PDT 24
Peak memory 202224 kb
Host smart-17340c17-3642-4521-81a4-9aa0d477bc05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097961014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3097961014
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1322226364
Short name T460
Test name
Test status
Simulation time 195150759637 ps
CPU time 418.18 seconds
Started Jun 21 06:54:04 PM PDT 24
Finished Jun 21 07:01:05 PM PDT 24
Peak memory 210520 kb
Host smart-b78eba50-2be3-437a-8c68-6f334790f6e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322226364 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1322226364
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2563450664
Short name T693
Test name
Test status
Simulation time 429333981 ps
CPU time 0.9 seconds
Started Jun 21 06:54:10 PM PDT 24
Finished Jun 21 06:54:13 PM PDT 24
Peak memory 201940 kb
Host smart-7a0566e4-f598-4188-9063-f03098218075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563450664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2563450664
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1188233681
Short name T305
Test name
Test status
Simulation time 358749699379 ps
CPU time 200.97 seconds
Started Jun 21 06:54:10 PM PDT 24
Finished Jun 21 06:57:33 PM PDT 24
Peak memory 202336 kb
Host smart-7a5c5c79-8ec9-4c7a-8fcf-1d94ef3e3b8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188233681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1188233681
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2354239206
Short name T701
Test name
Test status
Simulation time 162663674127 ps
CPU time 361.85 seconds
Started Jun 21 06:54:11 PM PDT 24
Finished Jun 21 07:00:14 PM PDT 24
Peak memory 202180 kb
Host smart-7fde01ed-ced9-4671-bc16-5e61cba1c2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354239206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2354239206
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.812833138
Short name T564
Test name
Test status
Simulation time 331789937867 ps
CPU time 842.24 seconds
Started Jun 21 06:54:02 PM PDT 24
Finished Jun 21 07:08:08 PM PDT 24
Peak memory 202204 kb
Host smart-87f62403-23e0-4b40-b677-e7382e20e762
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=812833138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.812833138
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.99717056
Short name T529
Test name
Test status
Simulation time 164509912747 ps
CPU time 85.35 seconds
Started Jun 21 06:54:05 PM PDT 24
Finished Jun 21 06:55:32 PM PDT 24
Peak memory 202164 kb
Host smart-c03edf20-b59a-4092-81b3-d685e212f8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99717056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.99717056
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1038378127
Short name T357
Test name
Test status
Simulation time 164766938038 ps
CPU time 186 seconds
Started Jun 21 06:54:03 PM PDT 24
Finished Jun 21 06:57:12 PM PDT 24
Peak memory 202192 kb
Host smart-67ef3eaa-67e2-448c-babc-3299863b5872
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038378127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1038378127
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.4172163347
Short name T233
Test name
Test status
Simulation time 265695414689 ps
CPU time 314.01 seconds
Started Jun 21 06:54:06 PM PDT 24
Finished Jun 21 06:59:22 PM PDT 24
Peak memory 202248 kb
Host smart-43cf5e60-0387-438c-b6d7-fe7864920d92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172163347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.4172163347
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.740138106
Short name T554
Test name
Test status
Simulation time 409447307620 ps
CPU time 163.19 seconds
Started Jun 21 06:54:01 PM PDT 24
Finished Jun 21 06:56:48 PM PDT 24
Peak memory 202212 kb
Host smart-25e44553-7c96-4ec2-aa0c-5a0ee67df915
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740138106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.740138106
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.4011017717
Short name T49
Test name
Test status
Simulation time 88309336517 ps
CPU time 331.78 seconds
Started Jun 21 06:54:09 PM PDT 24
Finished Jun 21 06:59:42 PM PDT 24
Peak memory 202604 kb
Host smart-af24bcb4-1710-4ec0-912d-a85af929852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011017717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.4011017717
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3632301584
Short name T439
Test name
Test status
Simulation time 22959776790 ps
CPU time 14.25 seconds
Started Jun 21 06:54:11 PM PDT 24
Finished Jun 21 06:54:27 PM PDT 24
Peak memory 202072 kb
Host smart-245f5bf6-9263-454a-b49b-028d79a5fd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632301584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3632301584
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2987426959
Short name T382
Test name
Test status
Simulation time 4439820984 ps
CPU time 2.6 seconds
Started Jun 21 06:54:14 PM PDT 24
Finished Jun 21 06:54:18 PM PDT 24
Peak memory 202028 kb
Host smart-884d81c7-2e05-44f9-b574-e67a7f4d243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987426959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2987426959
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1278787302
Short name T760
Test name
Test status
Simulation time 5891608296 ps
CPU time 13.92 seconds
Started Jun 21 06:54:02 PM PDT 24
Finished Jun 21 06:54:19 PM PDT 24
Peak memory 202020 kb
Host smart-03f77ebc-a9df-4594-a518-de9f7528c470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278787302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1278787302
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2575058876
Short name T742
Test name
Test status
Simulation time 34222010145 ps
CPU time 76.33 seconds
Started Jun 21 06:54:10 PM PDT 24
Finished Jun 21 06:55:28 PM PDT 24
Peak memory 202072 kb
Host smart-22bcc322-45ce-4661-92cd-d5b387deaafe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575058876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2575058876
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1384827607
Short name T212
Test name
Test status
Simulation time 95346591907 ps
CPU time 178.64 seconds
Started Jun 21 06:54:14 PM PDT 24
Finished Jun 21 06:57:14 PM PDT 24
Peak memory 210916 kb
Host smart-824a244b-baa1-4610-9064-dd8734a68881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384827607 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1384827607
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2439464025
Short name T479
Test name
Test status
Simulation time 453425101 ps
CPU time 1.81 seconds
Started Jun 21 06:54:26 PM PDT 24
Finished Jun 21 06:54:30 PM PDT 24
Peak memory 201892 kb
Host smart-d71d9791-6317-484a-8903-ce7c462d1cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439464025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2439464025
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2655369179
Short name T118
Test name
Test status
Simulation time 166428820506 ps
CPU time 12.51 seconds
Started Jun 21 06:54:10 PM PDT 24
Finished Jun 21 06:54:24 PM PDT 24
Peak memory 202232 kb
Host smart-53b80f51-8741-41df-a035-e014b4104117
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655369179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2655369179
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3274188524
Short name T247
Test name
Test status
Simulation time 175445893284 ps
CPU time 93.47 seconds
Started Jun 21 06:54:11 PM PDT 24
Finished Jun 21 06:55:46 PM PDT 24
Peak memory 202204 kb
Host smart-9f4e5ffd-508e-4ea8-bb20-cb58e685944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274188524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3274188524
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1669862520
Short name T242
Test name
Test status
Simulation time 161193208457 ps
CPU time 347.33 seconds
Started Jun 21 06:54:09 PM PDT 24
Finished Jun 21 06:59:58 PM PDT 24
Peak memory 202240 kb
Host smart-5d860456-67f0-47b1-824c-ef4ec948417d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669862520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1669862520
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1566782445
Short name T661
Test name
Test status
Simulation time 326185240630 ps
CPU time 183.35 seconds
Started Jun 21 06:54:14 PM PDT 24
Finished Jun 21 06:57:18 PM PDT 24
Peak memory 202188 kb
Host smart-effec126-2345-4008-8883-6ef857535d3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566782445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1566782445
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2935199985
Short name T688
Test name
Test status
Simulation time 489408580908 ps
CPU time 1124.47 seconds
Started Jun 21 06:54:11 PM PDT 24
Finished Jun 21 07:12:57 PM PDT 24
Peak memory 202240 kb
Host smart-b77c559d-5e30-4312-b85a-a0cba2f039f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935199985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2935199985
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.612886323
Short name T730
Test name
Test status
Simulation time 482855023109 ps
CPU time 1026.72 seconds
Started Jun 21 06:54:13 PM PDT 24
Finished Jun 21 07:11:21 PM PDT 24
Peak memory 202284 kb
Host smart-3270e88f-16c7-49bf-973f-977dce26494f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=612886323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.612886323
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.480765423
Short name T785
Test name
Test status
Simulation time 371050155015 ps
CPU time 162.85 seconds
Started Jun 21 06:54:13 PM PDT 24
Finished Jun 21 06:56:57 PM PDT 24
Peak memory 202228 kb
Host smart-029a6688-722a-4c07-b7f8-bbb102f0e037
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480765423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.480765423
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3641640785
Short name T658
Test name
Test status
Simulation time 586220964124 ps
CPU time 617.99 seconds
Started Jun 21 06:54:11 PM PDT 24
Finished Jun 21 07:04:31 PM PDT 24
Peak memory 202212 kb
Host smart-3efb13f4-1127-40bd-b093-4ccad77a424d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641640785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3641640785
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1586451836
Short name T731
Test name
Test status
Simulation time 117241847907 ps
CPU time 451.21 seconds
Started Jun 21 06:54:20 PM PDT 24
Finished Jun 21 07:01:54 PM PDT 24
Peak memory 202612 kb
Host smart-b401d53c-fb39-4514-8824-9b78347321b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586451836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1586451836
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3380197203
Short name T552
Test name
Test status
Simulation time 23635261592 ps
CPU time 59.5 seconds
Started Jun 21 06:54:20 PM PDT 24
Finished Jun 21 06:55:22 PM PDT 24
Peak memory 202080 kb
Host smart-52d17c65-dc5c-499c-a619-2cb11509673e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380197203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3380197203
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4085260315
Short name T482
Test name
Test status
Simulation time 3520118153 ps
CPU time 2.26 seconds
Started Jun 21 06:54:09 PM PDT 24
Finished Jun 21 06:54:13 PM PDT 24
Peak memory 202060 kb
Host smart-e5d017e4-c025-4717-b3a2-6877bddf012a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085260315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4085260315
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2224472155
Short name T654
Test name
Test status
Simulation time 6441854436 ps
CPU time 1.55 seconds
Started Jun 21 06:54:14 PM PDT 24
Finished Jun 21 06:54:17 PM PDT 24
Peak memory 202040 kb
Host smart-878978b5-4470-4dbc-be9d-2e4172c02898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224472155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2224472155
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3675430955
Short name T19
Test name
Test status
Simulation time 67707407571 ps
CPU time 51.84 seconds
Started Jun 21 06:54:22 PM PDT 24
Finished Jun 21 06:55:15 PM PDT 24
Peak memory 210900 kb
Host smart-abb1a506-231e-4e00-9817-814aa3bf8c67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675430955 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3675430955
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2419353243
Short name T89
Test name
Test status
Simulation time 326370931 ps
CPU time 1.02 seconds
Started Jun 21 06:54:33 PM PDT 24
Finished Jun 21 06:54:36 PM PDT 24
Peak memory 201940 kb
Host smart-9da30176-57c5-4896-a490-4b981fb45a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419353243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2419353243
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2252892010
Short name T122
Test name
Test status
Simulation time 369746069453 ps
CPU time 121.32 seconds
Started Jun 21 06:54:18 PM PDT 24
Finished Jun 21 06:56:21 PM PDT 24
Peak memory 202256 kb
Host smart-25f4dce3-6870-427b-8639-8175f0c7e505
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252892010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2252892010
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2001659920
Short name T123
Test name
Test status
Simulation time 371941041718 ps
CPU time 851.68 seconds
Started Jun 21 06:54:22 PM PDT 24
Finished Jun 21 07:08:36 PM PDT 24
Peak memory 202228 kb
Host smart-ab4dd0fe-3f72-4d08-a00a-5879b07117db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001659920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2001659920
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2280975375
Short name T674
Test name
Test status
Simulation time 333882638636 ps
CPU time 738.12 seconds
Started Jun 21 06:54:20 PM PDT 24
Finished Jun 21 07:06:41 PM PDT 24
Peak memory 202172 kb
Host smart-bf93fbd0-1a02-4747-be93-aa64a00dfc47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280975375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2280975375
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3548209023
Short name T310
Test name
Test status
Simulation time 328004654312 ps
CPU time 203.01 seconds
Started Jun 21 06:54:22 PM PDT 24
Finished Jun 21 06:57:47 PM PDT 24
Peak memory 202300 kb
Host smart-88f8af47-89ec-4f98-aa0a-63b311d33226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548209023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3548209023
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3332217289
Short name T656
Test name
Test status
Simulation time 487037855942 ps
CPU time 601.07 seconds
Started Jun 21 06:54:20 PM PDT 24
Finished Jun 21 07:04:23 PM PDT 24
Peak memory 202268 kb
Host smart-66b219cd-d899-4757-ad33-bd841441f9ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332217289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3332217289
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.376742639
Short name T263
Test name
Test status
Simulation time 173461573838 ps
CPU time 375.58 seconds
Started Jun 21 06:54:20 PM PDT 24
Finished Jun 21 07:00:38 PM PDT 24
Peak memory 202284 kb
Host smart-e3b0f4d6-88db-4a64-ad8b-65d2a8a7767a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376742639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.376742639
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.696877263
Short name T630
Test name
Test status
Simulation time 210427435327 ps
CPU time 118.99 seconds
Started Jun 21 06:54:19 PM PDT 24
Finished Jun 21 06:56:21 PM PDT 24
Peak memory 202208 kb
Host smart-8a61fd0d-7b27-4d34-b639-f157b3f84aec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696877263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.696877263
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3984994881
Short name T612
Test name
Test status
Simulation time 133821971875 ps
CPU time 630.84 seconds
Started Jun 21 06:54:31 PM PDT 24
Finished Jun 21 07:05:03 PM PDT 24
Peak memory 202524 kb
Host smart-7a8a5ec9-d030-49d9-9243-82d6b44593d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984994881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3984994881
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1184203756
Short name T391
Test name
Test status
Simulation time 34683270854 ps
CPU time 13.29 seconds
Started Jun 21 06:54:33 PM PDT 24
Finished Jun 21 06:54:49 PM PDT 24
Peak memory 202068 kb
Host smart-fdb5e548-699f-4283-800d-c571a8a28be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184203756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1184203756
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2878101810
Short name T791
Test name
Test status
Simulation time 3194789314 ps
CPU time 7.14 seconds
Started Jun 21 06:54:31 PM PDT 24
Finished Jun 21 06:54:40 PM PDT 24
Peak memory 202008 kb
Host smart-eab9e610-7c42-49d8-ab8a-ff7a8a7ad93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878101810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2878101810
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1805612763
Short name T723
Test name
Test status
Simulation time 5772951824 ps
CPU time 10.61 seconds
Started Jun 21 06:54:21 PM PDT 24
Finished Jun 21 06:54:33 PM PDT 24
Peak memory 202056 kb
Host smart-8bc13839-d182-47d3-911c-ee50a8b6d1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805612763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1805612763
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2038735205
Short name T514
Test name
Test status
Simulation time 279849892178 ps
CPU time 841.09 seconds
Started Jun 21 06:54:28 PM PDT 24
Finished Jun 21 07:08:30 PM PDT 24
Peak memory 210812 kb
Host smart-5ceca998-2bb4-4e05-a40a-8ad79953b77f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038735205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2038735205
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2051150801
Short name T40
Test name
Test status
Simulation time 58709765645 ps
CPU time 229.28 seconds
Started Jun 21 06:54:32 PM PDT 24
Finished Jun 21 06:58:23 PM PDT 24
Peak memory 210948 kb
Host smart-fd9a372d-76c5-47aa-bdf2-0d4976eb5d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051150801 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2051150801
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.498105661
Short name T594
Test name
Test status
Simulation time 646716601 ps
CPU time 0.7 seconds
Started Jun 21 06:54:32 PM PDT 24
Finished Jun 21 06:54:35 PM PDT 24
Peak memory 201964 kb
Host smart-170966ee-7e84-4cfc-ac94-146cf97dffff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498105661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.498105661
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3374550791
Short name T266
Test name
Test status
Simulation time 162118195878 ps
CPU time 20.71 seconds
Started Jun 21 06:54:30 PM PDT 24
Finished Jun 21 06:54:52 PM PDT 24
Peak memory 202224 kb
Host smart-e5a3c85f-b2a5-49c8-8236-8525bf25b740
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374550791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3374550791
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.4103876534
Short name T284
Test name
Test status
Simulation time 372427167056 ps
CPU time 869.63 seconds
Started Jun 21 06:54:31 PM PDT 24
Finished Jun 21 07:09:02 PM PDT 24
Peak memory 202240 kb
Host smart-55bbe6a8-c157-45d4-bd1a-538871e8a2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103876534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.4103876534
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.387126132
Short name T260
Test name
Test status
Simulation time 332279038074 ps
CPU time 757.13 seconds
Started Jun 21 06:54:34 PM PDT 24
Finished Jun 21 07:07:13 PM PDT 24
Peak memory 202224 kb
Host smart-08d1fcdc-99ad-4ff4-9571-99c193d61128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387126132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.387126132
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2705988272
Short name T366
Test name
Test status
Simulation time 497707384401 ps
CPU time 1016.94 seconds
Started Jun 21 06:54:33 PM PDT 24
Finished Jun 21 07:11:32 PM PDT 24
Peak memory 202240 kb
Host smart-b6c90b40-6a35-4b6d-80f2-65d070559b2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705988272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2705988272
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.235418573
Short name T544
Test name
Test status
Simulation time 496539976560 ps
CPU time 248.43 seconds
Started Jun 21 06:54:33 PM PDT 24
Finished Jun 21 06:58:44 PM PDT 24
Peak memory 202252 kb
Host smart-3fb89b7e-8e4c-49a9-8e3e-d0a7825c89b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235418573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.235418573
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2005463184
Short name T716
Test name
Test status
Simulation time 497692218782 ps
CPU time 605.71 seconds
Started Jun 21 06:54:32 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 202228 kb
Host smart-daef02c5-de29-4b17-b831-cb4f7d6decd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005463184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2005463184
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3314771418
Short name T495
Test name
Test status
Simulation time 595931571588 ps
CPU time 1432.27 seconds
Started Jun 21 06:54:33 PM PDT 24
Finished Jun 21 07:18:27 PM PDT 24
Peak memory 202240 kb
Host smart-c526d7b7-5990-48a3-bb3e-4323c628eabf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314771418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3314771418
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1931682921
Short name T336
Test name
Test status
Simulation time 137640663550 ps
CPU time 585.92 seconds
Started Jun 21 06:54:30 PM PDT 24
Finished Jun 21 07:04:17 PM PDT 24
Peak memory 202628 kb
Host smart-f922a415-4827-48ee-9d54-9dce750bdbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931682921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1931682921
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2978243355
Short name T503
Test name
Test status
Simulation time 41023612441 ps
CPU time 92.5 seconds
Started Jun 21 06:54:33 PM PDT 24
Finished Jun 21 06:56:08 PM PDT 24
Peak memory 202080 kb
Host smart-92aac27d-dbf4-49b9-b1b3-2564387cf2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978243355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2978243355
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1987936901
Short name T430
Test name
Test status
Simulation time 4426145088 ps
CPU time 11.26 seconds
Started Jun 21 06:54:33 PM PDT 24
Finished Jun 21 06:54:46 PM PDT 24
Peak memory 202044 kb
Host smart-d79aca32-b464-44b0-a463-5341c4fbcffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987936901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1987936901
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1744327829
Short name T772
Test name
Test status
Simulation time 5782181206 ps
CPU time 13.1 seconds
Started Jun 21 06:54:33 PM PDT 24
Finished Jun 21 06:54:48 PM PDT 24
Peak memory 202040 kb
Host smart-e6962eca-eb5b-428e-ad44-58d5b80d0717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744327829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1744327829
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3180103415
Short name T256
Test name
Test status
Simulation time 217755598051 ps
CPU time 460.23 seconds
Started Jun 21 06:54:34 PM PDT 24
Finished Jun 21 07:02:16 PM PDT 24
Peak memory 202244 kb
Host smart-5a95f98a-24ec-4599-b48e-19871638d673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180103415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3180103415
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2948251088
Short name T64
Test name
Test status
Simulation time 147400746653 ps
CPU time 196.78 seconds
Started Jun 21 06:54:32 PM PDT 24
Finished Jun 21 06:57:51 PM PDT 24
Peak memory 218676 kb
Host smart-4f0f4707-6251-4c4f-bad3-e59331bc572c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948251088 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2948251088
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2249026731
Short name T680
Test name
Test status
Simulation time 356489275 ps
CPU time 1.29 seconds
Started Jun 21 06:51:11 PM PDT 24
Finished Jun 21 06:51:15 PM PDT 24
Peak memory 201936 kb
Host smart-3d7c0344-ef49-42d0-870d-0ef224ae6c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249026731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2249026731
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.930273523
Short name T84
Test name
Test status
Simulation time 173433949442 ps
CPU time 294.06 seconds
Started Jun 21 06:51:01 PM PDT 24
Finished Jun 21 06:55:58 PM PDT 24
Peak memory 202208 kb
Host smart-cd41c58c-54d2-4844-b31c-8912594f117e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930273523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.930273523
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.949046007
Short name T558
Test name
Test status
Simulation time 161231396511 ps
CPU time 38.36 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 06:51:47 PM PDT 24
Peak memory 202244 kb
Host smart-0456c8af-a9b1-4a63-b60b-a62d7a86a233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949046007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.949046007
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2224585055
Short name T553
Test name
Test status
Simulation time 498840745354 ps
CPU time 253.42 seconds
Started Jun 21 06:51:10 PM PDT 24
Finished Jun 21 06:55:27 PM PDT 24
Peak memory 202272 kb
Host smart-a27ca9f5-3d6c-4a4e-abd6-a0f4f1242f1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224585055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2224585055
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3219485477
Short name T155
Test name
Test status
Simulation time 164688791987 ps
CPU time 91.81 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 06:52:40 PM PDT 24
Peak memory 202396 kb
Host smart-a227159c-dfff-4d2e-8ed9-3fc4c485987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219485477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3219485477
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.629557953
Short name T394
Test name
Test status
Simulation time 328946654054 ps
CPU time 183.06 seconds
Started Jun 21 06:51:04 PM PDT 24
Finished Jun 21 06:54:11 PM PDT 24
Peak memory 202196 kb
Host smart-4ac230ae-ee32-4b95-88e5-42804e398714
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=629557953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.629557953
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1564517140
Short name T325
Test name
Test status
Simulation time 374690096273 ps
CPU time 757.49 seconds
Started Jun 21 06:51:10 PM PDT 24
Finished Jun 21 07:03:50 PM PDT 24
Peak memory 202300 kb
Host smart-0d0fd1c4-c58f-45ba-8718-68627dcb2c6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564517140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1564517140
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2870484530
Short name T650
Test name
Test status
Simulation time 614714416597 ps
CPU time 1480.61 seconds
Started Jun 21 06:51:10 PM PDT 24
Finished Jun 21 07:15:54 PM PDT 24
Peak memory 202220 kb
Host smart-7382c19d-9198-4c06-bfe5-f42e690f775e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870484530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2870484530
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.947647968
Short name T627
Test name
Test status
Simulation time 105890920482 ps
CPU time 403.48 seconds
Started Jun 21 06:51:04 PM PDT 24
Finished Jun 21 06:57:51 PM PDT 24
Peak memory 202504 kb
Host smart-74faaf0a-83ef-48c2-ba1d-4955775c6587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947647968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.947647968
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2861539980
Short name T434
Test name
Test status
Simulation time 35543918283 ps
CPU time 25.01 seconds
Started Jun 21 06:51:09 PM PDT 24
Finished Jun 21 06:51:37 PM PDT 24
Peak memory 202032 kb
Host smart-767c509f-d0cb-43fa-b429-87882b21e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861539980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2861539980
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3309785720
Short name T493
Test name
Test status
Simulation time 5497581621 ps
CPU time 14.11 seconds
Started Jun 21 06:51:09 PM PDT 24
Finished Jun 21 06:51:26 PM PDT 24
Peak memory 201968 kb
Host smart-57881707-8fd9-41f4-bc5a-3c6ded609256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309785720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3309785720
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1570128472
Short name T613
Test name
Test status
Simulation time 5822642247 ps
CPU time 4.35 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 06:51:13 PM PDT 24
Peak memory 202032 kb
Host smart-31812778-fad4-4500-926b-fab2a41e2d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570128472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1570128472
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3704035859
Short name T537
Test name
Test status
Simulation time 462328223 ps
CPU time 1.69 seconds
Started Jun 21 06:54:40 PM PDT 24
Finished Jun 21 06:54:44 PM PDT 24
Peak memory 201912 kb
Host smart-ac3080b1-dbaa-4d57-b792-621cc1db4816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704035859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3704035859
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1071413598
Short name T745
Test name
Test status
Simulation time 343904411208 ps
CPU time 800.67 seconds
Started Jun 21 06:54:43 PM PDT 24
Finished Jun 21 07:08:05 PM PDT 24
Peak memory 202176 kb
Host smart-e7112532-5038-4474-854d-3ac5666f1707
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071413598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1071413598
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.616670438
Short name T142
Test name
Test status
Simulation time 335548052818 ps
CPU time 775.59 seconds
Started Jun 21 06:54:39 PM PDT 24
Finished Jun 21 07:07:37 PM PDT 24
Peak memory 202248 kb
Host smart-5644efcd-3236-4de7-8b4a-864ecbf9f913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616670438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.616670438
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3742469148
Short name T115
Test name
Test status
Simulation time 332497399114 ps
CPU time 164.86 seconds
Started Jun 21 06:54:32 PM PDT 24
Finished Jun 21 06:57:19 PM PDT 24
Peak memory 202212 kb
Host smart-a379cd01-ab8c-4486-9377-06c1d6d9b7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742469148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3742469148
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.106956496
Short name T146
Test name
Test status
Simulation time 165722153186 ps
CPU time 377.31 seconds
Started Jun 21 06:54:32 PM PDT 24
Finished Jun 21 07:00:52 PM PDT 24
Peak memory 202212 kb
Host smart-5b1284b9-a4b3-4c30-92dd-38c2d588bd19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=106956496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.106956496
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3881113376
Short name T696
Test name
Test status
Simulation time 493005349095 ps
CPU time 787.37 seconds
Started Jun 21 06:54:32 PM PDT 24
Finished Jun 21 07:07:41 PM PDT 24
Peak memory 202312 kb
Host smart-872fe66b-f72e-44ad-9747-9833706b30ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881113376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3881113376
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3079921926
Short name T341
Test name
Test status
Simulation time 337286698667 ps
CPU time 762.06 seconds
Started Jun 21 06:54:34 PM PDT 24
Finished Jun 21 07:07:18 PM PDT 24
Peak memory 202196 kb
Host smart-f49b424c-5837-4d9c-8ada-eb5234af0516
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079921926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3079921926
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3358057322
Short name T708
Test name
Test status
Simulation time 645968833681 ps
CPU time 1516.65 seconds
Started Jun 21 06:54:49 PM PDT 24
Finished Jun 21 07:20:07 PM PDT 24
Peak memory 201472 kb
Host smart-87e43846-f596-4f54-8555-971522b0516c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358057322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3358057322
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4057662488
Short name T407
Test name
Test status
Simulation time 203406833976 ps
CPU time 483.12 seconds
Started Jun 21 06:54:40 PM PDT 24
Finished Jun 21 07:02:46 PM PDT 24
Peak memory 202216 kb
Host smart-5f37e2d6-1463-42ae-bfce-b1c45d3f3ae0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057662488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4057662488
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2581276625
Short name T525
Test name
Test status
Simulation time 102542171632 ps
CPU time 411.59 seconds
Started Jun 21 06:54:40 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 202540 kb
Host smart-09aa3310-52af-4c2e-b697-59db6750312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581276625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2581276625
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2142521632
Short name T388
Test name
Test status
Simulation time 22537394670 ps
CPU time 15.76 seconds
Started Jun 21 06:54:49 PM PDT 24
Finished Jun 21 06:55:06 PM PDT 24
Peak memory 201440 kb
Host smart-2ff36b9a-98e6-4ad6-b96d-68fbe3bafd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142521632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2142521632
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3612235826
Short name T534
Test name
Test status
Simulation time 5025399791 ps
CPU time 12.22 seconds
Started Jun 21 06:54:40 PM PDT 24
Finished Jun 21 06:54:55 PM PDT 24
Peak memory 202048 kb
Host smart-2935943f-ce02-47ad-8c01-64085f02a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612235826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3612235826
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3302243328
Short name T738
Test name
Test status
Simulation time 5832537439 ps
CPU time 8.23 seconds
Started Jun 21 06:54:32 PM PDT 24
Finished Jun 21 06:54:43 PM PDT 24
Peak memory 202056 kb
Host smart-7c60c958-5edd-4a0e-97c5-86284c2a1487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302243328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3302243328
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.179042712
Short name T35
Test name
Test status
Simulation time 177655137637 ps
CPU time 95.83 seconds
Started Jun 21 06:54:42 PM PDT 24
Finished Jun 21 06:56:20 PM PDT 24
Peak memory 202244 kb
Host smart-6c8508ad-ed87-4675-8f89-dc54bdaa0e10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179042712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
179042712
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1567006907
Short name T694
Test name
Test status
Simulation time 507050878 ps
CPU time 0.73 seconds
Started Jun 21 06:54:53 PM PDT 24
Finished Jun 21 06:54:57 PM PDT 24
Peak memory 201912 kb
Host smart-577a9e06-3ce3-42e2-88d4-f132ec83f83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567006907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1567006907
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1600658170
Short name T587
Test name
Test status
Simulation time 466387640952 ps
CPU time 504.53 seconds
Started Jun 21 06:54:42 PM PDT 24
Finished Jun 21 07:03:09 PM PDT 24
Peak memory 202180 kb
Host smart-ad4cd8c1-c4d8-43bf-a49f-3754f75c6b8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600658170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1600658170
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3974056293
Short name T264
Test name
Test status
Simulation time 524197183385 ps
CPU time 498.52 seconds
Started Jun 21 06:54:40 PM PDT 24
Finished Jun 21 07:03:01 PM PDT 24
Peak memory 202308 kb
Host smart-62781b9b-4070-46d3-9eb6-ddb3446577a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974056293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3974056293
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2256455754
Short name T704
Test name
Test status
Simulation time 484088290598 ps
CPU time 543.75 seconds
Started Jun 21 06:54:41 PM PDT 24
Finished Jun 21 07:03:47 PM PDT 24
Peak memory 202308 kb
Host smart-a208e97c-e858-4ace-9b2c-d6e48d38e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256455754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2256455754
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2260454473
Short name T441
Test name
Test status
Simulation time 328357806799 ps
CPU time 193.37 seconds
Started Jun 21 06:54:49 PM PDT 24
Finished Jun 21 06:58:04 PM PDT 24
Peak memory 202168 kb
Host smart-18bd4d5d-4447-4fde-9f76-611d750d77a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260454473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2260454473
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.221342011
Short name T168
Test name
Test status
Simulation time 487693414343 ps
CPU time 582.08 seconds
Started Jun 21 06:54:40 PM PDT 24
Finished Jun 21 07:04:24 PM PDT 24
Peak memory 202324 kb
Host smart-ce2aadeb-e500-4c91-b9a3-e76d09b3ed90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221342011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.221342011
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2623747336
Short name T632
Test name
Test status
Simulation time 496887429762 ps
CPU time 1178.99 seconds
Started Jun 21 06:54:50 PM PDT 24
Finished Jun 21 07:14:30 PM PDT 24
Peak memory 202168 kb
Host smart-c643408d-654e-4d9c-8a28-bee5c7fcc9fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623747336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2623747336
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3031753804
Short name T289
Test name
Test status
Simulation time 447578241030 ps
CPU time 243.17 seconds
Started Jun 21 06:54:48 PM PDT 24
Finished Jun 21 06:58:53 PM PDT 24
Peak memory 202188 kb
Host smart-776ddad5-fc9e-42ef-a21d-04600505e704
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031753804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3031753804
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3334111444
Short name T570
Test name
Test status
Simulation time 189560483237 ps
CPU time 101.63 seconds
Started Jun 21 06:54:40 PM PDT 24
Finished Jun 21 06:56:24 PM PDT 24
Peak memory 202172 kb
Host smart-c7c045ca-dbb0-4c72-a5d7-00091f49f4b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334111444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3334111444
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2140793987
Short name T50
Test name
Test status
Simulation time 121792844041 ps
CPU time 500.57 seconds
Started Jun 21 06:54:53 PM PDT 24
Finished Jun 21 07:03:16 PM PDT 24
Peak memory 202556 kb
Host smart-04312726-0cbb-47a0-b4d5-defb07519b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140793987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2140793987
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1499125892
Short name T476
Test name
Test status
Simulation time 42523230329 ps
CPU time 25.1 seconds
Started Jun 21 06:54:51 PM PDT 24
Finished Jun 21 06:55:17 PM PDT 24
Peak memory 202004 kb
Host smart-21b3ba7a-41c6-40d9-b8d1-c867d8abda6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499125892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1499125892
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2797831160
Short name T501
Test name
Test status
Simulation time 4267308058 ps
CPU time 9.75 seconds
Started Jun 21 06:54:55 PM PDT 24
Finished Jun 21 06:55:07 PM PDT 24
Peak memory 202072 kb
Host smart-4cbde3db-f7f0-472b-bedb-c76d1c9c542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797831160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2797831160
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1637523940
Short name T607
Test name
Test status
Simulation time 5828041348 ps
CPU time 6.75 seconds
Started Jun 21 06:54:41 PM PDT 24
Finished Jun 21 06:54:50 PM PDT 24
Peak memory 202036 kb
Host smart-49c7c860-070b-4944-8349-8d90d6290965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637523940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1637523940
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.4104325138
Short name T431
Test name
Test status
Simulation time 334077099332 ps
CPU time 215.6 seconds
Started Jun 21 06:54:53 PM PDT 24
Finished Jun 21 06:58:32 PM PDT 24
Peak memory 202220 kb
Host smart-87fd833c-a748-4e92-ac1f-da7eb8642c17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104325138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.4104325138
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3570183901
Short name T280
Test name
Test status
Simulation time 66586499853 ps
CPU time 161.13 seconds
Started Jun 21 06:54:54 PM PDT 24
Finished Jun 21 06:57:38 PM PDT 24
Peak memory 210548 kb
Host smart-89bc62d7-b4aa-4fbb-afd4-94eca56cb4d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570183901 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3570183901
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3986167381
Short name T81
Test name
Test status
Simulation time 308465853 ps
CPU time 1.33 seconds
Started Jun 21 06:54:53 PM PDT 24
Finished Jun 21 06:54:57 PM PDT 24
Peak memory 201920 kb
Host smart-e831e11a-c694-4710-a749-fd4725a5edca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986167381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3986167381
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1196519478
Short name T138
Test name
Test status
Simulation time 351764762968 ps
CPU time 594.73 seconds
Started Jun 21 06:54:51 PM PDT 24
Finished Jun 21 07:04:48 PM PDT 24
Peak memory 202224 kb
Host smart-6d7589d9-dafe-44b4-a8da-ff15f8faece4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196519478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1196519478
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.128495269
Short name T119
Test name
Test status
Simulation time 493507635268 ps
CPU time 276.21 seconds
Started Jun 21 06:54:53 PM PDT 24
Finished Jun 21 06:59:32 PM PDT 24
Peak memory 202316 kb
Host smart-f784819c-7fed-4be7-9845-f4ec6c2e74e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128495269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.128495269
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4163859078
Short name T541
Test name
Test status
Simulation time 338659338798 ps
CPU time 824.79 seconds
Started Jun 21 06:54:53 PM PDT 24
Finished Jun 21 07:08:41 PM PDT 24
Peak memory 202308 kb
Host smart-6703e34d-a711-4fd3-b3de-8a2720b1cf56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163859078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4163859078
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4252484939
Short name T697
Test name
Test status
Simulation time 172431711336 ps
CPU time 222.42 seconds
Started Jun 21 06:54:52 PM PDT 24
Finished Jun 21 06:58:37 PM PDT 24
Peak memory 202296 kb
Host smart-52667509-80bc-4c87-af81-8b53efabee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252484939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4252484939
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1677175972
Short name T468
Test name
Test status
Simulation time 494159214782 ps
CPU time 579.67 seconds
Started Jun 21 06:54:52 PM PDT 24
Finished Jun 21 07:04:35 PM PDT 24
Peak memory 202292 kb
Host smart-b57c0c41-2472-4052-8596-455caa2a6d6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677175972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1677175972
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1915064610
Short name T319
Test name
Test status
Simulation time 275546757721 ps
CPU time 102.35 seconds
Started Jun 21 06:54:56 PM PDT 24
Finished Jun 21 06:56:40 PM PDT 24
Peak memory 202324 kb
Host smart-eac1d43d-0fe6-4884-afc4-ae12a1c4b101
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915064610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1915064610
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3508462638
Short name T456
Test name
Test status
Simulation time 607602521145 ps
CPU time 1318.45 seconds
Started Jun 21 06:54:52 PM PDT 24
Finished Jun 21 07:16:53 PM PDT 24
Peak memory 202216 kb
Host smart-867ee067-f2f9-4502-be99-e0e36e947a58
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508462638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3508462638
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3314134498
Short name T741
Test name
Test status
Simulation time 108803361076 ps
CPU time 564.85 seconds
Started Jun 21 06:54:52 PM PDT 24
Finished Jun 21 07:04:20 PM PDT 24
Peak memory 202548 kb
Host smart-b0e14c2c-6f10-4f6d-8574-a5886cc7a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314134498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3314134498
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3262065898
Short name T664
Test name
Test status
Simulation time 33053033159 ps
CPU time 67.85 seconds
Started Jun 21 06:54:55 PM PDT 24
Finished Jun 21 06:56:05 PM PDT 24
Peak memory 202076 kb
Host smart-103b0a30-afa7-4851-b4a6-2f736c6ee3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262065898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3262065898
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3416038336
Short name T759
Test name
Test status
Simulation time 3308861920 ps
CPU time 4.64 seconds
Started Jun 21 06:54:51 PM PDT 24
Finished Jun 21 06:54:57 PM PDT 24
Peak memory 202004 kb
Host smart-d1795525-1294-45a1-b02d-334fa3bd7a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416038336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3416038336
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2212217280
Short name T569
Test name
Test status
Simulation time 6026604816 ps
CPU time 4.32 seconds
Started Jun 21 06:54:53 PM PDT 24
Finished Jun 21 06:55:00 PM PDT 24
Peak memory 202020 kb
Host smart-df7913d1-a25f-491d-ac82-b5228215f201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212217280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2212217280
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1593570447
Short name T646
Test name
Test status
Simulation time 12610837658 ps
CPU time 31.86 seconds
Started Jun 21 06:54:53 PM PDT 24
Finished Jun 21 06:55:28 PM PDT 24
Peak memory 202316 kb
Host smart-c3a2d626-2e1b-423b-9670-45953869c037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593570447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1593570447
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3912199173
Short name T240
Test name
Test status
Simulation time 73136524274 ps
CPU time 52.16 seconds
Started Jun 21 06:54:52 PM PDT 24
Finished Jun 21 06:55:47 PM PDT 24
Peak memory 210628 kb
Host smart-3be6e60c-7a84-4d46-940a-ac62be34c3e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912199173 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3912199173
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1767241890
Short name T73
Test name
Test status
Simulation time 517835645 ps
CPU time 1.7 seconds
Started Jun 21 06:55:07 PM PDT 24
Finished Jun 21 06:55:11 PM PDT 24
Peak memory 201940 kb
Host smart-c4047ae2-293a-48ca-9547-8c37de583381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767241890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1767241890
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1644910925
Short name T326
Test name
Test status
Simulation time 184594010659 ps
CPU time 424.65 seconds
Started Jun 21 06:55:08 PM PDT 24
Finished Jun 21 07:02:15 PM PDT 24
Peak memory 202320 kb
Host smart-7b212e41-2be9-4cd8-82a4-bcfec3276dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644910925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1644910925
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2726827265
Short name T27
Test name
Test status
Simulation time 163188859861 ps
CPU time 352.75 seconds
Started Jun 21 06:54:55 PM PDT 24
Finished Jun 21 07:00:51 PM PDT 24
Peak memory 202412 kb
Host smart-db1f067f-06d2-4478-b63f-e4ea4ae6356b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726827265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2726827265
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3032851562
Short name T221
Test name
Test status
Simulation time 164867489665 ps
CPU time 388.46 seconds
Started Jun 21 06:54:56 PM PDT 24
Finished Jun 21 07:01:27 PM PDT 24
Peak memory 202104 kb
Host smart-b64b862f-fa6c-496d-9049-a64cf26f76ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032851562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3032851562
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1681759558
Short name T386
Test name
Test status
Simulation time 161553586432 ps
CPU time 73.16 seconds
Started Jun 21 06:54:54 PM PDT 24
Finished Jun 21 06:56:10 PM PDT 24
Peak memory 202240 kb
Host smart-90143507-2efd-4d2d-baa4-08d7fb23fbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681759558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1681759558
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2247229320
Short name T465
Test name
Test status
Simulation time 161251189835 ps
CPU time 77.46 seconds
Started Jun 21 06:54:56 PM PDT 24
Finished Jun 21 06:56:16 PM PDT 24
Peak memory 202120 kb
Host smart-aa5818cc-7e4a-488a-9c16-69c2008764ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247229320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2247229320
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3397943034
Short name T307
Test name
Test status
Simulation time 547628481916 ps
CPU time 1298.36 seconds
Started Jun 21 06:54:54 PM PDT 24
Finished Jun 21 07:16:35 PM PDT 24
Peak memory 202228 kb
Host smart-120ad5f4-442b-43d6-b2e6-a18fdd99806c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397943034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3397943034
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2977900839
Short name T448
Test name
Test status
Simulation time 607130817534 ps
CPU time 367.52 seconds
Started Jun 21 06:54:54 PM PDT 24
Finished Jun 21 07:01:05 PM PDT 24
Peak memory 202288 kb
Host smart-93416f1e-f7d6-486e-869f-0be232f75159
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977900839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2977900839
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2376662665
Short name T644
Test name
Test status
Simulation time 81519861836 ps
CPU time 292.95 seconds
Started Jun 21 06:55:06 PM PDT 24
Finished Jun 21 07:00:00 PM PDT 24
Peak memory 202548 kb
Host smart-88dcdc1f-73ce-4be9-97ad-7906121d0dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376662665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2376662665
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1198385290
Short name T635
Test name
Test status
Simulation time 34810137673 ps
CPU time 39.28 seconds
Started Jun 21 06:55:08 PM PDT 24
Finished Jun 21 06:55:50 PM PDT 24
Peak memory 202096 kb
Host smart-312a7d16-7f02-49a1-b3c2-97dec6bd1a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198385290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1198385290
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.769970409
Short name T556
Test name
Test status
Simulation time 4888164423 ps
CPU time 12.25 seconds
Started Jun 21 06:55:07 PM PDT 24
Finished Jun 21 06:55:23 PM PDT 24
Peak memory 202048 kb
Host smart-eb4e2a5e-2095-45b6-b99d-80ecd1f124dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769970409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.769970409
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1391036845
Short name T645
Test name
Test status
Simulation time 5895609119 ps
CPU time 14.59 seconds
Started Jun 21 06:54:52 PM PDT 24
Finished Jun 21 06:55:10 PM PDT 24
Peak memory 202052 kb
Host smart-f75684a7-e933-4338-9f21-7d695aa33ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391036845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1391036845
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.146762146
Short name T32
Test name
Test status
Simulation time 35196427961 ps
CPU time 101.04 seconds
Started Jun 21 06:55:09 PM PDT 24
Finished Jun 21 06:56:54 PM PDT 24
Peak memory 210880 kb
Host smart-453b891a-6abb-4dc0-b75e-bf98ca858dad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146762146 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.146762146
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1914813282
Short name T668
Test name
Test status
Simulation time 411428659 ps
CPU time 1.02 seconds
Started Jun 21 06:55:14 PM PDT 24
Finished Jun 21 06:55:19 PM PDT 24
Peak memory 201940 kb
Host smart-416a432d-3428-47e7-b45c-b31face0144c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914813282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1914813282
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1304825822
Short name T130
Test name
Test status
Simulation time 364246837814 ps
CPU time 479.62 seconds
Started Jun 21 06:55:07 PM PDT 24
Finished Jun 21 07:03:09 PM PDT 24
Peak memory 202300 kb
Host smart-c277280b-0677-4ed0-868e-a359cc5db13e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304825822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1304825822
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1865114045
Short name T312
Test name
Test status
Simulation time 501741885117 ps
CPU time 328.56 seconds
Started Jun 21 06:55:08 PM PDT 24
Finished Jun 21 07:00:40 PM PDT 24
Peak memory 202416 kb
Host smart-68db59b3-7f45-4459-b093-dfbe3c7ab768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865114045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1865114045
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.580548639
Short name T291
Test name
Test status
Simulation time 155771853503 ps
CPU time 103.94 seconds
Started Jun 21 06:55:07 PM PDT 24
Finished Jun 21 06:56:54 PM PDT 24
Peak memory 202216 kb
Host smart-c69ca49d-dc30-4aa8-bc71-2118bb6ffaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580548639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.580548639
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1480162337
Short name T404
Test name
Test status
Simulation time 321860896185 ps
CPU time 384.43 seconds
Started Jun 21 06:55:07 PM PDT 24
Finished Jun 21 07:01:33 PM PDT 24
Peak memory 202208 kb
Host smart-94f77473-a90c-465d-838f-c58a8138099e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480162337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1480162337
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.466939397
Short name T114
Test name
Test status
Simulation time 494025991358 ps
CPU time 517.62 seconds
Started Jun 21 06:55:07 PM PDT 24
Finished Jun 21 07:03:48 PM PDT 24
Peak memory 202216 kb
Host smart-541502c1-36ab-449d-b7ff-cf4a1b513b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466939397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.466939397
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.365350179
Short name T486
Test name
Test status
Simulation time 495754611266 ps
CPU time 423.3 seconds
Started Jun 21 06:55:07 PM PDT 24
Finished Jun 21 07:02:13 PM PDT 24
Peak memory 202204 kb
Host smart-33c70dbd-6125-463a-86de-4f7efcdc1cbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=365350179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.365350179
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1535025220
Short name T582
Test name
Test status
Simulation time 162316632823 ps
CPU time 357.66 seconds
Started Jun 21 06:55:08 PM PDT 24
Finished Jun 21 07:01:09 PM PDT 24
Peak memory 202228 kb
Host smart-3c9ed1d0-8f80-4319-be90-9371f8bd6c40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535025220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1535025220
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3572578056
Short name T228
Test name
Test status
Simulation time 404343306023 ps
CPU time 425.06 seconds
Started Jun 21 06:55:07 PM PDT 24
Finished Jun 21 07:02:15 PM PDT 24
Peak memory 202208 kb
Host smart-b13fe719-6c91-42c7-9024-4233ff13d2b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572578056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3572578056
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1456699081
Short name T581
Test name
Test status
Simulation time 98047111850 ps
CPU time 319.44 seconds
Started Jun 21 06:55:14 PM PDT 24
Finished Jun 21 07:00:38 PM PDT 24
Peak memory 202600 kb
Host smart-66137d77-2ee8-4015-a9b5-912e7742f1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456699081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1456699081
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1179632501
Short name T555
Test name
Test status
Simulation time 22164731403 ps
CPU time 51.65 seconds
Started Jun 21 06:55:08 PM PDT 24
Finished Jun 21 06:56:03 PM PDT 24
Peak memory 202072 kb
Host smart-f4171a3d-0302-4076-8778-9d98b64cb004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179632501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1179632501
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.530350890
Short name T629
Test name
Test status
Simulation time 3730040322 ps
CPU time 8.94 seconds
Started Jun 21 06:55:08 PM PDT 24
Finished Jun 21 06:55:21 PM PDT 24
Peak memory 202048 kb
Host smart-273694e3-8625-43be-9a1f-276009629c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530350890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.530350890
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2482958969
Short name T578
Test name
Test status
Simulation time 6115588398 ps
CPU time 15.11 seconds
Started Jun 21 06:55:10 PM PDT 24
Finished Jun 21 06:55:29 PM PDT 24
Peak memory 202040 kb
Host smart-fa53a9a6-270d-4ccb-9fea-9b2889d7ef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482958969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2482958969
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3465665249
Short name T43
Test name
Test status
Simulation time 94949751564 ps
CPU time 199.88 seconds
Started Jun 21 06:55:14 PM PDT 24
Finished Jun 21 06:58:38 PM PDT 24
Peak memory 210944 kb
Host smart-57a23fac-e212-443e-9f93-3399b3343fa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465665249 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3465665249
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.239840378
Short name T85
Test name
Test status
Simulation time 363756745 ps
CPU time 0.86 seconds
Started Jun 21 06:55:18 PM PDT 24
Finished Jun 21 06:55:22 PM PDT 24
Peak memory 201920 kb
Host smart-b1803a1b-48ce-49b2-a506-0686b037e02e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239840378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.239840378
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2084458669
Short name T226
Test name
Test status
Simulation time 500302009198 ps
CPU time 1087.62 seconds
Started Jun 21 06:55:16 PM PDT 24
Finished Jun 21 07:13:27 PM PDT 24
Peak memory 202232 kb
Host smart-fc16cb3f-8d36-4f99-9083-0df9c0b3cad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084458669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2084458669
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1685170609
Short name T488
Test name
Test status
Simulation time 329256335807 ps
CPU time 342.71 seconds
Started Jun 21 06:55:12 PM PDT 24
Finished Jun 21 07:00:59 PM PDT 24
Peak memory 202296 kb
Host smart-9aded3b5-9072-48ad-8b16-8055582130cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685170609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1685170609
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3751381063
Short name T567
Test name
Test status
Simulation time 164610934686 ps
CPU time 345.1 seconds
Started Jun 21 06:55:14 PM PDT 24
Finished Jun 21 07:01:03 PM PDT 24
Peak memory 202260 kb
Host smart-67ff781b-542c-41fd-baeb-4291a3754c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751381063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3751381063
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1172744937
Short name T669
Test name
Test status
Simulation time 163713369354 ps
CPU time 368.69 seconds
Started Jun 21 06:55:14 PM PDT 24
Finished Jun 21 07:01:26 PM PDT 24
Peak memory 202212 kb
Host smart-6614200d-c309-4045-8123-07058379ebd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172744937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1172744937
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1712419512
Short name T117
Test name
Test status
Simulation time 194187156604 ps
CPU time 339.37 seconds
Started Jun 21 06:55:15 PM PDT 24
Finished Jun 21 07:00:59 PM PDT 24
Peak memory 202240 kb
Host smart-19fb8352-cafc-4a0d-9abe-522e6ffa4836
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712419512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1712419512
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2226994233
Short name T444
Test name
Test status
Simulation time 206355859070 ps
CPU time 478.98 seconds
Started Jun 21 06:55:12 PM PDT 24
Finished Jun 21 07:03:15 PM PDT 24
Peak memory 202284 kb
Host smart-f8736d13-0e08-4553-b6a1-cc99db2d56de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226994233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2226994233
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.4095240760
Short name T375
Test name
Test status
Simulation time 43452126999 ps
CPU time 46.64 seconds
Started Jun 21 06:55:12 PM PDT 24
Finished Jun 21 06:56:02 PM PDT 24
Peak memory 202056 kb
Host smart-4119b69e-e4b9-4c73-b429-d8ea0b2594f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095240760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.4095240760
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.871864160
Short name T614
Test name
Test status
Simulation time 5380553128 ps
CPU time 3.65 seconds
Started Jun 21 06:55:15 PM PDT 24
Finished Jun 21 06:55:23 PM PDT 24
Peak memory 202060 kb
Host smart-ec5d4a6b-1936-42cd-a381-062ab9d89570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871864160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.871864160
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.697910373
Short name T403
Test name
Test status
Simulation time 5940676543 ps
CPU time 7.73 seconds
Started Jun 21 06:55:14 PM PDT 24
Finished Jun 21 06:55:26 PM PDT 24
Peak memory 202168 kb
Host smart-1d9357d4-876e-40e0-ba47-d782fe5349e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697910373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.697910373
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3029436989
Short name T44
Test name
Test status
Simulation time 51484672596 ps
CPU time 71.12 seconds
Started Jun 21 06:55:13 PM PDT 24
Finished Jun 21 06:56:28 PM PDT 24
Peak memory 202772 kb
Host smart-c580f77d-5b4c-4214-8b8d-325deb7fd917
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029436989 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3029436989
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3752319157
Short name T516
Test name
Test status
Simulation time 335927728 ps
CPU time 1.32 seconds
Started Jun 21 06:55:23 PM PDT 24
Finished Jun 21 06:55:29 PM PDT 24
Peak memory 201912 kb
Host smart-debe1991-aefb-497f-ba98-3f3bfa98eb25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752319157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3752319157
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2183462570
Short name T443
Test name
Test status
Simulation time 505157749326 ps
CPU time 220.22 seconds
Started Jun 21 06:55:26 PM PDT 24
Finished Jun 21 06:59:10 PM PDT 24
Peak memory 202304 kb
Host smart-bdac76b7-a258-470d-9b4f-64d90c09ce6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183462570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2183462570
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3444791144
Short name T603
Test name
Test status
Simulation time 164063117041 ps
CPU time 119.89 seconds
Started Jun 21 06:55:21 PM PDT 24
Finished Jun 21 06:57:25 PM PDT 24
Peak memory 202268 kb
Host smart-8cc2e05f-bca0-496e-9a4a-80718454e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444791144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3444791144
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1384016790
Short name T183
Test name
Test status
Simulation time 492868587314 ps
CPU time 307.88 seconds
Started Jun 21 06:55:23 PM PDT 24
Finished Jun 21 07:00:36 PM PDT 24
Peak memory 202320 kb
Host smart-a626d1a6-15ed-4832-a74d-45df00487d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384016790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1384016790
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2358036459
Short name T633
Test name
Test status
Simulation time 494083204548 ps
CPU time 127.5 seconds
Started Jun 21 06:55:23 PM PDT 24
Finished Jun 21 06:57:35 PM PDT 24
Peak memory 202204 kb
Host smart-58ad9824-6603-4c41-b31f-9c9ac87e60cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358036459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2358036459
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1415442755
Short name T216
Test name
Test status
Simulation time 162188053970 ps
CPU time 365.03 seconds
Started Jun 21 06:55:24 PM PDT 24
Finished Jun 21 07:01:34 PM PDT 24
Peak memory 202240 kb
Host smart-fdbc7b1f-b96b-4312-ae26-3eb49d11ebc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415442755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1415442755
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2754010738
Short name T365
Test name
Test status
Simulation time 499279470706 ps
CPU time 408.35 seconds
Started Jun 21 06:55:25 PM PDT 24
Finished Jun 21 07:02:18 PM PDT 24
Peak memory 202212 kb
Host smart-69c9f1af-ace3-4365-ab28-58e0c2e9db30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754010738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2754010738
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.4105177612
Short name T475
Test name
Test status
Simulation time 373332863639 ps
CPU time 822.99 seconds
Started Jun 21 06:55:25 PM PDT 24
Finished Jun 21 07:09:12 PM PDT 24
Peak memory 202312 kb
Host smart-0aa7746c-8276-4734-ae79-9e174f131051
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105177612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.4105177612
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2573463507
Short name T400
Test name
Test status
Simulation time 210168626361 ps
CPU time 87.42 seconds
Started Jun 21 06:55:22 PM PDT 24
Finished Jun 21 06:56:53 PM PDT 24
Peak memory 202260 kb
Host smart-0fdcc051-87ec-4653-87f8-4aa1246c32c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573463507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2573463507
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1510300557
Short name T532
Test name
Test status
Simulation time 81185076526 ps
CPU time 280.52 seconds
Started Jun 21 06:55:23 PM PDT 24
Finished Jun 21 07:00:09 PM PDT 24
Peak memory 202596 kb
Host smart-7b125a36-43ed-4ecb-aaab-1a996d08fd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510300557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1510300557
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.983574618
Short name T647
Test name
Test status
Simulation time 34266438908 ps
CPU time 82.47 seconds
Started Jun 21 06:55:23 PM PDT 24
Finished Jun 21 06:56:51 PM PDT 24
Peak memory 202048 kb
Host smart-f4b0861e-8a63-4851-a6e4-166f64bf439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983574618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.983574618
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3848180587
Short name T572
Test name
Test status
Simulation time 3851786303 ps
CPU time 8.81 seconds
Started Jun 21 06:55:23 PM PDT 24
Finished Jun 21 06:55:37 PM PDT 24
Peak memory 202024 kb
Host smart-0d6d0994-e5d0-4902-9a56-a7a0bd727d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848180587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3848180587
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.263468471
Short name T112
Test name
Test status
Simulation time 5683521776 ps
CPU time 13.95 seconds
Started Jun 21 06:55:12 PM PDT 24
Finished Jun 21 06:55:29 PM PDT 24
Peak memory 202052 kb
Host smart-d8a0db05-cea7-42f3-8563-598220082e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263468471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.263468471
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2111304461
Short name T230
Test name
Test status
Simulation time 329577066529 ps
CPU time 794.49 seconds
Started Jun 21 06:55:23 PM PDT 24
Finished Jun 21 07:08:43 PM PDT 24
Peak memory 202228 kb
Host smart-a61fe8c1-75f7-429d-b68c-5b57db6227cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111304461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2111304461
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.639599293
Short name T417
Test name
Test status
Simulation time 521657716 ps
CPU time 0.89 seconds
Started Jun 21 06:55:32 PM PDT 24
Finished Jun 21 06:55:34 PM PDT 24
Peak memory 201944 kb
Host smart-2588ae1f-057a-4838-bdbd-121c5843af6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639599293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.639599293
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3904890603
Short name T229
Test name
Test status
Simulation time 529865443029 ps
CPU time 1207.42 seconds
Started Jun 21 06:55:32 PM PDT 24
Finished Jun 21 07:15:41 PM PDT 24
Peak memory 202224 kb
Host smart-1b9ca5bb-c90b-4c12-b606-f41fd9d21ba7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904890603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3904890603
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2199652175
Short name T583
Test name
Test status
Simulation time 165465163850 ps
CPU time 373.53 seconds
Started Jun 21 06:55:33 PM PDT 24
Finished Jun 21 07:01:49 PM PDT 24
Peak memory 202224 kb
Host smart-bc2b5a55-c73a-4dfb-b2b8-cdce94582371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199652175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2199652175
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1435773417
Short name T747
Test name
Test status
Simulation time 171184756573 ps
CPU time 95.02 seconds
Started Jun 21 06:55:34 PM PDT 24
Finished Jun 21 06:57:12 PM PDT 24
Peak memory 202180 kb
Host smart-67864fb7-1991-432c-bc9a-231112611504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435773417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1435773417
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3577765158
Short name T131
Test name
Test status
Simulation time 329753591589 ps
CPU time 52.69 seconds
Started Jun 21 06:55:34 PM PDT 24
Finished Jun 21 06:56:29 PM PDT 24
Peak memory 202220 kb
Host smart-f6041c70-0316-40b1-9f98-ec21b621bb35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577765158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3577765158
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.378429031
Short name T10
Test name
Test status
Simulation time 493250040396 ps
CPU time 623.35 seconds
Started Jun 21 06:55:26 PM PDT 24
Finished Jun 21 07:05:53 PM PDT 24
Peak memory 202236 kb
Host smart-ecfb62d1-0712-4115-a52b-efd2e74d818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378429031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.378429031
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3409030966
Short name T705
Test name
Test status
Simulation time 488085677517 ps
CPU time 1082.62 seconds
Started Jun 21 06:55:22 PM PDT 24
Finished Jun 21 07:13:30 PM PDT 24
Peak memory 202164 kb
Host smart-114f68f8-5447-4e78-83c1-93eab79230bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409030966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3409030966
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3367958479
Short name T681
Test name
Test status
Simulation time 173704641878 ps
CPU time 212.13 seconds
Started Jun 21 06:55:33 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 202276 kb
Host smart-eb37993e-02f3-4b41-a2b1-3979cf4158bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367958479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3367958479
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1138221894
Short name T733
Test name
Test status
Simulation time 201425523261 ps
CPU time 225.58 seconds
Started Jun 21 06:55:33 PM PDT 24
Finished Jun 21 06:59:20 PM PDT 24
Peak memory 202272 kb
Host smart-442c72fd-2f6b-43a6-9ce9-916d332f8cf0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138221894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1138221894
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3397780905
Short name T51
Test name
Test status
Simulation time 121228707661 ps
CPU time 462.9 seconds
Started Jun 21 06:55:34 PM PDT 24
Finished Jun 21 07:03:19 PM PDT 24
Peak memory 202624 kb
Host smart-8e45dc1d-4163-437c-85f4-842d2fb0c58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397780905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3397780905
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1848600053
Short name T135
Test name
Test status
Simulation time 31256803154 ps
CPU time 16.33 seconds
Started Jun 21 06:55:35 PM PDT 24
Finished Jun 21 06:55:53 PM PDT 24
Peak memory 202084 kb
Host smart-28f38a4c-6ff1-42e3-b1a8-86cd9f812b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848600053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1848600053
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2198754914
Short name T347
Test name
Test status
Simulation time 2996779804 ps
CPU time 7.68 seconds
Started Jun 21 06:55:36 PM PDT 24
Finished Jun 21 06:55:45 PM PDT 24
Peak memory 202056 kb
Host smart-8460d93f-fb37-41f2-9883-4fed37017a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198754914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2198754914
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2476076897
Short name T478
Test name
Test status
Simulation time 5960449114 ps
CPU time 16.33 seconds
Started Jun 21 06:55:25 PM PDT 24
Finished Jun 21 06:55:46 PM PDT 24
Peak memory 202052 kb
Host smart-4a4717bc-130e-43a1-96be-63f795977f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476076897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2476076897
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1329797270
Short name T36
Test name
Test status
Simulation time 340136638583 ps
CPU time 1064.05 seconds
Started Jun 21 06:55:34 PM PDT 24
Finished Jun 21 07:13:20 PM PDT 24
Peak memory 210808 kb
Host smart-66b9cb6d-3c9e-470a-ae6c-95e2eff0bcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329797270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1329797270
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3015418746
Short name T709
Test name
Test status
Simulation time 15679541379 ps
CPU time 49.93 seconds
Started Jun 21 06:55:35 PM PDT 24
Finished Jun 21 06:56:27 PM PDT 24
Peak memory 210940 kb
Host smart-8d086a3d-c4b8-4c32-b6b4-b97afbd8105c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015418746 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3015418746
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1263969236
Short name T706
Test name
Test status
Simulation time 375821332 ps
CPU time 1.51 seconds
Started Jun 21 06:55:45 PM PDT 24
Finished Jun 21 06:55:48 PM PDT 24
Peak memory 201884 kb
Host smart-2692f6da-798f-4375-a2b5-8f288e4cee2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263969236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1263969236
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2910053108
Short name T156
Test name
Test status
Simulation time 323137503803 ps
CPU time 69.43 seconds
Started Jun 21 06:55:44 PM PDT 24
Finished Jun 21 06:56:55 PM PDT 24
Peak memory 202344 kb
Host smart-bb2e695b-0080-4883-94d3-45914341cb56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910053108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2910053108
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3567489467
Short name T620
Test name
Test status
Simulation time 328303435322 ps
CPU time 302.68 seconds
Started Jun 21 06:55:33 PM PDT 24
Finished Jun 21 07:00:37 PM PDT 24
Peak memory 202188 kb
Host smart-5ab16617-3b4e-4a18-a633-56e905618c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567489467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3567489467
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.655705246
Short name T566
Test name
Test status
Simulation time 490777444841 ps
CPU time 564.5 seconds
Started Jun 21 06:55:33 PM PDT 24
Finished Jun 21 07:05:00 PM PDT 24
Peak memory 202200 kb
Host smart-e2c14fa9-362a-4b55-b3af-f75349cb3a08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=655705246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.655705246
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.4123250019
Short name T150
Test name
Test status
Simulation time 491997714390 ps
CPU time 277.43 seconds
Started Jun 21 06:55:33 PM PDT 24
Finished Jun 21 07:00:13 PM PDT 24
Peak memory 202300 kb
Host smart-86b01244-91d5-4b3f-8c7b-4479f1765816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123250019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4123250019
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1493614477
Short name T371
Test name
Test status
Simulation time 320790967315 ps
CPU time 755.84 seconds
Started Jun 21 06:55:33 PM PDT 24
Finished Jun 21 07:08:11 PM PDT 24
Peak memory 202248 kb
Host smart-ee193e3e-2ee4-4303-b22d-27c1636dc037
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493614477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1493614477
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2927399369
Short name T248
Test name
Test status
Simulation time 169244099516 ps
CPU time 296.4 seconds
Started Jun 21 06:55:33 PM PDT 24
Finished Jun 21 07:00:32 PM PDT 24
Peak memory 202316 kb
Host smart-0d34720f-ead6-4456-8fc8-e0e212a7a539
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927399369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2927399369
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1980317342
Short name T727
Test name
Test status
Simulation time 622814462656 ps
CPU time 250.02 seconds
Started Jun 21 06:55:44 PM PDT 24
Finished Jun 21 06:59:57 PM PDT 24
Peak memory 202212 kb
Host smart-7eef7873-85c4-40e2-8e9e-8cf905ffdaf5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980317342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1980317342
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3220241346
Short name T54
Test name
Test status
Simulation time 69590078276 ps
CPU time 301.01 seconds
Started Jun 21 06:55:44 PM PDT 24
Finished Jun 21 07:00:47 PM PDT 24
Peak memory 202600 kb
Host smart-04553c53-1041-41d1-94d1-4d47b9e159f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220241346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3220241346
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4149679698
Short name T483
Test name
Test status
Simulation time 34284205497 ps
CPU time 39.45 seconds
Started Jun 21 06:55:43 PM PDT 24
Finished Jun 21 06:56:25 PM PDT 24
Peak memory 202084 kb
Host smart-4d1fa6e8-2275-40fa-8c52-3a343fc4d663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149679698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.4149679698
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.13373038
Short name T685
Test name
Test status
Simulation time 3464926808 ps
CPU time 4.54 seconds
Started Jun 21 06:55:49 PM PDT 24
Finished Jun 21 06:55:55 PM PDT 24
Peak memory 202060 kb
Host smart-165855b9-fe2f-4d61-b04c-5e7b9cf5d6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13373038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.13373038
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3342082799
Short name T190
Test name
Test status
Simulation time 6004524098 ps
CPU time 4.1 seconds
Started Jun 21 06:55:34 PM PDT 24
Finished Jun 21 06:55:40 PM PDT 24
Peak memory 202020 kb
Host smart-23e3cf6d-67c5-401c-b81b-0da758cb06ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342082799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3342082799
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3754742188
Short name T243
Test name
Test status
Simulation time 340688241112 ps
CPU time 702.38 seconds
Started Jun 21 06:55:49 PM PDT 24
Finished Jun 21 07:07:33 PM PDT 24
Peak memory 202300 kb
Host smart-bcf3f794-82f5-4714-913d-cb283afef528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754742188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3754742188
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.173214760
Short name T533
Test name
Test status
Simulation time 69033134816 ps
CPU time 110.03 seconds
Started Jun 21 06:55:44 PM PDT 24
Finished Jun 21 06:57:37 PM PDT 24
Peak memory 210884 kb
Host smart-03a77d27-727f-4206-8f95-088a6b206dd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173214760 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.173214760
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.209040906
Short name T467
Test name
Test status
Simulation time 312866871 ps
CPU time 0.91 seconds
Started Jun 21 06:55:57 PM PDT 24
Finished Jun 21 06:55:59 PM PDT 24
Peak memory 201912 kb
Host smart-713d5fcc-663a-4c32-966c-3d022479c6a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209040906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.209040906
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2386259114
Short name T45
Test name
Test status
Simulation time 165426939272 ps
CPU time 85.43 seconds
Started Jun 21 06:55:43 PM PDT 24
Finished Jun 21 06:57:11 PM PDT 24
Peak memory 202268 kb
Host smart-3e90f519-de97-4c31-9679-7845e4f2e6e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386259114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2386259114
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1100151721
Short name T193
Test name
Test status
Simulation time 491823713771 ps
CPU time 293.92 seconds
Started Jun 21 06:55:43 PM PDT 24
Finished Jun 21 07:00:39 PM PDT 24
Peak memory 202276 kb
Host smart-5130c1a8-0774-4005-80df-d61b4f7d01e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100151721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1100151721
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2950394605
Short name T464
Test name
Test status
Simulation time 489203817379 ps
CPU time 603.98 seconds
Started Jun 21 06:55:46 PM PDT 24
Finished Jun 21 07:05:51 PM PDT 24
Peak memory 202216 kb
Host smart-612fb71b-a0c7-4102-b134-d5404703b6c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950394605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2950394605
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2287931560
Short name T321
Test name
Test status
Simulation time 487753109513 ps
CPU time 1146.7 seconds
Started Jun 21 06:55:46 PM PDT 24
Finished Jun 21 07:14:55 PM PDT 24
Peak memory 202324 kb
Host smart-5fc7d8e9-2bd1-442d-a32a-ae59528a38de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287931560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2287931560
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3425836303
Short name T637
Test name
Test status
Simulation time 487965600507 ps
CPU time 514.9 seconds
Started Jun 21 06:55:46 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 202296 kb
Host smart-b3b59b5d-5d48-4e9e-a6ed-60ad5f715351
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425836303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3425836303
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1200976380
Short name T236
Test name
Test status
Simulation time 178579610458 ps
CPU time 140.1 seconds
Started Jun 21 06:55:44 PM PDT 24
Finished Jun 21 06:58:07 PM PDT 24
Peak memory 202300 kb
Host smart-1c48c0a8-6e8e-4d6e-abee-fb4f681b14c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200976380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1200976380
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1496327468
Short name T585
Test name
Test status
Simulation time 208275578060 ps
CPU time 84.27 seconds
Started Jun 21 06:55:45 PM PDT 24
Finished Jun 21 06:57:12 PM PDT 24
Peak memory 202296 kb
Host smart-62e0e3c6-7333-42b4-9aff-c98be5c04610
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496327468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1496327468
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.228303044
Short name T634
Test name
Test status
Simulation time 30096208094 ps
CPU time 71.45 seconds
Started Jun 21 06:55:57 PM PDT 24
Finished Jun 21 06:57:10 PM PDT 24
Peak memory 202072 kb
Host smart-cbd8f418-e5b2-47f1-af2d-ea5011e2548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228303044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.228303044
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2129435675
Short name T651
Test name
Test status
Simulation time 3920679296 ps
CPU time 5.18 seconds
Started Jun 21 06:55:54 PM PDT 24
Finished Jun 21 06:56:01 PM PDT 24
Peak memory 202056 kb
Host smart-62ad0b77-3870-4d5d-8ad7-9edbf15d9ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129435675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2129435675
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2562500205
Short name T728
Test name
Test status
Simulation time 6029082668 ps
CPU time 13.96 seconds
Started Jun 21 06:55:49 PM PDT 24
Finished Jun 21 06:56:04 PM PDT 24
Peak memory 202064 kb
Host smart-79f74bd2-4d74-47ce-a4cc-97c967d4da09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562500205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2562500205
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3692020531
Short name T423
Test name
Test status
Simulation time 354973888958 ps
CPU time 200.58 seconds
Started Jun 21 06:55:55 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 202284 kb
Host smart-249e1f05-957a-41f4-9db4-e937249d003d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692020531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3692020531
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3488018337
Short name T771
Test name
Test status
Simulation time 72979573450 ps
CPU time 83.18 seconds
Started Jun 21 06:55:53 PM PDT 24
Finished Jun 21 06:57:17 PM PDT 24
Peak memory 210568 kb
Host smart-80aa183a-4002-44d1-b286-d83eefd9e2cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488018337 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3488018337
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2596315731
Short name T592
Test name
Test status
Simulation time 525225686 ps
CPU time 0.95 seconds
Started Jun 21 06:51:16 PM PDT 24
Finished Jun 21 06:51:20 PM PDT 24
Peak memory 201936 kb
Host smart-c3fca881-6f34-414a-8b83-4be00806b033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596315731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2596315731
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.832458583
Short name T623
Test name
Test status
Simulation time 160150072126 ps
CPU time 26.44 seconds
Started Jun 21 06:51:06 PM PDT 24
Finished Jun 21 06:51:36 PM PDT 24
Peak memory 202220 kb
Host smart-b1a95dbf-be5d-464e-b96a-f8c93993ee2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832458583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.832458583
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3185356118
Short name T88
Test name
Test status
Simulation time 175226698504 ps
CPU time 403.84 seconds
Started Jun 21 06:51:04 PM PDT 24
Finished Jun 21 06:57:52 PM PDT 24
Peak memory 202244 kb
Host smart-cd1356dd-84a4-4576-b3bd-cfb9a57a021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185356118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3185356118
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.729598786
Short name T712
Test name
Test status
Simulation time 484220115738 ps
CPU time 583.04 seconds
Started Jun 21 06:51:06 PM PDT 24
Finished Jun 21 07:00:54 PM PDT 24
Peak memory 202220 kb
Host smart-b29262d0-412b-44df-b011-0cb7b177a278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729598786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.729598786
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1126201034
Short name T496
Test name
Test status
Simulation time 162748075456 ps
CPU time 67.26 seconds
Started Jun 21 06:51:09 PM PDT 24
Finished Jun 21 06:52:19 PM PDT 24
Peak memory 202276 kb
Host smart-7f67f5ac-4c50-40f0-8d56-30615da750de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126201034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1126201034
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.157729341
Short name T406
Test name
Test status
Simulation time 324793121880 ps
CPU time 206.97 seconds
Started Jun 21 06:51:09 PM PDT 24
Finished Jun 21 06:54:39 PM PDT 24
Peak memory 202204 kb
Host smart-2557a91a-5b3e-477a-83d6-3023b5001ba7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=157729341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.157729341
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3111818065
Short name T245
Test name
Test status
Simulation time 353707251861 ps
CPU time 750.13 seconds
Started Jun 21 06:51:03 PM PDT 24
Finished Jun 21 07:03:36 PM PDT 24
Peak memory 202320 kb
Host smart-43fcad4b-3641-41de-9e61-163e361fbd39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111818065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3111818065
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3838153218
Short name T505
Test name
Test status
Simulation time 415502341659 ps
CPU time 214.35 seconds
Started Jun 21 06:51:06 PM PDT 24
Finished Jun 21 06:54:44 PM PDT 24
Peak memory 202212 kb
Host smart-f16c2b9e-f6a0-4126-bc73-78bc5af05c6a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838153218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3838153218
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3303868823
Short name T619
Test name
Test status
Simulation time 93504142697 ps
CPU time 510.11 seconds
Started Jun 21 06:51:10 PM PDT 24
Finished Jun 21 06:59:43 PM PDT 24
Peak memory 202608 kb
Host smart-8f47d9a5-6b2a-4645-a788-5bc4ad65ed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303868823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3303868823
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1085602516
Short name T563
Test name
Test status
Simulation time 42833060871 ps
CPU time 95.47 seconds
Started Jun 21 06:51:07 PM PDT 24
Finished Jun 21 06:52:46 PM PDT 24
Peak memory 202032 kb
Host smart-038e1d9e-0030-497a-a459-98bb3f860052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085602516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1085602516
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3718704242
Short name T380
Test name
Test status
Simulation time 4124967046 ps
CPU time 3.08 seconds
Started Jun 21 06:51:05 PM PDT 24
Finished Jun 21 06:51:12 PM PDT 24
Peak memory 202036 kb
Host smart-d63cedd6-3a9c-438e-bd38-12207f453722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718704242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3718704242
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.624828362
Short name T469
Test name
Test status
Simulation time 6020742940 ps
CPU time 8.29 seconds
Started Jun 21 06:51:08 PM PDT 24
Finished Jun 21 06:51:20 PM PDT 24
Peak memory 202076 kb
Host smart-54f4d28e-3810-4cb4-b118-a28db4d33b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624828362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.624828362
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2725767298
Short name T721
Test name
Test status
Simulation time 499937237543 ps
CPU time 1061.83 seconds
Started Jun 21 06:51:15 PM PDT 24
Finished Jun 21 07:08:59 PM PDT 24
Peak memory 202316 kb
Host smart-8549cdb4-7968-4376-8ac3-9043301ad15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725767298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2725767298
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.158806923
Short name T610
Test name
Test status
Simulation time 14934032754 ps
CPU time 36.01 seconds
Started Jun 21 06:51:07 PM PDT 24
Finished Jun 21 06:51:47 PM PDT 24
Peak memory 210852 kb
Host smart-388eb8e5-f1f0-48da-aca5-f89fc874fb17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158806923 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.158806923
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1729455230
Short name T755
Test name
Test status
Simulation time 505672719 ps
CPU time 1.82 seconds
Started Jun 21 06:51:23 PM PDT 24
Finished Jun 21 06:51:30 PM PDT 24
Peak memory 201156 kb
Host smart-f5a0b636-63f9-41b7-9c54-c756cb91a892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729455230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1729455230
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3665904032
Short name T258
Test name
Test status
Simulation time 507105877025 ps
CPU time 828.11 seconds
Started Jun 21 06:51:16 PM PDT 24
Finished Jun 21 07:05:06 PM PDT 24
Peak memory 202236 kb
Host smart-68ab29c6-2aa5-4c08-a3cf-48e80899d66e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665904032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3665904032
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2875145121
Short name T281
Test name
Test status
Simulation time 162517567093 ps
CPU time 195.75 seconds
Started Jun 21 06:51:22 PM PDT 24
Finished Jun 21 06:54:40 PM PDT 24
Peak memory 202240 kb
Host smart-e1907cf2-c65a-476a-976e-65b3bd9eaa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875145121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2875145121
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2624311763
Short name T161
Test name
Test status
Simulation time 326359459096 ps
CPU time 207.25 seconds
Started Jun 21 06:51:17 PM PDT 24
Finished Jun 21 06:54:49 PM PDT 24
Peak memory 202232 kb
Host smart-8ae755af-853c-4cfe-92d7-896f4f634117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624311763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2624311763
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3726556823
Short name T428
Test name
Test status
Simulation time 492961773805 ps
CPU time 216.54 seconds
Started Jun 21 06:51:15 PM PDT 24
Finished Jun 21 06:54:54 PM PDT 24
Peak memory 202232 kb
Host smart-d39dc6ea-fa4d-4f0a-9094-8d5678b04c10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726556823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3726556823
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1001091337
Short name T665
Test name
Test status
Simulation time 168328818617 ps
CPU time 93.82 seconds
Started Jun 21 06:51:16 PM PDT 24
Finished Jun 21 06:52:51 PM PDT 24
Peak memory 202320 kb
Host smart-54329e9c-b798-491a-b120-f4d58f1f7165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001091337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1001091337
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3562843055
Short name T671
Test name
Test status
Simulation time 486870209289 ps
CPU time 66.81 seconds
Started Jun 21 06:51:14 PM PDT 24
Finished Jun 21 06:52:23 PM PDT 24
Peak memory 202208 kb
Host smart-dfa49493-8de6-4d46-9a27-2410dd9ec36f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562843055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3562843055
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3372053980
Short name T189
Test name
Test status
Simulation time 185700851967 ps
CPU time 421.3 seconds
Started Jun 21 06:51:17 PM PDT 24
Finished Jun 21 06:58:22 PM PDT 24
Peak memory 202228 kb
Host smart-44623ded-ae38-447f-80a7-56a591f6799f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372053980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3372053980
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.805742850
Short name T574
Test name
Test status
Simulation time 390747247658 ps
CPU time 217.86 seconds
Started Jun 21 06:51:14 PM PDT 24
Finished Jun 21 06:54:54 PM PDT 24
Peak memory 202216 kb
Host smart-90361d7e-bcd6-4dcf-a11f-b38a0cf9f059
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805742850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.805742850
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3094551184
Short name T204
Test name
Test status
Simulation time 92866292099 ps
CPU time 498.09 seconds
Started Jun 21 06:51:21 PM PDT 24
Finished Jun 21 06:59:41 PM PDT 24
Peak memory 202544 kb
Host smart-9a2f0afb-f3ab-4eb9-8c20-767ef35ad085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094551184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3094551184
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1192801527
Short name T507
Test name
Test status
Simulation time 42970017248 ps
CPU time 90.76 seconds
Started Jun 21 06:51:22 PM PDT 24
Finished Jun 21 06:52:55 PM PDT 24
Peak memory 202044 kb
Host smart-149ab372-8c40-4ffa-b7ef-6d20be40019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192801527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1192801527
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2078253573
Short name T145
Test name
Test status
Simulation time 3697794578 ps
CPU time 4.94 seconds
Started Jun 21 06:51:16 PM PDT 24
Finished Jun 21 06:51:22 PM PDT 24
Peak memory 202028 kb
Host smart-7de86130-d939-482d-8fcb-58fd8c020596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078253573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2078253573
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2075179681
Short name T389
Test name
Test status
Simulation time 5959285385 ps
CPU time 13.7 seconds
Started Jun 21 06:51:16 PM PDT 24
Finished Jun 21 06:51:32 PM PDT 24
Peak memory 202048 kb
Host smart-94ab39d2-46e6-4692-83b9-180a94d1be16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075179681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2075179681
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3702396071
Short name T401
Test name
Test status
Simulation time 243591814742 ps
CPU time 356.34 seconds
Started Jun 21 06:51:15 PM PDT 24
Finished Jun 21 06:57:14 PM PDT 24
Peak memory 202288 kb
Host smart-1f1ad2be-a047-40c1-9c50-b4fd95e5c26f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702396071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3702396071
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1849308918
Short name T511
Test name
Test status
Simulation time 464734854 ps
CPU time 1.62 seconds
Started Jun 21 06:51:17 PM PDT 24
Finished Jun 21 06:51:21 PM PDT 24
Peak memory 201940 kb
Host smart-b385b429-a1eb-42e1-b026-821ca0144e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849308918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1849308918
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1904155456
Short name T184
Test name
Test status
Simulation time 519610835385 ps
CPU time 286.3 seconds
Started Jun 21 06:51:17 PM PDT 24
Finished Jun 21 06:56:07 PM PDT 24
Peak memory 202292 kb
Host smart-bc19c837-66fc-4e53-b5fc-c90ffb165881
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904155456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1904155456
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3241408103
Short name T528
Test name
Test status
Simulation time 328364626826 ps
CPU time 380.88 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:57:51 PM PDT 24
Peak memory 202260 kb
Host smart-dba48087-fd4f-4813-8c40-c1d59ff7c0aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241408103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3241408103
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2083730311
Short name T165
Test name
Test status
Simulation time 503854360060 ps
CPU time 296.33 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:56:26 PM PDT 24
Peak memory 202304 kb
Host smart-6873486c-6637-4ae1-9bde-a8b967d5d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083730311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2083730311
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.650061362
Short name T433
Test name
Test status
Simulation time 323641011571 ps
CPU time 198 seconds
Started Jun 21 06:51:15 PM PDT 24
Finished Jun 21 06:54:35 PM PDT 24
Peak memory 202216 kb
Host smart-d4fd3d44-e803-46d8-8ad5-749f7ba2b992
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=650061362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.650061362
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2594543
Short name T702
Test name
Test status
Simulation time 163436123007 ps
CPU time 99.64 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:53:10 PM PDT 24
Peak memory 202232 kb
Host smart-779ff8f5-4865-4294-b1a5-9b953a494d37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wak
eup.2594543
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.859323886
Short name T527
Test name
Test status
Simulation time 400974660910 ps
CPU time 445.49 seconds
Started Jun 21 06:51:17 PM PDT 24
Finished Jun 21 06:58:45 PM PDT 24
Peak memory 202292 kb
Host smart-bc36d9e4-31a3-4897-86bf-11e5dba8003c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859323886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.859323886
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1037055207
Short name T335
Test name
Test status
Simulation time 97223519549 ps
CPU time 503.14 seconds
Started Jun 21 06:51:15 PM PDT 24
Finished Jun 21 06:59:40 PM PDT 24
Peak memory 202636 kb
Host smart-2c3446ab-39f4-421f-ad44-d598888efe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037055207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1037055207
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.725403533
Short name T491
Test name
Test status
Simulation time 37511027585 ps
CPU time 83.5 seconds
Started Jun 21 06:51:18 PM PDT 24
Finished Jun 21 06:52:46 PM PDT 24
Peak memory 202000 kb
Host smart-c221ea02-b947-47e8-8e16-ba623827cece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725403533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.725403533
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.997441767
Short name T517
Test name
Test status
Simulation time 5278037801 ps
CPU time 2.49 seconds
Started Jun 21 06:51:25 PM PDT 24
Finished Jun 21 06:51:35 PM PDT 24
Peak memory 202064 kb
Host smart-b934044f-3328-4962-bd2e-9ecb900e1149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997441767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.997441767
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3936538258
Short name T551
Test name
Test status
Simulation time 6191942517 ps
CPU time 4.2 seconds
Started Jun 21 06:51:22 PM PDT 24
Finished Jun 21 06:51:28 PM PDT 24
Peak memory 202056 kb
Host smart-456c2c5d-5e8c-4110-a9f8-e8e3f1a89c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936538258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3936538258
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3801161346
Short name T202
Test name
Test status
Simulation time 262436195520 ps
CPU time 904.53 seconds
Started Jun 21 06:51:17 PM PDT 24
Finished Jun 21 07:06:25 PM PDT 24
Peak memory 218888 kb
Host smart-dc75bce6-92d9-43dc-9baf-1528d03b0f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801161346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3801161346
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.4042932190
Short name T328
Test name
Test status
Simulation time 537833858164 ps
CPU time 149.36 seconds
Started Jun 21 06:51:18 PM PDT 24
Finished Jun 21 06:53:52 PM PDT 24
Peak memory 210752 kb
Host smart-03143989-8650-40b1-89e6-c6750254d9e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042932190 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.4042932190
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2103903395
Short name T87
Test name
Test status
Simulation time 303746730 ps
CPU time 0.83 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:51:31 PM PDT 24
Peak memory 201932 kb
Host smart-b60e3229-8a18-4360-9760-bd53872f7efa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103903395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2103903395
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1723794306
Short name T272
Test name
Test status
Simulation time 164490590626 ps
CPU time 242.7 seconds
Started Jun 21 06:51:18 PM PDT 24
Finished Jun 21 06:55:24 PM PDT 24
Peak memory 202284 kb
Host smart-87f05830-656d-4560-b532-94ed4cd45290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723794306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1723794306
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.475484427
Short name T659
Test name
Test status
Simulation time 331297455105 ps
CPU time 748.96 seconds
Started Jun 21 06:51:23 PM PDT 24
Finished Jun 21 07:03:57 PM PDT 24
Peak memory 201516 kb
Host smart-724d28e3-88e6-47a7-bba7-5f621856ac4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=475484427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.475484427
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2367150818
Short name T640
Test name
Test status
Simulation time 330384407317 ps
CPU time 466.57 seconds
Started Jun 21 06:51:16 PM PDT 24
Finished Jun 21 06:59:04 PM PDT 24
Peak memory 202348 kb
Host smart-a4c6f481-1c4e-49e4-82dd-5c5d3d50b2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367150818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2367150818
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2412296197
Short name T267
Test name
Test status
Simulation time 335455206183 ps
CPU time 105.01 seconds
Started Jun 21 06:51:16 PM PDT 24
Finished Jun 21 06:53:04 PM PDT 24
Peak memory 202172 kb
Host smart-5c44327f-210a-4b1b-8746-afe36789c697
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412296197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2412296197
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.488768211
Short name T238
Test name
Test status
Simulation time 210231190483 ps
CPU time 381.41 seconds
Started Jun 21 06:51:15 PM PDT 24
Finished Jun 21 06:57:38 PM PDT 24
Peak memory 202252 kb
Host smart-01f7b5b6-4bfb-4072-9a9b-9d431067c4c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488768211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.488768211
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.306413225
Short name T188
Test name
Test status
Simulation time 203627311479 ps
CPU time 226.01 seconds
Started Jun 21 06:51:15 PM PDT 24
Finished Jun 21 06:55:03 PM PDT 24
Peak memory 202204 kb
Host smart-1bffe098-9033-4c5f-9413-d183c3f55ed8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306413225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.306413225
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1604838701
Short name T689
Test name
Test status
Simulation time 85262087248 ps
CPU time 284.42 seconds
Started Jun 21 06:51:28 PM PDT 24
Finished Jun 21 06:56:19 PM PDT 24
Peak memory 202552 kb
Host smart-24222c3b-4706-45f8-9cc5-2e6e139c28c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604838701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1604838701
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2921583317
Short name T452
Test name
Test status
Simulation time 25079053660 ps
CPU time 12.16 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:51:41 PM PDT 24
Peak memory 202084 kb
Host smart-9cb38a0f-2def-4919-95d2-e8bfe2d38b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921583317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2921583317
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.688588740
Short name T363
Test name
Test status
Simulation time 4317134851 ps
CPU time 1.7 seconds
Started Jun 21 06:51:25 PM PDT 24
Finished Jun 21 06:51:33 PM PDT 24
Peak memory 202128 kb
Host smart-5fee2f2f-742b-4f92-9216-03c60b10bc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688588740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.688588740
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.202265390
Short name T683
Test name
Test status
Simulation time 5911920337 ps
CPU time 10.77 seconds
Started Jun 21 06:51:22 PM PDT 24
Finished Jun 21 06:51:35 PM PDT 24
Peak memory 202068 kb
Host smart-45d3356c-801d-495c-970f-cc1aff4be82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202265390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.202265390
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.4150725654
Short name T679
Test name
Test status
Simulation time 194925651770 ps
CPU time 11.57 seconds
Started Jun 21 06:51:23 PM PDT 24
Finished Jun 21 06:51:38 PM PDT 24
Peak memory 202176 kb
Host smart-5461d031-57f2-481e-bed7-394c9561aef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150725654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
4150725654
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.228319008
Short name T213
Test name
Test status
Simulation time 135983520992 ps
CPU time 182.18 seconds
Started Jun 21 06:51:25 PM PDT 24
Finished Jun 21 06:54:34 PM PDT 24
Peak memory 219088 kb
Host smart-19b9a061-95db-4f70-bead-74c3f6717153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228319008 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.228319008
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3910306986
Short name T480
Test name
Test status
Simulation time 299239658 ps
CPU time 0.8 seconds
Started Jun 21 06:51:27 PM PDT 24
Finished Jun 21 06:51:36 PM PDT 24
Peak memory 201948 kb
Host smart-14a2fa15-ecb8-4e1a-b463-1e5543e5226e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910306986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3910306986
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3831376521
Short name T322
Test name
Test status
Simulation time 495808625773 ps
CPU time 64.02 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:52:33 PM PDT 24
Peak memory 202236 kb
Host smart-8c2d1c8d-6d0f-4775-84f0-6ceb409cfbdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831376521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3831376521
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3823104204
Short name T330
Test name
Test status
Simulation time 379259824351 ps
CPU time 918.07 seconds
Started Jun 21 06:51:28 PM PDT 24
Finished Jun 21 07:06:53 PM PDT 24
Peak memory 202300 kb
Host smart-225d3ab5-e986-45ba-a180-3ec20364bc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823104204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3823104204
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1612467808
Short name T276
Test name
Test status
Simulation time 164390241502 ps
CPU time 95.03 seconds
Started Jun 21 06:51:25 PM PDT 24
Finished Jun 21 06:53:07 PM PDT 24
Peak memory 202244 kb
Host smart-fdbe992e-79d9-424f-945b-9b62c80c92b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612467808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1612467808
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1477786778
Short name T352
Test name
Test status
Simulation time 164605163034 ps
CPU time 404.75 seconds
Started Jun 21 06:51:22 PM PDT 24
Finished Jun 21 06:58:10 PM PDT 24
Peak memory 202216 kb
Host smart-1c92bffc-8535-46be-a975-a66d9e6c18cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477786778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1477786778
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.801763629
Short name T152
Test name
Test status
Simulation time 166660482315 ps
CPU time 104.58 seconds
Started Jun 21 06:51:26 PM PDT 24
Finished Jun 21 06:53:17 PM PDT 24
Peak memory 202316 kb
Host smart-1376f6a5-dac2-47f9-a6d9-29fcc9b74a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801763629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.801763629
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3003677316
Short name T416
Test name
Test status
Simulation time 160536581374 ps
CPU time 375.59 seconds
Started Jun 21 06:51:30 PM PDT 24
Finished Jun 21 06:57:52 PM PDT 24
Peak memory 202204 kb
Host smart-6a5c7218-2b2a-48e9-a51c-f4a944dcf614
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003677316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3003677316
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4290982871
Short name T432
Test name
Test status
Simulation time 613343125386 ps
CPU time 1479.77 seconds
Started Jun 21 06:51:28 PM PDT 24
Finished Jun 21 07:16:15 PM PDT 24
Peak memory 202276 kb
Host smart-a641d14b-9564-4c81-b65b-b3edd726fbde
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290982871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.4290982871
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.737667133
Short name T205
Test name
Test status
Simulation time 109936424656 ps
CPU time 617.9 seconds
Started Jun 21 06:51:27 PM PDT 24
Finished Jun 21 07:01:52 PM PDT 24
Peak memory 202608 kb
Host smart-ea32666a-f076-48a8-b471-590fd747b66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737667133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.737667133
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3545269165
Short name T670
Test name
Test status
Simulation time 37462435913 ps
CPU time 77.14 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:52:47 PM PDT 24
Peak memory 202008 kb
Host smart-e094145a-1503-452e-aa26-9da19819c25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545269165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3545269165
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.818121830
Short name T445
Test name
Test status
Simulation time 4269136502 ps
CPU time 9.51 seconds
Started Jun 21 06:51:29 PM PDT 24
Finished Jun 21 06:51:45 PM PDT 24
Peak memory 202076 kb
Host smart-2d8a315d-c81b-4e7e-a54d-c0d4da69835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818121830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.818121830
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.673993363
Short name T367
Test name
Test status
Simulation time 5562089411 ps
CPU time 3.69 seconds
Started Jun 21 06:51:24 PM PDT 24
Finished Jun 21 06:51:33 PM PDT 24
Peak memory 202076 kb
Host smart-d6ba2e1a-d9f6-44c4-840d-63e39426e423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673993363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.673993363
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2862434931
Short name T18
Test name
Test status
Simulation time 150706659762 ps
CPU time 229.81 seconds
Started Jun 21 06:51:27 PM PDT 24
Finished Jun 21 06:55:23 PM PDT 24
Peak memory 210548 kb
Host smart-8cc08190-4201-4044-8596-62cc85fcf067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862434931 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2862434931
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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