Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7163	1			T3	20		T62	40		T63	40
testmodes[AdcCtrlTestmodeNormal]	5838	1			T1	2		T3	1		T7	3
testmodes[AdcCtrlTestmodeLowpower]	5976	1			T1	1		T2	1		T3	16
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3744	1			T3	19		T62	39		T63	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1899	1			T63	12		T72	7		T73	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1402	1			T3	1		T63	17		T67	8
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1900	1			T63	17		T72	6		T73	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2123	1			T1	1		T7	2		T11	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1471	1			T3	1		T63	13		T67	8
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1403	1			T3	1		T63	12		T67	6
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1482	1			T1	1		T58	1		T63	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2855	1			T3	14		T6	2		T8	1