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Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26826 1 T1 22 T2 30 T3 45



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 23297 1 T1 2 T3 40 T6 6
auto[ADC_CTRL_FILTER_COND_OUT] 3529 1 T1 20 T2 30 T3 5



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20904 1 T1 2 T3 41 T6 11
auto[1] 5922 1 T1 20 T2 30 T3 4



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22910 1 T1 14 T2 16 T3 43
auto[1] 3916 1 T1 8 T2 14 T3 2



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 1 1 T148 1 - - - -
values[0] 77 1 T16 5 T217 1 T218 16
values[1] 766 1 T1 2 T6 8 T8 14
values[2] 817 1 T1 18 T2 30 T146 12
values[3] 627 1 T59 29 T61 30 T33 1
values[4] 598 1 T1 2 T39 7 T54 2
values[5] 546 1 T3 4 T72 1 T151 1
values[6] 526 1 T147 12 T149 20 T166 10
values[7] 733 1 T3 5 T6 3 T58 40
values[8] 2823 1 T7 34 T8 11 T10 24
values[9] 1256 1 T6 3 T9 1 T12 2
minimum 18056 1 T3 36 T62 40 T63 119



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 1157 1 T1 20 T2 30 T6 8
values[1] 652 1 T45 19 T219 1 T152 1
values[2] 695 1 T72 1 T59 29 T61 30
values[3] 476 1 T151 1 T39 7 T147 6
values[4] 542 1 T1 2 T3 4 T72 1
values[5] 676 1 T58 22 T220 3 T36 9
values[6] 2818 1 T6 3 T7 34 T10 24
values[7] 626 1 T3 5 T8 11 T35 11
values[8] 915 1 T6 3 T9 1 T12 1
values[9] 213 1 T12 1 T148 1 T152 1
minimum 18056 1 T3 36 T62 40 T63 119



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22893 1 T1 11 T2 15 T3 39
auto[1] 3933 1 T1 11 T2 15 T3 6



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 296 1 T8 8 T40 12 T157 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 402 1 T1 13 T2 16 T6 8
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T219 1 T221 1 T222 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T45 12 T152 1 T223 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T72 1 T61 15 T54 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T59 16 T33 1 T157 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 119 1 T151 1 T147 6 T54 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 149 1 T39 1 T51 15 T197 14
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T1 1 T3 3 T166 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T72 1 T38 1 T154 11
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 183 1 T58 13 T220 1 T157 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 147 1 T36 9 T149 10 T166 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1445 1 T6 3 T7 3 T10 24
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T58 5 T122 1 T151 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T8 6 T35 11 T161 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T3 5 T36 10 T42 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 285 1 T6 3 T9 1 T12 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 260 1 T146 1 T40 18 T149 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 24 1 T152 1 T160 1 T224 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 78 1 T12 1 T148 1 T47 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17910 1 T3 35 T62 40 T63 119
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 189 1 T8 6 T157 1 T196 8
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 270 1 T1 7 T2 14 T146 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T222 1 T204 6 T198 5
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T45 7 T223 11 T155 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T61 15 T177 12 T225 14
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T59 13 T177 12 T159 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 74 1 T226 2 T161 3 T227 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 134 1 T39 6 T51 15 T197 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 97 1 T1 1 T3 1 T166 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T228 9 T229 5 T230 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 175 1 T58 9 T220 2 T157 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T149 10 T166 10 T196 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1056 1 T7 31 T146 2 T156 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 115 1 T58 13 T122 9 T61 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T8 5 T161 10 T153 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 103 1 T42 2 T231 6 T232 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T59 1 T149 8 T48 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T146 7 T149 13 T233 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 24 1 T224 10 T200 7 T110 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 87 1 T234 2 T235 1 T236 14
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 146 1 T3 1 T64 1 T33 1



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [maximum] * -- -- 2


Uncovered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T148 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 32 1 T16 4 T218 16 T237 12
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 19 1 T217 1 T238 18 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T8 8 T40 12 T148 2
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 304 1 T1 1 T6 8 T120 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 216 1 T72 1 T157 1 T221 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 224 1 T1 12 T2 16 T146 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T61 15 T179 1 T239 12
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 204 1 T59 16 T33 1 T157 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T1 1 T54 2 T177 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T39 1 T197 14 T177 17
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 153 1 T3 3 T151 1 T147 6
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T72 1 T38 1 T51 15
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T147 12 T166 1 T158 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T149 10 T196 1 T187 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 246 1 T6 3 T58 13 T220 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 181 1 T3 5 T58 5 T122 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1439 1 T7 3 T8 6 T10 24
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T36 10 T219 1 T14 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 332 1 T6 3 T9 1 T12 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 378 1 T12 1 T146 1 T40 18
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17910 1 T3 35 T62 40 T63 119
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 12 1 T16 1 T237 11 - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 14 1 T238 14 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 92 1 T8 6 T196 8 T232 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T1 1 T240 2 T241 4
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T157 1 T222 1 T204 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 185 1 T1 6 T2 14 T146 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 130 1 T61 15 T239 11 T242 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T59 13 T223 11 T159 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 122 1 T1 1 T177 12 T226 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T39 6 T197 11 T177 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 78 1 T3 1 T204 4 T243 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T51 15 T166 10 T244 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 120 1 T166 9 T245 2 T46 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T149 10 T196 7 T246 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T58 9 T220 2 T157 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 119 1 T58 13 T122 9 T61 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1065 1 T7 31 T8 5 T146 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 109 1 T48 5 T247 10 T232 8
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T59 1 T149 8 T153 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 336 1 T146 7 T42 2 T149 13
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 146 1 T3 1 T64 1 T33 1



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 7 41 85.42 7


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 247 1 T8 7 T40 1 T157 2
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 342 1 T1 9 T2 15 T6 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T219 1 T221 1 T222 2
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 228 1 T45 15 T152 1 T223 12
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 195 1 T72 1 T61 16 T54 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T59 14 T33 1 T157 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 107 1 T151 1 T147 1 T54 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T39 7 T51 16 T197 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 130 1 T1 2 T3 2 T166 10
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 152 1 T72 1 T38 1 T154 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 206 1 T58 10 T220 3 T157 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 213 1 T36 1 T149 11 T166 11
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1395 1 T6 1 T7 34 T10 2
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 150 1 T58 14 T122 10 T151 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T8 6 T35 1 T161 11
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 133 1 T3 1 T36 1 T42 3
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T6 1 T9 1 T12 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 267 1 T146 8 T40 1 T149 14
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 37 1 T152 1 T160 1 T224 11
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 104 1 T12 1 T148 1 T47 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 18056 1 T3 36 T62 40 T63 119
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 238 1 T8 7 T40 11 T196 2
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 330 1 T1 11 T2 15 T6 7
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 105 1 T204 12 T162 4 T198 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 150 1 T45 4 T223 10 T248 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T61 14 T177 11 T225 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T59 15 T177 16 T159 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 86 1 T147 5 T226 3 T249 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 119 1 T51 14 T197 13 T154 5
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T3 2 T225 7 T243 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 108 1 T154 10 T225 10 T228 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T58 12 T147 11 T250 5
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 105 1 T36 8 T149 9 T197 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1106 1 T6 2 T10 22 T60 24
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T58 4 T61 8 T150 18
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T8 5 T35 10 T223 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T3 4 T36 9 T251 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 226 1 T6 2 T59 7 T37 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T40 17 T233 11 T154 8
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 11 1 T200 8 T110 1 T252 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 61 1 T234 9 T167 10 T253 22



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T148 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 17 1 T16 4 T218 1 T237 12
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 16 1 T217 1 T238 15 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T8 7 T40 1 T148 2
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 258 1 T1 2 T6 1 T120 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 241 1 T72 1 T157 2 T221 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 233 1 T1 7 T2 15 T146 12
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T61 16 T179 1 T239 12
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 197 1 T59 14 T33 1 T157 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T1 2 T54 2 T177 13
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T39 7 T197 12 T177 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 107 1 T3 2 T151 1 T147 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T72 1 T38 1 T51 16
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T147 1 T166 10 T158 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T149 11 T196 8 T187 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 236 1 T6 1 T58 10 T220 3
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T3 1 T58 14 T122 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1400 1 T7 34 T8 6 T10 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T36 1 T219 1 T14 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 293 1 T6 1 T9 1 T12 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 408 1 T12 1 T146 8 T40 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 18056 1 T3 36 T62 40 T63 119
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 27 1 T16 1 T218 15 T237 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 17 1 T238 17 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T8 7 T40 11 T196 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 244 1 T6 7 T36 16 T240 13
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T204 12 T254 19 T162 4
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T1 11 T2 15 T147 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 106 1 T61 14 T239 11 T255 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T59 15 T223 10 T159 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 113 1 T177 11 T226 3 T225 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T197 13 T177 16 T154 5
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 124 1 T3 2 T147 5 T204 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 121 1 T51 14 T244 2 T154 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 131 1 T147 11 T46 2 T225 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 88 1 T149 9 T246 10 T163 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T6 2 T58 12 T44 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 137 1 T3 4 T58 4 T61 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1104 1 T8 5 T10 22 T60 24
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T36 9 T48 5 T251 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 249 1 T6 2 T59 7 T37 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 306 1 T40 17 T233 11 T154 8



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 22893 1 T1 11 T2 15 T3 39
auto[1] auto[0] 3933 1 T1 11 T2 15 T3 6


Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26826 1 T1 22 T2 30 T3 45



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 23443 1 T1 22 T3 45 T6 8
auto[ADC_CTRL_FILTER_COND_OUT] 3383 1 T2 30 T6 6 T8 14



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21285 1 T1 2 T2 30 T3 45
auto[1] 5541 1 T1 20 T6 8 T7 34



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22910 1 T1 14 T2 16 T3 43
auto[1] 3916 1 T1 8 T2 14 T3 2



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 19 1 T40 18 T54 1 - -
values[0] 85 1 T12 1 T36 17 T40 12
values[1] 607 1 T1 2 T12 1 T72 2
values[2] 2741 1 T1 18 T6 3 T7 34
values[3] 846 1 T1 2 T59 29 T35 11
values[4] 745 1 T146 20 T59 8 T151 1
values[5] 790 1 T3 9 T36 9 T197 25
values[6] 684 1 T2 30 T58 22 T61 43
values[7] 789 1 T8 11 T219 1 T196 8
values[8] 454 1 T58 18 T220 3 T151 1
values[9] 1010 1 T6 11 T9 1 T146 3
minimum 18056 1 T3 36 T62 40 T63 119



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 828 1 T1 2 T6 3 T12 2
values[1] 2800 1 T1 18 T7 34 T8 14
values[2] 855 1 T1 2 T59 29 T35 11
values[3] 644 1 T146 20 T59 8 T151 1
values[4] 922 1 T3 9 T61 30 T36 9
values[5] 608 1 T2 30 T58 22 T61 13
values[6] 720 1 T8 11 T58 18 T201 1
values[7] 617 1 T220 3 T151 1 T36 10
values[8] 599 1 T6 11 T9 1 T146 3
values[9] 176 1 T149 20 T54 1 T226 2
minimum 18057 1 T3 36 T62 40 T63 119



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22893 1 T1 11 T2 15 T3 39
auto[1] 3933 1 T1 11 T2 15 T3 6



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 228 1 T1 1 T12 1 T72 2
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 233 1 T6 3 T12 1 T122 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1444 1 T1 12 T7 3 T10 24
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 199 1 T8 8 T120 1 T42 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 231 1 T1 1 T59 16 T35 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 240 1 T157 1 T201 1 T147 12
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T146 1 T59 8 T33 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T146 1 T151 1 T38 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 280 1 T3 8 T36 9 T240 14
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T61 15 T51 15 T197 14
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T58 13 T61 9 T196 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T2 16 T219 1 T161 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 212 1 T8 6 T201 1 T241 14
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 229 1 T58 5 T196 3 T32 15
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T151 1 T36 10 T37 3
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 201 1 T220 1 T39 1 T166 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T6 8 T9 1 T59 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 213 1 T6 3 T146 1 T40 18
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 49 1 T149 10 T226 1 T234 10
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 62 1 T54 1 T222 1 T249 14
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17911 1 T3 35 T62 40 T63 119
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T1 1 T14 1 T155 4
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T122 9 T157 12 T149 8
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1018 1 T1 6 T7 31 T156 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T8 6 T42 2 T250 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 199 1 T1 1 T59 13 T44 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 185 1 T161 3 T153 4 T225 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 109 1 T146 11 T153 7 T159 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T146 7 T157 1 T239 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 221 1 T3 1 T240 2 T177 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 209 1 T61 15 T51 15 T197 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 186 1 T58 9 T61 4 T196 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T2 14 T161 10 T46 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T8 5 T241 4 T48 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T58 13 T196 8 T16 3
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 125 1 T197 9 T244 4 T159 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 125 1 T220 2 T39 6 T166 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 103 1 T59 1 T245 2 T246 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 147 1 T146 2 T166 10 T256 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 41 1 T149 10 T226 1 T234 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 24 1 T222 11 T227 8 T257 5
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 146 1 T3 1 T64 1 T33 1



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [maximum] * -- -- 2


Uncovered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 19 1 T40 18 T54 1 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 29 1 T12 1 T40 12 T235 16
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 22 1 T36 17 T219 1 T258 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 188 1 T1 1 T72 2 T150 19
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T12 1 T157 1 T149 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1405 1 T1 12 T7 3 T10 24
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 193 1 T6 3 T8 8 T120 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 270 1 T1 1 T59 16 T35 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 258 1 T42 1 T201 1 T147 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 125 1 T146 1 T59 8 T33 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 244 1 T146 1 T151 1 T38 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 292 1 T3 8 T36 9 T177 12
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T197 14 T70 1 T221 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T58 13 T61 9 T240 14
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T2 16 T61 15 T51 15
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 234 1 T8 6 T196 1 T241 14
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 264 1 T219 1 T32 15 T161 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T151 1 T36 10 T37 3
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 109 1 T58 5 T220 1 T39 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 255 1 T6 8 T9 1 T59 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 345 1 T6 3 T146 1 T147 9
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17910 1 T3 35 T62 40 T63 119
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 15 1 T235 15 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 19 1 T258 4 T259 13 T111 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T1 1 T155 4 T204 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T157 12 T149 8 T222 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1014 1 T1 6 T7 31 T156 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T8 6 T122 9 T18 4
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T1 1 T59 13 T44 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T42 2 T161 3 T153 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T146 11 T153 7 T159 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 235 1 T146 7 T157 1 T225 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T3 1 T177 12 T260 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T197 11 T250 10 T159 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T58 9 T61 4 T240 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T2 14 T61 15 T51 15
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T8 5 T196 7 T241 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 134 1 T161 10 T16 3 T261 13
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 98 1 T262 8 T239 11 T263 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T58 13 T220 2 T39 6
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 202 1 T59 1 T149 10 T197 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 208 1 T146 2 T166 19 T197 13
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 146 1 T3 1 T64 1 T33 1

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