Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23599

1

T1

22

T3

40

T6

8

auto[ADC_CTRL_FILTER_COND_OUT]

3227

1

T2

30

T3

5

T6

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20702

1

T1

22

T3

45

T6

6

auto[1]

6124

1

T2

30

T6

8

T7

34

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	427	1			T63	2		T67	2		T64	8
values[0]	39	1			T288	12		T303	1		T172	1
values[1]	583	1			T3	4		T59	2		T149	20
values[2]	2797	1			T7	34		T10	24		T11	2
values[3]	614	1			T146	3		T147	9		T240	16
values[4]	600	1			T2	30		T122	10		T151	1
values[5]	650	1			T3	5		T6	8		T9	1
values[6]	666	1			T6	3		T146	12		T120	1
values[7]	726	1			T72	1		T220	3		T35	11
values[8]	779	1			T1	4		T12	2		T59	29
values[9]	1290	1			T1	18		T6	3		T8	25
minimum	17655	1			T3	36		T62	40		T63	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	850	1			T3	4		T59	2		T36	26
values[1]	2621	1			T7	34		T10	24		T11	2
values[2]	665	1			T146	3		T240	16		T197	32
values[3]	641	1			T122	10		T151	1		T51	30
values[4]	595	1			T2	30		T3	5		T6	8
values[5]	699	1			T6	3		T146	12		T120	1
values[6]	685	1			T1	2		T72	1		T35	11
values[7]	1007	1			T1	2		T6	3		T12	2
values[8]	731	1			T1	18		T8	11		T72	1
values[9]	263	1			T8	14		T148	1		T197	20
minimum	18069	1			T3	36		T62	40		T63	119

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	3		T36	17		T149	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T59	1		T36	9		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T7	3		T10	24		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T147	9		T148	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T240	14		T197	19		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T146	1		T177	1		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T151	1		T51	15		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T122	1		T196	1		T14	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	8		T9	1		T59	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	16		T3	5		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	1		T120	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	3		T37	3		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T1	1		T35	11		T36	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T72	1		T54	1		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T1	1		T12	2		T58	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T6	3		T40	12		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	12		T8	6		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T72	1		T44	6		T150	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T159	19		T262	12		T266	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T8	8		T148	1		T197	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T163	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T149	10		T223	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T59	1		T166	10		T254	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T7	31		T146	7		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T250	10		T224	5		T262	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T240	2		T197	13		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T146	2		T177	1		T226	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T51	15		T243	9		T248	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T122	9		T196	7		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T177	12		T153	4		T155	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	14		T39	6		T161	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	11		T220	2		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T45	7		T166	9		T250	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T157	1		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T161	10		T239	11		T282	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T58	22		T59	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T149	21		T233	10		T243	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	6		T8	5		T222	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	2		T295	11		T325	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T159	11		T262	11		T266	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T8	6		T197	9		T305	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T163	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	402	1			T63	2		T67	2		T64	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T285	10		T171	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T172	1		T326	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T288	12		T303	1		T185	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	3		T149	10		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T59	1		T219	1		T32	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T7	3		T10	24		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T36	9		T148	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T240	14		T197	19		T177	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T146	1		T147	9		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T151	1		T51	15		T265	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	16		T122	1		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	8		T9	1		T59	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	5		T39	1		T147	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T146	1		T120	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	3		T37	3		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T220	1		T35	11		T36	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T72	1		T157	1		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T1	2		T12	2		T59	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	12		T147	12		T149	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T1	12		T8	6		T58	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T6	3		T8	8		T72	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17509	1			T3	35		T62	40		T63	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T327	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T285	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T328	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	1		T149	10		T223	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T59	1		T254	21		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1046	1			T7	31		T146	7		T156	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T166	10		T48	5		T224	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T240	2		T197	13		T177	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T146	2		T153	16		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T51	15		T198	5		T248	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	14		T122	9		T196	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T153	7		T155	4		T159	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	6		T161	3		T222	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T146	11		T42	2		T197	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T166	9		T250	2		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T220	2		T157	1		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T45	7		T161	10		T239	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	2		T59	13		T61	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T149	21		T243	15		T163	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T1	6		T8	5		T58	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T8	6		T44	2		T197	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	2		T36	1		T149	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T59	2		T36	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T7	34		T10	2		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T147	1		T148	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T240	3		T197	14		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T146	3		T177	2		T226	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T151	1		T51	16		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T122	10		T196	8		T14	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	1		T9	1		T59	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	15		T3	1		T39	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T146	12		T120	1		T220	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T37	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	2		T35	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T72	1		T54	1		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T1	2		T12	2		T58	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	1		T40	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	7		T8	6		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T72	1		T44	6		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T159	12		T262	12		T266	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T8	7		T148	1		T197	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T163	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	2		T36	16		T149	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T36	8		T32	15		T254	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T10	22		T60	24		T55	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T147	8		T250	5		T154	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T240	13		T197	18		T265	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T227	7		T198	8		T251	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T51	14		T243	9		T249	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T264	4		T266	6		T188	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	7		T59	7		T32	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T2	15		T3	4		T147	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T197	13		T244	2		T264	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	2		T37	2		T45	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T35	10		T36	9		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T47	1		T239	11		T329	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T58	16		T59	15		T61	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	2		T40	11		T147	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	11		T8	5		T40	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T44	2		T150	18		T325	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T159	18		T262	11		T266	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T8	7		T197	10		T305	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T163	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	406	1			T63	2		T67	2		T64	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T285	11		T171	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T172	1		T326	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T288	1		T303	1		T185	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	2		T149	11		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T59	2		T219	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T7	34		T10	2		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	1		T148	1		T166	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T240	3		T197	14		T177	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T146	3		T147	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T151	1		T51	16		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	15		T122	10		T196	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T9	1		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	1		T39	7		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T146	12		T120	1		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T37	1		T166	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T220	3		T35	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T72	1		T157	1		T45	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	4		T12	2		T59	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	1		T147	1		T149	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T1	7		T8	6		T58	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T6	1		T8	7		T72	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17655	1			T3	36		T62	40		T63	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T285	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T288	11		T185	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T3	2		T149	9		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T32	15		T254	19		T264	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T10	22		T60	24		T36	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T36	8		T154	5		T48	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T240	13		T197	18		T177	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T147	8		T250	5		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T51	14		T265	7		T249	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T2	15		T270	10		T288	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	7		T59	7		T32	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	4		T147	5		T264	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T197	13		T177	16		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	2		T37	2		T250	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T35	10		T36	9		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	4		T47	1		T239	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T59	15		T61	22		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	11		T147	11		T243	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T1	11		T8	5		T58	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T6	2		T8	7		T44	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6