Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23792

1

T1

2

T2

30

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3034

1

T1

20

T9

1

T146

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21266

1

T1

20

T2

30

T3

40

auto[1]

5560

1

T1

2

T3

5

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	255	1			T146	3		T58	22		T226	6
values[0]	40	1			T162	12		T188	1		T308	26
values[1]	764	1			T151	1		T40	30		T148	1
values[2]	732	1			T39	7		T148	1		T149	14
values[3]	604	1			T12	1		T59	29		T201	1
values[4]	531	1			T1	2		T146	8		T120	1
values[5]	2809	1			T7	34		T10	24		T11	2
values[6]	637	1			T58	18		T240	16		T54	1
values[7]	791	1			T1	18		T3	9		T6	6
values[8]	707	1			T1	2		T8	25		T9	1
values[9]	900	1			T2	30		T6	8		T146	12
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	825	1			T151	1		T40	30		T148	2
values[1]	631	1			T39	7		T149	14		T54	1
values[2]	572	1			T1	2		T12	1		T59	29
values[3]	2707	1			T7	34		T10	24		T11	2
values[4]	677	1			T72	1		T59	2		T42	3
values[5]	721	1			T3	5		T6	3		T58	18
values[6]	705	1			T1	20		T3	4		T6	3
values[7]	658	1			T2	30		T8	25		T9	1
values[8]	961	1			T6	8		T146	12		T33	1
values[9]	98	1			T146	3		T58	22		T330	4
minimum	18271	1			T3	36		T62	40		T63	119

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T151	1		T148	2		T14	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T40	30		T51	15		T32	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T39	1		T178	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T149	1		T54	1		T32	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T38	1		T201	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T59	16		T196	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T7	3		T10	24		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T120	1		T36	10		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T72	1		T42	1		T154	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T59	1		T240	14		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	5		T6	3		T35	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T58	5		T59	8		T61	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	1		T3	3		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	12		T72	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	16		T8	14		T36	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	1		T220	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	8		T146	1		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T36	17		T46	1		T204	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T331	11		T291	3		T332	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T146	1		T58	13		T330	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17958	1			T3	35		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T70	1		T188	1		T281	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	1		T153	7		T155	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T51	15		T177	12		T254	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T39	6		T153	4		T225	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T149	13		T197	11		T311	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T48	5		T270	8		T259	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T59	13		T196	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T7	31		T146	7		T156	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T196	7		T223	11		T295	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T42	2		T155	4		T48	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T59	1		T240	2		T166	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T177	1		T260	10		T231	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T58	13		T61	15		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T3	1		T61	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T1	6		T122	9		T157	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	14		T8	11		T149	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T220	2		T197	9		T226	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T146	11		T197	13		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T204	6		T159	12		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T331	15		T332	1		T171	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T146	2		T58	9		T330	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T64	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T281	3		T333	4		T238	23

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T226	4		T199	1		T21	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T146	1		T58	13		T204	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T334	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T162	12		T188	1		T308	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T151	1		T148	1		T14	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T40	30		T51	15		T32	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T39	1		T148	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T149	1		T54	1		T32	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T201	1		T219	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T59	16		T241	14		T335	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	1		T37	3		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	1		T120	1		T196	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T7	3		T10	24		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T59	1		T36	10		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T177	1		T152	1		T260	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T58	5		T240	14		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T3	8		T6	6		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	12		T122	1		T59	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	1		T8	14		T36	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	1		T72	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	16		T6	8		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T36	17		T226	1		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T226	2		T199	2		T164	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T146	2		T58	9		T204	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T308	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	1		T153	7		T155	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T51	15		T177	12		T224	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T39	6		T153	4		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T149	13		T197	11		T254	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T159	2		T48	5		T259	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T59	13		T241	4		T104	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	7		T149	8		T233	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T1	1		T196	8		T277	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T7	31		T156	10		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T59	1		T166	9		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T177	1		T260	10		T239	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T58	13		T240	2		T250	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T61	4		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	6		T122	9		T61	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	1		T8	11		T157	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T220	2		T45	7		T197	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	14		T146	11		T197	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T226	1		T159	12		T246	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T151	1		T148	2		T14	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T40	2		T51	16		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T39	7		T178	1		T153	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T149	14		T54	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T38	1		T201	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	2		T59	14		T196	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T7	34		T10	2		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T120	1		T36	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T72	1		T42	3		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T59	2		T240	3		T166	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T6	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T58	14		T59	1		T61	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	2		T3	2		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	7		T72	1		T122	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	15		T8	13		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	1		T220	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	1		T146	12		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T36	1		T46	1		T204	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T331	16		T291	1		T332	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T146	3		T58	10		T330	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18139	1			T3	36		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T70	1		T188	1		T281	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T16	1		T286	9		T262	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	28		T51	14		T32	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T225	12		T159	2		T243	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T32	14		T197	13		T264	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T154	8		T225	10		T48	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T59	15		T196	2		T241	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T10	22		T60	24		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T36	9		T150	18		T223	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T154	10		T48	3		T246	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T240	13		T250	5		T247	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	4		T6	2		T35	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T58	4		T59	7		T61	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	2		T6	2		T61	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	11		T147	5		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	15		T8	12		T36	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T197	10		T223	14		T251	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	7		T197	18		T226	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T36	16		T204	12		T159	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T331	10		T291	2		T332	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T58	12		T300	5		T306	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T227	7		T261	10		T268	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T333	2		T238	17		T252	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T226	3		T199	3		T21	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T146	3		T58	10		T204	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T334	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T162	1		T188	1		T308	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T151	1		T148	1		T14	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T40	2		T51	16		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T39	7		T148	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T149	14		T54	1		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	1		T201	1		T219	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T59	14		T241	5		T335	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T146	8		T37	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	2		T120	1		T196	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T7	34		T10	2		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T59	2		T36	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T177	2		T152	1		T260	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T58	14		T240	3		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	3		T6	2		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	7		T122	10		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	2		T8	13		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	1		T72	1		T220	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	15		T6	1		T146	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T36	1		T226	2		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T226	3		T164	5		T332	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T58	12		T204	12		T198	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T162	11		T308	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T16	1		T286	9		T227	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	28		T51	14		T32	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T225	12		T243	9		T249	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T32	14		T197	13		T254	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	8		T225	10		T159	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T59	15		T241	13		T263	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	2		T233	11		T244	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T196	2		T264	4		T277	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1102	1			T10	22		T60	24		T55	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T36	9		T150	18		T223	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T260	8		T227	7		T239	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T58	4		T240	13		T250	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	6		T6	4		T61	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	11		T59	7		T61	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	12		T36	8		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T45	4		T197	10		T223	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	15		T6	7		T197	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T36	16		T159	12		T246	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6