Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23367

1

T1

18

T3

45

T6

14

auto[ADC_CTRL_FILTER_COND_OUT]

3459

1

T1

4

T2

30

T8

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20780

1

T1

18

T3

40

T6

3

auto[1]

6046

1

T1

4

T2

30

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	639	1			T8	11		T63	2		T72	1
values[0]	25	1			T172	1		T336	9		T326	1
values[1]	605	1			T3	4		T59	2		T149	20
values[2]	2778	1			T7	34		T10	24		T11	2
values[3]	629	1			T146	3		T147	9		T240	16
values[4]	589	1			T122	10		T151	1		T51	30
values[5]	590	1			T2	30		T3	5		T6	8
values[6]	742	1			T6	3		T146	12		T120	1
values[7]	732	1			T72	1		T35	11		T36	10
values[8]	733	1			T1	4		T6	3		T12	2
values[9]	1109	1			T1	18		T8	14		T58	40
minimum	17655	1			T3	36		T62	40		T63	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	601	1			T59	2		T36	9		T219	1
values[1]	2764	1			T7	34		T10	24		T11	2
values[2]	571	1			T146	3		T240	16		T197	32
values[3]	648	1			T122	10		T151	1		T51	30
values[4]	616	1			T2	30		T3	5		T6	8
values[5]	694	1			T6	3		T146	12		T120	1
values[6]	667	1			T1	2		T72	1		T35	11
values[7]	980	1			T1	2		T6	3		T12	2
values[8]	804	1			T1	18		T58	18		T72	1
values[9]	215	1			T8	25		T148	1		T197	20
minimum	18266	1			T3	40		T62	40		T63	119

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T32	16		T46	3		T254	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T59	1		T36	9		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T7	3		T10	24		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T147	9		T177	12		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T240	14		T197	19		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T146	1		T177	1		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T122	1		T151	1		T51	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	5		T152	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T3	5		T6	8		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	16		T39	1		T147	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	3		T146	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T37	3		T157	1		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T35	11		T54	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	1		T72	1		T36	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T6	3		T12	2		T59	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T1	1		T58	13		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T1	12		T58	5		T40	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T72	1		T38	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	6		T148	1		T159	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T8	8		T197	11		T235	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17961	1			T3	38		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T149	10		T163	7		T311	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T46	2		T254	21		T256	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T59	1		T166	10		T48	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T7	31		T146	7		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T177	12		T224	5		T262	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T240	2		T197	13		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T146	2		T177	1		T226	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T122	9		T51	15		T196	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T153	16		T248	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T177	12		T153	4		T155	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	14		T39	6		T161	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T146	11		T220	2		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	7		T250	2		T16	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T223	9		T225	2		T282	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	1		T157	1		T161	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T59	13		T61	15		T196	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T58	9		T61	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	6		T58	13		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T233	10		T204	6		T159	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T8	5		T159	11		T262	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T8	6		T197	9		T235	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	2		T64	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T149	10		T163	6		T311	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	481	1			T8	6		T63	2		T67	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T72	1		T197	11		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T172	1		T326	1		T328	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T336	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	3		T54	1		T32	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T59	1		T149	10		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T7	3		T10	24		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T36	9		T166	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T240	14		T219	1		T197	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T146	1		T147	9		T177	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T122	1		T151	1		T51	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	5		T177	1		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	5		T6	8		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	16		T39	1		T147	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	3		T146	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T37	3		T70	1		T250	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T35	11		T201	1		T54	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T72	1		T36	10		T157	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	3		T12	2		T59	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	2		T151	1		T61	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T1	12		T58	5		T61	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	8		T58	13		T38	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17509	1			T3	35		T62	40		T63	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T8	5		T266	8		T279	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T197	9		T204	6		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T328	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T336	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T3	1		T223	11		T254	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T59	1		T149	10		T272	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T7	31		T146	7		T156	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T166	10		T48	5		T224	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T240	2		T197	13		T225	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T146	2		T177	12		T153	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T122	9		T51	15		T196	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	1		T177	1		T226	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T42	2		T155	4		T222	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	14		T39	6		T161	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	11		T220	2		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T250	2		T155	10		T16	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T223	9		T225	2		T248	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T157	1		T45	7		T161	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T59	13		T241	4		T204	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	2		T61	4		T149	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	6		T58	13		T61	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	6		T58	9		T233	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T32	1		T46	3		T254	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T59	2		T36	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T7	34		T10	2		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T147	1		T177	13		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T240	3		T197	14		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T146	3		T177	2		T226	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T122	10		T151	1		T51	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	6		T152	1		T153	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	1		T6	1		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	15		T39	7		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	1		T146	12		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	1		T157	1		T45	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T35	1		T54	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	2		T72	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	1		T12	2		T59	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	2		T58	10		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	7		T58	14		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T72	1		T38	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T8	6		T148	1		T159	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T8	7		T197	10		T235	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	38		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T149	11		T163	7		T311	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T32	15		T46	2		T254	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T36	8		T48	5		T264	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T10	22		T60	24		T36	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T147	8		T177	11		T262	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T240	13		T197	18		T265	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T243	9		T227	7		T198	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T51	14		T264	4		T249	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T248	14		T266	6		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T3	4		T6	7		T59	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	15		T147	5		T32	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	2		T197	13		T244	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	2		T45	4		T250	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T35	10		T223	14		T225	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T36	9		T48	3		T239	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	2		T59	15		T61	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T58	12		T61	8		T40	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	11		T58	4		T40	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T233	11		T204	12		T159	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T8	5		T159	18		T262	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T8	7		T197	10		T182	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T3	2		T223	10		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T149	9		T163	6		T288	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	468	1			T8	6		T63	2		T67	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T72	1		T197	10		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T172	1		T326	1		T328	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T336	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	2		T54	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T59	2		T149	11		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T7	34		T10	2		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T36	1		T166	11		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T240	3		T219	1		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T146	3		T147	1		T177	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T122	10		T151	1		T51	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	6		T177	2		T226	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T6	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	15		T39	7		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T146	12		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T37	1		T70	1		T250	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T35	1		T201	1		T54	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T72	1		T36	1		T157	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	1		T12	2		T59	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	4		T151	1		T61	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T1	7		T58	14		T61	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T8	7		T58	10		T38	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17655	1			T3	36		T62	40		T63	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T8	5		T266	5		T279	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T197	10		T204	12		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T336	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	2		T32	15		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T149	9		T264	8		T162	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1102	1			T10	22		T60	24		T36	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T36	8		T48	5		T262	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T240	13		T197	18		T225	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T147	8		T177	11		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T51	14		T265	7		T249	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T198	9		T248	14		T188	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T3	4		T6	7		T59	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	15		T147	5		T32	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	2		T197	13		T177	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T37	2		T250	2		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T35	10		T223	14		T225	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T36	9		T45	4		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	2		T59	15		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	8		T40	11		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T1	11		T58	4		T61	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	7		T58	12		T233	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6