Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23370

1

T1

2

T2

30

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3456

1

T1

20

T3

5

T6

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21126

1

T2

30

T3

41

T6

11

auto[1]

5700

1

T1

22

T3

4

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	232	1			T220	3		T177	24		T250	5
values[0]	80	1			T166	10		T270	23		T274	6
values[1]	629	1			T72	1		T151	1		T36	9
values[2]	634	1			T61	13		T42	3		T54	1
values[3]	590	1			T1	2		T146	12		T120	1
values[4]	842	1			T12	2		T146	3		T58	40
values[5]	717	1			T2	30		T3	5		T6	3
values[6]	588	1			T3	4		T6	8		T59	29
values[7]	712	1			T1	18		T6	3		T122	10
values[8]	669	1			T8	14		T146	8		T59	8
values[9]	3077	1			T1	2		T7	34		T10	24
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	646	1			T151	1		T36	9		T42	3
values[1]	594	1			T1	2		T61	13		T177	29
values[2]	550	1			T146	12		T120	1		T58	18
values[3]	826	1			T6	3		T12	2		T146	3
values[4]	720	1			T2	30		T3	5		T8	11
values[5]	684	1			T1	18		T3	4		T6	8
values[6]	2748	1			T6	3		T7	34		T10	24
values[7]	763	1			T1	2		T8	14		T146	8
values[8]	786	1			T151	1		T36	27		T39	7
values[9]	169	1			T220	3		T177	24		T250	5
minimum	18340	1			T3	36		T62	40		T63	119

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T42	1		T148	1		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T151	1		T36	9		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T61	9		T150	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T177	17		T178	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T120	1		T58	5		T197	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T146	1		T149	1		T226	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	3		T12	1		T40	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T12	1		T146	1		T58	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	16		T8	6		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	5		T38	1		T44	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	3		T40	18		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	12		T6	8		T147	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T7	3		T10	24		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	3		T35	11		T197	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T59	8		T61	15		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T8	8		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T151	1		T36	27		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T39	1		T201	2		T149	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T250	3		T47	4		T198	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T220	1		T177	12		T235	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17973	1			T3	35		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T72	1		T197	11		T153	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	2		T155	10		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T177	1		T223	11		T16	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	1		T61	4		T222	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T177	12		T153	7		T243	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T58	13		T197	11		T225	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T146	11		T149	13		T226	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T161	10		T222	11		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T146	2		T58	9		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	14		T8	5		T59	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T44	2		T166	10		T196	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	1		T196	7		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	6		T153	4		T254	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T7	31		T156	10		T122	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T197	13		T159	11		T48	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T61	15		T157	1		T226	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T8	6		T146	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T149	8		T225	14		T262	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	6		T149	10		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T250	2		T198	2		T163	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T220	2		T177	12		T235	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	1		T64	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T197	9		T153	16		T243	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T250	3		T17	6		T198	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T220	1		T177	12		T231	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T166	1		T274	1		T278	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T270	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	3		T148	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T72	1		T151	1		T36	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T61	9		T42	1		T150	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T54	1		T177	17		T154	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T120	1		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	1		T149	1		T226	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T58	5		T40	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T12	1		T146	1		T58	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	16		T6	3		T8	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	5		T38	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	3		T59	16		T240	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	8		T147	15		T44	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T122	1		T59	1		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	12		T6	3		T197	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T59	8		T61	15		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	8		T146	1		T35	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T7	3		T10	24		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	1		T39	1		T201	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T250	2		T17	3		T198	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T220	2		T177	12		T231	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T166	9		T274	5		T278	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T270	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T155	10		T159	2		T260	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T197	9		T177	1		T153	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T61	4		T42	2		T286	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T177	12		T104	2		T276	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	1		T197	11		T222	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T146	11		T149	13		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T58	13		T161	10		T222	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T146	2		T58	9		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	14		T8	5		T204	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T166	10		T245	2		T155	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T3	1		T59	13		T240	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T44	2		T196	8		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T122	9		T59	1		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	6		T197	13		T159	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T61	15		T157	1		T226	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	6		T146	7		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1089	1			T7	31		T156	10		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T39	6		T149	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T42	3		T148	1		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T151	1		T36	1		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	2		T61	5		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T177	13		T178	1		T153	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T120	1		T58	14		T197	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T146	12		T149	14		T226	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	1		T12	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	1		T146	3		T58	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	15		T8	6		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	1		T38	1		T44	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	2		T40	1		T196	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	7		T6	1		T147	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T7	34		T10	2		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	1		T35	1		T197	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T59	1		T61	16		T157	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	2		T8	7		T146	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T151	1		T36	2		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	7		T201	2		T149	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T250	3		T47	3		T198	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T220	3		T177	13		T235	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18164	1			T3	36		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T72	1		T197	10		T153	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T159	2		T286	9		T234	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T36	8		T223	10		T162	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T61	8		T150	18		T264	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T177	16		T154	5		T243	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T58	4		T197	13		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T226	3		T264	8		T277	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	2		T40	11		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T58	12		T51	14		T45	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	15		T8	5		T59	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T3	4		T44	2		T196	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	2		T40	17		T250	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	11		T6	7		T147	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T10	22		T60	24		T55	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	2		T35	10		T197	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T59	7		T61	14		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T8	7		T32	14		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T36	25		T147	11		T225	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T149	9		T223	14		T204	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T250	2		T47	1		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T177	11		T190	12		T289	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T37	2		T260	8		T291	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T197	10		T154	8		T243	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T250	3		T17	7		T198	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T220	3		T177	13		T231	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T166	10		T274	6		T278	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T270	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T37	1		T148	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T72	1		T151	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T61	5		T42	3		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T54	1		T177	13		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	2		T120	1		T197	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T146	12		T149	14		T226	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T58	14		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	1		T146	3		T58	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	15		T6	1		T8	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T38	1		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	2		T59	14		T240	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T147	2		T44	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T122	10		T59	2		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	7		T6	1		T197	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T59	1		T61	16		T157	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	7		T146	8		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T7	34		T10	2		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	2		T39	7		T201	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T250	2		T17	2		T198	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T177	11		T231	8		T270	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T278	12		T186	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T270	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T37	2		T159	2		T260	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T36	8		T197	10		T154	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T61	8		T150	18		T264	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T177	16		T154	5		T251	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T197	13		T225	17		T162	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T226	3		T243	15		T277	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T58	4		T40	11		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T58	12		T51	14		T45	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	15		T6	2		T8	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	4		T254	19		T288	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	2		T59	15		T240	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T6	7		T147	13		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T233	11		T265	7		T264	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	11		T6	2		T197	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T59	7		T61	14		T244	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	7		T35	10		T32	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T10	22		T60	24		T36	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T149	9		T241	13		T223	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6