Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23405

1

T1

2

T3

40

T6

6

auto[ADC_CTRL_FILTER_COND_OUT]

3421

1

T1

20

T2

30

T3

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20936

1

T1

2

T3

41

T6

11

auto[1]

5890

1

T1

20

T2

30

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	228	1			T149	23		T152	1		T233	22
values[0]	38	1			T16	5		T217	1		T238	32
values[1]	807	1			T1	2		T6	8		T8	14
values[2]	758	1			T1	18		T2	30		T146	12
values[3]	689	1			T72	1		T59	29		T61	30
values[4]	560	1			T39	7		T54	2		T177	53
values[5]	558	1			T1	2		T3	4		T72	1
values[6]	530	1			T147	12		T149	20		T166	21
values[7]	713	1			T6	3		T58	40		T122	10
values[8]	2869	1			T3	5		T7	34		T8	11
values[9]	1020	1			T6	3		T9	1		T12	2
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	784	1			T1	20		T2	30		T8	14
values[1]	745	1			T146	12		T147	9		T45	19
values[2]	666	1			T72	1		T59	29		T61	30
values[3]	520	1			T151	1		T39	7		T147	6
values[4]	538	1			T1	2		T3	4		T72	1
values[5]	657	1			T122	10		T157	13		T147	12
values[6]	2789	1			T6	3		T7	34		T10	24
values[7]	702	1			T3	5		T8	11		T146	3
values[8]	990	1			T6	3		T9	1		T12	2
values[9]	91	1			T148	1		T47	1		T337	11
minimum	18344	1			T3	36		T6	8		T62	40

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	8		T157	1		T148	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	13		T2	16		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T219	1		T222	1		T204	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T146	1		T147	9		T45	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T72	1		T61	15		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T59	16		T33	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T151	1		T147	6		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	1		T51	15		T197	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	1		T3	3		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T72	1		T38	1		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T157	1		T147	12		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T122	1		T149	10		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T6	3		T7	3		T10	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T58	5		T151	1		T61	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	6		T146	1		T35	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	5		T36	10		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T6	3		T9	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	1		T146	1		T59	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T47	1		T110	4		T252	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T148	1		T337	1		T338	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17998	1			T3	35		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T6	8		T177	1		T187	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T8	6		T157	1		T196	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	7		T2	14		T240	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T222	1		T204	6		T277	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T146	11		T45	7		T223	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T61	15		T177	12		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T59	13		T177	12		T262	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T226	2		T161	3		T227	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T39	6		T51	15		T197	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	1		T3	1		T166	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T339	12		T228	9		T229	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T157	12		T250	10		T204	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T122	9		T149	10		T166	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T7	31		T58	9		T156	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T58	13		T61	4		T197	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	5		T146	2		T161	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T42	2		T232	8		T200	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T59	1		T149	8		T48	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T146	7		T149	13		T233	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T110	1		T252	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T337	10		T253	17		T340	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T64	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T177	1		T247	9		T325	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T149	1		T152	1		T47	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T149	1		T233	12		T154	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T16	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T217	1		T238	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	8		T40	12		T148	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T1	1		T6	8		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T157	1		T219	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	12		T2	16		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T72	1		T61	15		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T59	16		T33	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T54	2		T177	12		T226	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	1		T177	17		T154	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	1		T3	3		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T72	1		T38	1		T51	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T147	12		T166	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T149	10		T166	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	3		T58	13		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T58	5		T122	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1464	1			T7	3		T8	6		T10	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	5		T36	10		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T6	3		T9	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T12	1		T146	1		T59	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T149	8		T48	4		T330	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T149	13		T233	10		T234	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T16	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T238	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T8	6		T196	8		T232	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	1		T240	2		T241	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T157	1		T222	1		T204	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	6		T2	14		T146	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T61	15		T239	11		T34	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T59	13		T223	11		T304	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T177	12		T226	2		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T39	6		T177	12		T159	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T1	1		T3	1		T243	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T51	15		T197	11		T244	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T166	9		T245	2		T225	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T149	10		T166	10		T196	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T58	9		T220	2		T157	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T58	13		T122	9		T61	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T7	31		T8	5		T146	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T48	5		T232	8		T279	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T59	1		T223	9		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T146	7		T42	2		T305	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	7		T157	2		T148	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	9		T2	15		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T219	1		T222	2		T204	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T146	12		T147	1		T45	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T72	1		T61	16		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T59	14		T33	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T151	1		T147	1		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	7		T51	16		T197	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	2		T3	2		T166	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T72	1		T38	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T157	13		T147	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T122	10		T149	11		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T6	1		T7	34		T10	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T58	14		T151	1		T61	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T8	6		T146	3		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	1		T36	1		T42	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	1		T9	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T12	1		T146	8		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T47	1		T110	4		T252	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T148	1		T337	11		T338	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18108	1			T3	36		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T6	1		T177	2		T187	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	7		T196	2		T265	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	11		T2	15		T36	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T204	12		T162	4		T277	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T147	8		T45	4		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T61	14		T177	11		T225	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T59	15		T177	16		T262	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T147	5		T226	3		T249	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T51	14		T197	13		T154	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	2		T225	7		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T154	10		T225	10		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T147	11		T250	5		T204	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T149	9		T150	18		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1127	1			T6	2		T10	22		T58	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T58	4		T61	8		T36	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	5		T35	10		T223	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	4		T36	9		T251	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	2		T48	3		T262	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T59	7		T37	2		T40	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T110	1		T252	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T253	22		T340	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T40	11		T32	14		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T6	7		T247	10		T325	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T149	9		T152	1		T47	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T149	14		T233	11		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T16	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T217	1		T238	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	7		T40	1		T148	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	2		T6	1		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T157	2		T219	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	7		T2	15		T146	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T72	1		T61	16		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T59	14		T33	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T54	2		T177	13		T226	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	7		T177	13		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	2		T3	2		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T72	1		T38	1		T51	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T147	1		T166	10		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T149	11		T166	11		T196	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	1		T58	10		T220	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T58	14		T122	10		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T7	34		T8	6		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	1		T36	1		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	1		T9	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T12	1		T146	8		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T48	3		T283	12		T110	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T233	11		T154	8		T264	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T16	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T238	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	7		T40	11		T196	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	7		T36	16		T240	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T204	12		T254	19		T162	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	11		T2	15		T147	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T61	14		T239	11		T255	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T59	15		T223	10		T262	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T177	11		T226	3		T225	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T177	16		T154	5		T159	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	2		T147	5		T243	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T51	14		T197	13		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T147	11		T225	7		T204	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T149	9		T246	10		T266	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	2		T58	12		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T58	4		T61	8		T36	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T8	5		T10	22		T60	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	4		T36	9		T48	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	2		T223	14		T264	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T59	7		T37	2		T40	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6