Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23502

1

T1

4

T3

41

T6

11

auto[ADC_CTRL_FILTER_COND_OUT]

3324

1

T1

18

T2

30

T3

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21196

1

T1

2

T3

41

T6

14

auto[1]

5630

1

T1

20

T2

30

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	200	1			T1	2		T42	3		T147	9
values[0]	50	1			T207	1		T232	23		T312	26
values[1]	695	1			T1	2		T3	5		T38	1
values[2]	492	1			T8	11		T146	8		T220	3
values[3]	728	1			T1	18		T6	11		T12	1
values[4]	495	1			T120	1		T36	17		T45	19
values[5]	3152	1			T7	34		T10	24		T11	2
values[6]	574	1			T12	1		T59	8		T35	11
values[7]	692	1			T2	30		T9	1		T72	1
values[8]	709	1			T59	2		T166	11		T241	18
values[9]	983	1			T3	4		T6	3		T8	14
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	670	1			T146	8		T151	1		T61	30
values[1]	516	1			T1	18		T8	11		T72	1
values[2]	703	1			T6	11		T12	1		T146	15
values[3]	2714	1			T7	34		T10	24		T11	2
values[4]	941	1			T58	22		T122	10		T59	8
values[5]	583	1			T2	30		T12	1		T35	11
values[6]	603	1			T9	1		T72	1		T151	1
values[7]	875	1			T3	4		T59	2		T61	13
values[8]	740	1			T1	2		T8	14		T58	18
values[9]	157	1			T6	3		T42	3		T178	1
minimum	18324	1			T1	2		T3	41		T62	40

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T148	1		T177	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T146	1		T151	1		T61	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T59	16		T220	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	12		T8	6		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T6	11		T146	1		T36	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	1		T146	1		T240	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T7	3		T10	24		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T150	19		T187	1		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T147	6		T219	1		T197	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T58	13		T122	1		T59	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T149	1		T225	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	16		T35	11		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T72	1		T151	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T9	1		T157	1		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T59	1		T61	9		T36	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	3		T37	3		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T58	5		T147	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	8		T40	12		T14	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T178	1		T159	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T6	3		T42	1		T310	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17956	1			T1	1		T3	40		T62	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T54	1		T287	11		T247	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T177	1		T222	1		T243	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T146	7		T61	15		T196	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T59	13		T220	2		T149	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T1	6		T8	5		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T146	11		T157	12		T226	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T146	2		T240	2		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T7	31		T156	10		T315	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T159	12		T341	2		T263	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T197	13		T226	2		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T58	9		T122	9		T39	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T149	8		T225	14		T272	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T2	14		T157	1		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T241	4		T250	10		T204	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T223	9		T260	10		T277	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T59	1		T61	4		T295	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	1		T51	15		T166	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T58	13		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	6		T14	1		T244	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T159	2		T285	10		T342	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T42	2		T312	2		T343	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T3	1		T64	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T247	9		T232	10		T169	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T1	1		T147	9		T44	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T42	1		T14	5		T310	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T312	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T207	1		T232	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T3	5		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T54	1		T196	1		T197	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T220	1		T36	10		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T8	6		T146	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	11		T146	1		T59	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	12		T12	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T120	1		T36	17		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T45	12		T150	19		T304	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T7	3		T10	24		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T58	13		T122	1		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T149	1		T250	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T59	8		T35	11		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T72	1		T151	1		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	16		T9	1		T157	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T59	1		T241	14		T316	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T166	1		T177	17		T223	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T58	5		T61	9		T36	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	3		T6	3		T8	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T1	1		T44	2		T159	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T42	2		T14	1		T312	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T312	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T232	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T177	1		T222	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T196	7		T197	9		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T220	2		T149	13		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T8	5		T146	7		T61	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T146	11		T59	13		T157	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T1	6		T146	2		T240	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T226	1		T153	4		T250	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T45	7		T304	9		T234	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T7	31		T156	10		T315	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T58	9		T122	9		T39	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T149	8		T250	10		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T233	10		T46	2		T268	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T225	14		T204	4		T48	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	14		T157	1		T260	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T59	1		T241	4		T224	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T166	10		T177	12		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T58	13		T61	4		T295	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T8	6		T51	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T148	1		T177	2		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T146	8		T151	1		T61	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T59	14		T220	3		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	7		T8	6		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	2		T146	12		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T146	3		T240	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T7	34		T10	2		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T150	1		T187	1		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T147	1		T219	1		T197	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T58	10		T122	10		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T149	9		T225	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	15		T35	1		T157	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T72	1		T151	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	1		T157	1		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T59	2		T61	5		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	2		T37	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	2		T58	14		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	7		T40	1		T14	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T178	1		T159	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T6	1		T42	3		T310	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18140	1			T1	2		T3	37		T62	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T54	1		T287	1		T247	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T243	9		T262	6		T261	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T61	14		T197	10		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T59	15		T36	9		T196	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	11		T8	5		T264	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	9		T36	16		T249	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T240	13		T45	4		T32	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1088	1			T10	22		T60	24		T55	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T150	18		T159	12		T249	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T147	5		T197	18		T226	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T58	12		T59	7		T40	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T225	12		T264	4		T162	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	15		T35	10		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T241	13		T250	5		T204	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T223	14		T260	8		T277	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T61	8		T36	8		T262	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	2		T37	2		T147	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T58	4		T147	8		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	7		T40	11		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T159	2		T285	9		T318	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T6	2		T310	6		T340	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T3	4		T239	11		T312	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T287	10		T247	10		T232	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T1	2		T147	1		T44	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T42	3		T14	6		T310	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T312	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T207	1		T232	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	2		T3	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T54	1		T196	8		T197	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T220	3		T36	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T8	6		T146	8		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	2		T146	12		T59	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	7		T12	1		T146	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T120	1		T36	1		T226	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T45	15		T150	1		T304	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T7	34		T10	2		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T58	10		T122	10		T39	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T149	9		T250	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T59	1		T35	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T72	1		T151	1		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	15		T9	1		T157	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T59	2		T241	5		T316	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T166	11		T177	13		T223	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T58	14		T61	5		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	2		T6	1		T8	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T147	8		T44	2		T159	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T310	6		T288	11		T110	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T312	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T232	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	4		T262	6		T261	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T197	10		T154	10		T162	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T36	9		T154	13		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T8	5		T61	14		T251	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	9		T59	15		T196	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	11		T240	13		T32	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T36	16		T250	2		T277	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T45	4		T150	18		T249	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T10	22		T60	24		T147	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T58	12		T40	17		T149	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T250	5		T264	4		T162	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T59	7		T35	10		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T225	12		T204	2		T48	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T2	15		T260	8		T200	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T241	13		T262	20		T227	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T177	16		T223	14		T246	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T58	4		T61	8		T36	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	2		T6	2		T8	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6