Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23235

1

T1

18

T3

45

T6

8

auto[ADC_CTRL_FILTER_COND_OUT]

3591

1

T1

4

T2

30

T6

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21237

1

T1

20

T3

41

T6

14

auto[1]

5589

1

T1

2

T2

30

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	248	1			T158	1		T197	32		T154	11
values[0]	79	1			T273	8		T255	9		T266	14
values[1]	668	1			T1	20		T3	4		T8	14
values[2]	725	1			T2	30		T12	1		T146	12
values[3]	602	1			T8	11		T146	8		T157	2
values[4]	2877	1			T3	5		T6	3		T7	34
values[5]	660	1			T147	12		T149	20		T45	19
values[6]	653	1			T9	1		T12	1		T72	1
values[7]	732	1			T6	3		T59	8		T35	11
values[8]	649	1			T1	2		T157	1		T44	8
values[9]	877	1			T6	8		T58	40		T39	7
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	697	1			T1	18		T8	14		T146	12
values[1]	682	1			T2	30		T8	11		T12	1
values[2]	610	1			T6	3		T146	11		T33	1
values[3]	2899	1			T3	5		T7	34		T10	24
values[4]	685	1			T36	17		T201	1		T149	14
values[5]	640	1			T6	3		T9	1		T12	1
values[6]	713	1			T59	8		T36	10		T40	12
values[7]	646	1			T1	2		T149	9		T44	8
values[8]	758	1			T6	8		T58	40		T39	7
values[9]	235	1			T148	1		T158	1		T197	32
minimum	18261	1			T1	2		T3	40		T62	40

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	12		T122	1		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	8		T146	1		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	6		T32	15		T226	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	16		T12	1		T59	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T146	1		T38	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	3		T146	1		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T3	5		T7	3		T10	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T72	1		T61	15		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T54	1		T178	1		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	17		T201	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	1		T12	1		T35	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T6	3		T72	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T36	10		T42	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T59	8		T40	12		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T177	12		T244	3		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T149	1		T44	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	8		T58	5		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T58	13		T197	14		T198	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T158	1		T197	19		T154	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T148	1		T178	1		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17949	1			T3	38		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T1	1		T223	15		T262	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	6		T122	9		T61	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T8	6		T146	11		T51	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	5		T226	2		T153	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	14		T59	14		T157	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T146	2		T157	1		T166	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T146	7		T240	2		T246	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T7	31		T156	10		T220	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T61	15		T153	16		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T245	2		T224	5		T261	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T149	13		T45	7		T225	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T198	5		T18	4		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T166	9		T204	6		T159	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T42	2		T196	7		T197	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T241	4		T226	1		T161	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T177	12		T244	4		T250	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	1		T149	8		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T58	13		T39	6		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T58	9		T197	11		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T197	13		T243	15		T173	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T236	16		T168	11		T283	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	2		T64	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T1	1		T223	9		T262	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T158	1		T197	19		T154	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T281	1		T236	1		T168	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T266	6		T285	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T273	6		T255	9		T344	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	12		T3	3		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	1		T8	8		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T148	2		T226	4		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	16		T12	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	6		T157	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T146	1		T240	14		T335	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T3	5		T7	3		T10	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	3		T72	1		T61	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T147	12		T149	10		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T45	12		T54	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	1		T12	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T72	1		T151	1		T36	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T35	11		T36	10		T37	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	3		T59	8		T40	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T177	12		T244	3		T250	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T157	1		T44	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T6	8		T58	5		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T58	13		T148	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T197	13		T169	2		T345	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T236	7		T168	20		T283	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T266	8		T285	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T273	2		T344	8		T186	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	6		T3	1		T122	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	1		T8	6		T51	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T226	2		T153	7		T260	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	14		T146	11		T59	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	5		T157	1		T166	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T146	7		T240	2		T248	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T7	31		T146	2		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T61	15		T250	10		T222	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T149	10		T245	2		T282	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T45	7		T153	16		T225	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T224	5		T261	13		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T149	13		T166	9		T225	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T42	2		T196	7		T197	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T161	3		T19	1		T34	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T177	12		T244	4		T250	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T44	2		T241	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T58	13		T39	6		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T58	9		T149	8		T197	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	7		T122	10		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	7		T146	12		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	6		T32	1		T226	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	15		T12	1		T59	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T146	3		T38	1		T157	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	1		T146	8		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T3	1		T7	34		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T72	1		T61	16		T153	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T54	1		T178	1		T245	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T36	1		T201	1		T149	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	1		T12	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	1		T72	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	1		T42	3		T196	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T59	1		T40	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T177	13		T244	5		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	2		T149	9		T44	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	1		T58	14		T39	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T58	10		T197	12		T198	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T158	1		T197	14		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T148	1		T178	1		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18093	1			T3	38		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T1	2		T223	10		T262	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	11		T61	8		T159	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	7		T36	8		T40	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	5		T32	14		T226	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	15		T59	15		T286	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T264	4		T227	7		T288	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	2		T240	13		T249	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T3	4		T10	22		T60	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T61	14		T250	5		T256	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T261	10		T279	13		T242	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T36	16		T45	4		T225	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T35	10		T37	2		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	2		T147	8		T150	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T36	9		T197	10		T262	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T59	7		T40	11		T32	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T177	11		T244	2		T250	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	2		T264	8		T248	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	7		T58	4		T223	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T58	12		T197	13		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T197	18		T154	10		T243	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T283	12		T340	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T3	2		T196	2		T266	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T223	14		T262	11		T273	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T158	1		T197	14		T154	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T281	1		T236	8		T168	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T266	9		T285	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T273	3		T255	1		T344	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	7		T3	2		T122	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	2		T8	7		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T148	2		T226	3		T153	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	15		T12	1		T146	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	6		T157	2		T166	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T146	8		T240	3		T335	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T3	1		T7	34		T10	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T72	1		T61	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T147	1		T149	11		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T45	15		T54	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	1		T12	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T72	1		T151	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T35	1		T36	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	1		T59	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T177	13		T244	5		T250	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	2		T157	1		T44	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T6	1		T58	14		T39	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T58	10		T148	1		T149	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T197	18		T154	10		T310	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T283	12		T291	2		T312	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T266	5		T285	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T273	5		T255	8		T344	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	11		T3	2		T61	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	7		T40	17		T147	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T226	3		T260	8		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	15		T59	15		T36	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T8	5		T32	14		T159	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T240	13		T249	13		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T3	4		T10	22		T60	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	2		T61	14		T250	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T147	11		T149	9		T268	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T45	4		T225	7		T234	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T261	10		T198	9		T18	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T36	16		T147	8		T150	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T35	10		T36	9		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	2		T59	7		T40	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T177	11		T244	2		T250	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T44	2		T241	13		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	7		T58	4		T223	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T58	12		T197	13		T264	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6