Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	2		T12	1		T72	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	1		T12	1		T122	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T1	7		T7	34		T10	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	7		T120	1		T42	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	2		T59	14		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T157	1		T201	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	12		T59	1		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T146	8		T151	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	3		T36	1		T240	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T61	16		T51	16		T197	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T58	10		T61	5		T196	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	15		T219	1		T161	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	6		T201	1		T241	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T58	14		T196	9		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T151	1		T36	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T220	3		T39	7		T166	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	1		T9	1		T59	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T146	3		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T149	11		T226	2		T234	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T54	1		T222	12		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18057	1			T3	36		T62	40		T63	119
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	11		T150	18		T204	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	2		T36	16		T264	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1120	1			T1	11		T10	22		T60	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	7		T250	2		T265	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T59	15		T35	10		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T147	11		T225	7		T254	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T59	7		T159	18		T247	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T147	5		T32	15		T239	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	6		T36	8		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T61	14		T51	14		T197	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T58	12		T61	8		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T2	15		T46	2		T264	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	5		T241	13		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T58	4		T196	2		T32	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T36	9		T37	2		T197	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T197	18		T154	8		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T6	7		T225	10		T162	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	2		T40	17		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T149	9		T234	9		T266	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T249	13		T227	7		T167	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T40	1		T54	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T12	1		T40	1		T235	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T36	1		T219	1		T258	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	2		T72	2		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	1		T157	13		T149	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T1	7		T7	34		T10	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	1		T8	7		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	2		T59	14		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T42	3		T201	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T146	12		T59	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T146	8		T151	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	3		T36	1		T177	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T197	12		T70	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T58	10		T61	5		T240	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	15		T61	16		T51	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	6		T196	8		T241	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T219	1		T32	1		T161	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T151	1		T36	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T58	14		T220	3		T39	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	1		T9	1		T59	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T6	1		T146	3		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T40	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T40	11		T235	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T36	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T150	18		T204	2		T48	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T262	6		T267	2		T229	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T1	11		T10	22		T60	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	2		T8	7		T265	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T59	15		T35	10		T44	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T147	11		T250	2		T243	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T59	7		T159	18		T268	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T147	5		T32	15		T225	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T3	6		T36	8		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T197	13		T250	5		T159	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T58	12		T61	8		T240	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	15		T61	14		T51	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	5		T241	13		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T32	14		T264	8		T261	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T36	9		T37	2		T262	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T58	4		T196	2		T154	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	7		T149	9		T197	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T6	2		T147	8		T197	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6