Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23462

1

T1

2

T2

30

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3364

1

T1

20

T3

5

T6

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21166

1

T2

30

T3

41

T6

11

auto[1]

5660

1

T1

22

T3

4

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T236	15		T269	19		-	-
values[0]	76	1			T177	2		T270	23		T271	16
values[1]	649	1			T72	1		T151	1		T36	9
values[2]	620	1			T61	13		T42	3		T54	1
values[3]	620	1			T1	2		T146	12		T120	1
values[4]	790	1			T12	2		T146	3		T58	40
values[5]	708	1			T2	30		T3	5		T6	3
values[6]	599	1			T3	4		T6	8		T59	29
values[7]	664	1			T1	18		T6	3		T122	10
values[8]	670	1			T8	14		T146	8		T35	11
values[9]	3340	1			T1	2		T7	34		T10	24
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	869	1			T72	1		T151	1		T36	9
values[1]	629	1			T1	2		T61	13		T177	29
values[2]	533	1			T146	12		T120	1		T58	18
values[3]	819	1			T6	3		T12	2		T146	3
values[4]	750	1			T2	30		T3	5		T8	11
values[5]	658	1			T1	18		T6	8		T147	15
values[6]	2783	1			T3	4		T6	3		T7	34
values[7]	770	1			T1	2		T8	14		T146	8
values[8]	720	1			T151	1		T36	27		T39	7
values[9]	212	1			T220	3		T177	24		T250	5
minimum	18083	1			T3	36		T62	40		T63	119

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T37	3		T42	1		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T72	1		T151	1		T36	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T61	9		T150	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T177	17		T178	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T120	1		T58	5		T197	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	1		T149	1		T226	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	3		T12	1		T40	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T12	1		T146	1		T58	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T2	16		T8	6		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	5		T38	1		T44	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T196	1		T14	1		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	12		T6	8		T147	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T3	3		T7	3		T10	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	3		T197	19		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T59	8		T61	15		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T8	8		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T151	1		T36	27		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T39	1		T201	2		T149	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T250	3		T47	4		T262	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T220	1		T177	12		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T3	35		T62	40		T63	119
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T42	2		T166	9		T197	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T177	1		T153	16		T223	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T61	4		T222	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T177	12		T153	7		T243	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T58	13		T197	11		T225	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T146	11		T149	13		T226	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T45	7		T161	10		T222	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T146	2		T58	9		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	14		T8	5		T59	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T44	2		T166	10		T196	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T196	7		T250	10		T272	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	6		T14	1		T153	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T3	1		T7	31		T156	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T197	13		T159	11		T48	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T61	15		T157	1		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T8	6		T146	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T149	8		T225	14		T273	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	6		T149	10		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T250	2		T262	8		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T220	2		T177	12		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T64	1		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T236	1		T269	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T271	8		T274	1		T275	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T177	1		T270	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T37	3		T148	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T72	1		T151	1		T36	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T61	9		T42	1		T150	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	1		T177	17		T154	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T120	1		T197	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T146	1		T149	1		T226	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T58	5		T40	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T12	1		T146	1		T58	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	16		T6	3		T8	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	5		T33	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	3		T59	16		T240	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	8		T147	15		T44	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T122	1		T59	9		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	12		T6	3		T197	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T35	11		T157	1		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	8		T146	1		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T7	3		T10	24		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T1	1		T220	1		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T236	14		T269	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T271	8		T274	5		T275	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T177	1		T270	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T166	9		T197	9		T155	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T153	16		T223	11		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T61	4		T42	2		T159	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T177	12		T104	2		T276	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	1		T197	11		T222	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T146	11		T149	13		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T58	13		T45	7		T161	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T146	2		T58	9		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	14		T8	5		T159	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T51	15		T153	4		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T59	13		T240	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T44	2		T166	10		T196	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T122	9		T59	1		T196	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	6		T197	13		T159	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T157	1		T226	1		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	6		T146	7		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T7	31		T156	10		T61	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	1		T220	2		T39	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T37	1		T42	3		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T72	1		T151	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	2		T61	5		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T177	13		T178	1		T153	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T120	1		T58	14		T197	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T146	12		T149	14		T226	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	1		T12	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T146	3		T58	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	15		T8	6		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	1		T38	1		T44	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T196	8		T14	1		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	7		T6	1		T147	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T3	2		T7	34		T10	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	1		T197	14		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T59	1		T61	16		T157	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	2		T8	7		T146	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T151	1		T36	2		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	7		T201	2		T149	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T250	3		T47	3		T262	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T220	3		T177	13		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18071	1			T3	36		T62	40		T63	119
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	2		T197	10		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T36	8		T154	8		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T61	8		T150	18		T264	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T177	16		T154	5		T243	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T58	4		T197	13		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T226	3		T264	8		T277	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	2		T40	11		T45	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T58	12		T51	14		T32	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	15		T8	5		T59	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	4		T44	2		T196	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T250	5		T264	8		T200	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	11		T6	7		T147	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T3	2		T10	22		T60	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	2		T197	18		T159	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T59	7		T61	14		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	7		T32	14		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T36	25		T147	11		T225	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T149	9		T223	14		T204	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T250	2		T47	1		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T177	11		T19	1		T190	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T278	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T236	15		T269	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T271	9		T274	6		T275	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T177	2		T270	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T37	1		T148	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T72	1		T151	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T61	5		T42	3		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T54	1		T177	13		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	2		T120	1		T197	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T146	12		T149	14		T226	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	1		T58	14		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	1		T146	3		T58	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	15		T6	1		T8	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T33	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	2		T59	14		T240	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	1		T147	2		T44	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T122	10		T59	3		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	7		T6	1		T197	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T35	1		T157	2		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T8	7		T146	8		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T7	34		T10	2		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T1	2		T220	3		T39	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T269	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T271	7		T186	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T270	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	2		T197	10		T260	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T36	8		T154	8		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T61	8		T150	18		T159	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T177	16		T154	5		T251	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T197	13		T225	17		T198	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T226	3		T243	15		T162	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T58	4		T40	11		T45	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T58	12		T32	15		T264	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	15		T6	2		T8	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	4		T51	14		T204	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	2		T59	15		T240	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T6	7		T147	13		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T59	7		T233	11		T265	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	11		T6	2		T197	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T35	10		T244	2		T279	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	7		T32	14		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T10	22		T60	24		T61	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T149	9		T241	13		T177	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6