Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23225

1

T1

18

T3

45

T6

8

auto[ADC_CTRL_FILTER_COND_OUT]

3601

1

T1

4

T2

30

T6

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21236

1

T1

20

T3

41

T6

14

auto[1]

5590

1

T1

2

T2

30

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T188	15		T280	7		-	-
values[0]	145	1			T1	20		T8	14		T262	23
values[1]	588	1			T3	4		T120	1		T122	10
values[2]	714	1			T2	30		T12	1		T146	12
values[3]	621	1			T8	11		T146	8		T157	2
values[4]	2834	1			T3	5		T6	3		T7	34
values[5]	677	1			T147	12		T149	20		T45	19
values[6]	721	1			T9	1		T12	1		T72	1
values[7]	669	1			T6	3		T59	8		T35	11
values[8]	629	1			T1	2		T157	1		T44	8
values[9]	1150	1			T6	8		T58	40		T39	7
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	848	1			T1	20		T8	14		T120	1
values[1]	722	1			T2	30		T8	11		T12	1
values[2]	594	1			T6	3		T146	11		T33	1
values[3]	2892	1			T3	5		T7	34		T10	24
values[4]	638	1			T9	1		T36	17		T201	1
values[5]	729	1			T6	3		T12	1		T72	1
values[6]	693	1			T59	8		T36	10		T40	12
values[7]	662	1			T1	2		T149	9		T44	8
values[8]	723	1			T6	8		T58	40		T39	7
values[9]	255	1			T158	1		T178	2		T154	11
minimum	18070	1			T3	40		T62	40		T63	119

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	12		T122	1		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T1	1		T8	8		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	6		T32	15		T226	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	16		T12	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T146	1		T38	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	3		T146	1		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1513	1			T3	5		T7	3		T10	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T72	1		T61	15		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	1		T54	1		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T36	17		T201	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T35	11		T37	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T6	3		T72	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	10		T42	1		T197	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T59	8		T40	12		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T196	1		T177	12		T244	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T149	1		T44	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	8		T58	5		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T58	13		T148	1		T197	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T158	1		T178	1		T154	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T178	1		T34	1		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17914	1			T3	38		T62	40		T63	119
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	6		T122	9		T61	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T8	6		T59	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	5		T226	2		T153	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	14		T146	11		T59	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	2		T166	10		T155	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T146	7		T240	2		T246	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T7	31		T156	10		T220	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T61	15		T153	16		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T245	2		T224	5		T282	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T149	13		T45	7		T225	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T261	13		T198	5		T18	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T166	9		T161	3		T225	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T42	2		T197	9		T262	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T241	4		T226	1		T19	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T196	7		T177	12		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T149	8		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T58	13		T39	6		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T58	9		T197	11		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T243	15		T247	10		T173	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T168	11		T283	12		T284	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	2		T64	1		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T188	15		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T280	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T1	12		T285	3		T191	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T1	1		T8	8		T262	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	3		T122	1		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T120	1		T40	18		T147	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T148	2		T226	4		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	16		T12	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	6		T157	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T146	1		T240	14		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T3	5		T7	3		T10	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	3		T72	1		T61	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T147	12		T149	10		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T45	12		T54	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	1		T12	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T72	1		T151	1		T36	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T35	11		T36	10		T37	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	3		T59	8		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T177	12		T244	3		T250	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T157	1		T44	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T6	8		T58	5		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T58	13		T148	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T1	6		T285	2		T191	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T1	1		T8	6		T262	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	1		T122	9		T61	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T51	15		T161	10		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T226	2		T153	7		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	14		T146	11		T59	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T8	5		T157	1		T166	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T146	7		T240	2		T248	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T7	31		T146	2		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T61	15		T250	10		T222	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T149	10		T245	2		T48	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	7		T153	16		T225	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T224	5		T261	13		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T149	13		T166	9		T225	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T42	2		T196	7		T197	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T161	3		T34	12		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T177	12		T244	4		T250	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	1		T44	2		T241	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T58	13		T39	6		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T58	9		T149	8		T197	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	7		T122	10		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	2		T8	7		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T8	6		T32	1		T226	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	15		T12	1		T146	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T146	3		T38	1		T166	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	1		T146	8		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T3	1		T7	34		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T72	1		T61	16		T153	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	1		T54	1		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T36	1		T201	1		T149	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T35	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T72	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T36	1		T42	3		T197	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T59	1		T40	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T196	8		T177	13		T244	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	2		T149	9		T44	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	1		T58	14		T39	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T58	10		T148	1		T197	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T158	1		T178	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T178	1		T34	1		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18068	1			T3	38		T62	40		T63	119
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	11		T61	8		T196	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	7		T59	15		T36	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	5		T32	14		T226	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	15		T286	9		T287	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T264	4		T227	7		T288	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	2		T240	13		T249	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T3	4		T10	22		T60	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T61	14		T250	5		T256	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T279	13		T21	2		T242	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	16		T45	4		T225	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T35	10		T37	2		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	2		T147	8		T150	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T36	9		T197	10		T262	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T59	7		T40	11		T32	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T177	11		T244	2		T250	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T44	2		T264	8		T248	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	7		T58	4		T197	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T58	12		T197	13		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T154	10		T265	7		T243	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T283	12		T289	9		T290	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T3	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T188	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T1	7		T285	3		T191	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T1	2		T8	7		T262	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	2		T122	10		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T120	1		T40	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T148	2		T226	3		T153	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	15		T12	1		T146	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	6		T157	2		T166	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	8		T240	3		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T3	1		T7	34		T10	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T72	1		T61	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T147	1		T149	11		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T45	15		T54	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T12	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T72	1		T151	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T35	1		T36	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	1		T59	1		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T177	13		T244	5		T250	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	2		T157	1		T44	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T6	1		T58	14		T39	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T58	10		T148	1		T149	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T188	14		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T280	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T1	11		T285	2		T191	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T8	7		T262	11		T273	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	2		T61	8		T196	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	17		T147	5		T51	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T226	3		T16	1		T239	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	15		T59	15		T36	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	5		T32	14		T159	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T240	13		T249	13		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1156	1			T3	4		T10	22		T60	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	2		T61	14		T250	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T147	11		T149	9		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T45	4		T225	7		T266	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T261	10		T198	9		T18	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T36	16		T40	11		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T35	10		T36	9		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	2		T59	7		T32	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T177	11		T244	2		T250	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T44	2		T241	13		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	7		T58	4		T197	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T58	12		T197	13		T264	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6