Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21094

1

T1

2

T3

40

T6

3

auto[ADC_CTRL_FILTER_COND_OUT]

5732

1

T1

20

T2

30

T3

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21450

1

T1

18

T2

30

T3

45

auto[1]

5376

1

T1

4

T6

8

T7

34

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	54	1			T250	16		T246	21		T207	1
values[0]	45	1			T14	6		T291	3		T292	1
values[1]	741	1			T1	20		T151	1		T157	1
values[2]	701	1			T12	1		T59	29		T35	11
values[3]	579	1			T3	4		T8	14		T146	3
values[4]	639	1			T6	8		T12	1		T59	8
values[5]	750	1			T6	3		T146	8		T151	1
values[6]	628	1			T1	2		T157	13		T201	1
values[7]	641	1			T3	5		T146	12		T58	40
values[8]	469	1			T122	10		T45	19		T166	10
values[9]	3523	1			T2	30		T6	3		T7	34
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	837	1			T1	20		T12	1		T151	1
values[1]	2804	1			T7	34		T10	24		T11	2
values[2]	689	1			T3	4		T8	14		T146	3
values[3]	712	1			T6	3		T12	1		T59	8
values[4]	682	1			T1	2		T6	8		T146	8
values[5]	662	1			T58	18		T39	7		T157	13
values[6]	642	1			T3	5		T146	12		T58	22
values[7]	422	1			T8	11		T45	19		T166	10
values[8]	973	1			T2	30		T6	3		T120	1
values[9]	347	1			T9	1		T220	3		T36	17
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	1		T147	9		T14	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T1	13		T151	1		T157	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T70	1		T187	1		T154	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1427	1			T7	3		T10	24		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	3		T8	8		T40	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T146	1		T59	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	3		T59	8		T37	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	1		T151	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T33	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	8		T146	1		T61	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T157	1		T201	1		T147	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T58	5		T39	1		T149	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T122	1		T196	3		T233	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	5		T146	1		T58	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T273	1		T272	1		T293	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	6		T45	12		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T61	9		T201	1		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T2	16		T6	3		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	1		T220	1		T40	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T36	17		T32	15		T264	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	1		T46	2		T243	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	7		T157	1		T294	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T261	13		T17	3		T277	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1011	1			T7	31		T156	10		T59	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T8	6		T153	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T146	2		T59	1		T295	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T240	2		T279	13		T228	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T44	2		T155	4		T277	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	1		T196	7		T241	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T146	7		T61	15		T197	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T157	12		T149	21		T177	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T58	13		T39	6		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T122	9		T196	8		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T146	11		T58	9		T51	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T272	2		T259	13		T296	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T8	5		T45	7		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T61	4		T197	11		T161	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	14		T42	2		T166	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T220	2		T223	9		T262	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T273	2		T231	10		T285	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T250	6		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T246	11		T207	1		T263	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T14	5		T291	3		T297	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T292	1		T298	1		T299	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T147	9		T46	3		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	13		T151	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T70	1		T154	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T59	16		T35	11		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	3		T8	8		T40	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T146	1		T59	1		T36	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T59	8		T37	3		T240	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	8		T12	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T6	3		T33	1		T148	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T146	1		T151	1		T61	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	1		T157	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T148	1		T54	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T149	1		T196	3		T244	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	5		T146	1		T58	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T122	1		T233	12		T266	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T45	12		T166	1		T223	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T9	1		T220	1		T61	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1679	1			T2	16		T6	3		T7	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T250	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T246	10		T263	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T14	1		T297	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T298	3		T299	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T46	2		T243	24		T224	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	7		T294	9		T48	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T204	4		T261	13		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T59	13		T157	1		T245	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	1		T8	6		T153	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T146	2		T59	1		T262	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T240	2		T250	2		T222	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T44	2		T197	13		T295	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T241	4		T177	12		T204	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T146	7		T61	15		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	1		T157	12		T149	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T226	1		T225	2		T164	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T149	8		T196	8		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T146	11		T58	22		T39	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T122	9		T233	10		T266	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T45	7		T166	9		T223	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T220	2		T61	4		T197	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1221	1			T2	14		T7	31		T8	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	1		T147	1		T14	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	9		T151	1		T157	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T70	1		T187	1		T154	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1334	1			T7	34		T10	2		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	2		T8	7		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T146	3		T59	2		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	1		T59	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T12	1		T151	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	2		T33	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	1		T146	8		T61	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T157	13		T201	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T58	14		T39	7		T149	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T122	10		T196	9		T233	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T146	12		T58	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T273	1		T272	3		T293	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	6		T45	15		T166	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T61	5		T201	1		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	15		T6	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T9	1		T220	3		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T36	1		T32	1		T264	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T147	8		T265	7		T46	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	11		T249	20		T262	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T154	18		T261	10		T17	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1104	1			T10	22		T59	15		T60	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	2		T8	7		T40	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T150	18		T225	10		T264	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T59	7		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T44	2		T277	13		T248	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T241	13		T177	11		T204	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	7		T61	14		T197	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T147	5		T177	16		T255	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T58	4		T149	9		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T196	2		T233	11		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	4		T58	12		T51	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T300	5		T301	7		T185	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	5		T45	4		T154	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T61	8		T32	15		T197	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	15		T6	2		T36	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T40	17		T223	14		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T36	16		T32	14		T264	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T250	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T246	11		T207	1		T263	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T14	6		T291	1		T297	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T292	1		T298	4		T299	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T147	1		T46	3		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	9		T151	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T70	1		T154	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T59	14		T35	1		T157	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	2		T8	7		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T146	3		T59	2		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T59	1		T37	1		T240	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T6	1		T12	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T33	1		T148	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T146	8		T151	1		T61	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	2		T157	13		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T148	1		T54	1		T226	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T149	9		T196	9		T244	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	1		T146	12		T58	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T122	10		T233	11		T266	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T45	15		T166	10		T223	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T9	1		T220	3		T61	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1586	1			T2	15		T6	1		T7	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T250	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T246	10		T263	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T291	2		T297	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T147	8		T46	2		T243	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	11		T48	3		T249	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T154	18		T265	7		T204	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T59	15		T35	10		T287	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	2		T8	7		T40	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T36	8		T150	18		T262	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T59	7		T37	2		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	7		T44	2		T197	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	2		T241	13		T177	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	14		T149	9		T277	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T147	5		T177	11		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T225	7		T188	14		T164	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T196	2		T244	2		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	4		T58	16		T51	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T233	11		T266	5		T235	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T45	4		T223	10		T249	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T61	8		T40	17		T32	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1314	1			T2	15		T6	2		T8	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6