Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23632

1

T1

2

T3

45

T6

14

auto[ADC_CTRL_FILTER_COND_OUT]

3194

1

T1

20

T2

30

T120

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21238

1

T1

20

T3

40

T6

11

auto[1]

5588

1

T1

2

T2

30

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T278	27		T302	1		-	-
values[0]	73	1			T151	1		T162	12		T188	1
values[1]	602	1			T40	30		T148	1		T51	30
values[2]	894	1			T59	29		T39	7		T148	1
values[3]	554	1			T146	8		T38	1		T201	1
values[4]	563	1			T1	2		T12	1		T120	1
values[5]	2775	1			T7	34		T10	24		T11	2
values[6]	656	1			T240	16		T54	1		T177	2
values[7]	795	1			T1	18		T3	9		T6	6
values[8]	655	1			T1	2		T8	25		T9	1
values[9]	1175	1			T2	30		T6	8		T146	15
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	997	1			T151	1		T40	30		T148	2
values[1]	639	1			T39	7		T149	14		T54	1
values[2]	571	1			T1	2		T12	1		T59	29
values[3]	2686	1			T7	34		T10	24		T11	2
values[4]	694	1			T72	1		T59	2		T42	3
values[5]	742	1			T3	5		T6	3		T58	18
values[6]	702	1			T1	20		T3	4		T6	3
values[7]	620	1			T8	25		T9	1		T220	3
values[8]	975	1			T2	30		T6	8		T146	12
values[9]	112	1			T146	3		T58	22		T201	1
minimum	18088	1			T3	36		T62	40		T63	119

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T151	1		T148	2		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T40	30		T51	15		T14	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T39	1		T152	1		T225	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	1		T54	1		T32	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T37	3		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	1		T59	16		T196	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T7	3		T10	24		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T120	1		T36	10		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T72	1		T42	1		T240	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T59	1		T166	1		T250	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	5		T6	3		T35	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T58	5		T59	8		T61	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T3	3		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	12		T122	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	14		T9	1		T36	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T220	1		T148	1		T197	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T6	8		T146	1		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	16		T226	4		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T146	1		T201	1		T277	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T58	13		T222	1		T303	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17925	1			T3	35		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T281	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T153	4		T155	10		T304	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	15		T14	1		T177	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T39	6		T225	14		T159	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T149	13		T197	11		T262	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T48	5		T305	16		T270	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	1		T59	13		T196	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T7	31		T146	7		T156	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T196	7		T248	11		T272	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	2		T240	2		T177	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T59	1		T166	9		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T231	6		T232	10		T199	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T58	13		T61	15		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	1		T3	1		T61	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	6		T122	9		T157	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	11		T149	10		T177	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T220	2		T197	9		T226	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T146	11		T197	13		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	14		T226	2		T204	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T146	2		T277	6		T163	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T58	9		T222	1		T306	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T64	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T281	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T278	13		T302	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T151	1		T307	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T162	12		T188	1		T308	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T148	1		T155	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	30		T51	15		T32	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T39	1		T148	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T59	16		T149	1		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T146	1		T38	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T241	14		T104	5		T263	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T37	3		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	1		T120	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T7	3		T10	24		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T58	5		T59	1		T36	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T240	14		T177	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T54	1		T250	6		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T3	8		T6	6		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	12		T122	1		T59	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	1		T8	14		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T147	6		T148	1		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T6	8		T146	2		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T2	16		T58	13		T220	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T278	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T307	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T308	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T155	10		T294	9		T286	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	15		T177	12		T153	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T39	6		T153	4		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T59	13		T149	13		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T146	7		T48	5		T271	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T241	4		T104	2		T263	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T149	8		T233	10		T244	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	1		T196	8		T277	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T7	31		T156	10		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T58	13		T59	1		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T240	2		T177	1		T239	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T250	10		T245	2		T260	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	1		T61	4		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	6		T122	9		T61	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T8	11		T157	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T45	7		T197	9		T161	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T146	13		T197	13		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T2	14		T58	9		T220	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T151	1		T148	2		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T40	2		T51	16		T14	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	7		T152	1		T225	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T149	14		T54	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T37	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	2		T59	14		T196	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T7	34		T10	2		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T120	1		T36	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T72	1		T42	3		T240	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T59	2		T166	10		T250	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T6	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T58	14		T59	1		T61	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	2		T3	2		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	7		T122	10		T157	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	13		T9	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T220	3		T148	1		T197	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	1		T146	12		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T2	15		T226	3		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T146	3		T201	1		T277	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T58	10		T222	2		T303	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18074	1			T3	36		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T281	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T286	9		T262	6		T227	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T40	28		T51	14		T32	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T225	12		T159	2		T243	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T32	14		T197	13		T264	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T37	2		T154	8		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T59	15		T196	2		T241	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T10	22		T60	24		T55	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T36	9		T150	18		T264	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T240	13		T223	10		T48	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T250	5		T154	10		T247	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	4		T6	2		T35	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T58	4		T59	7		T61	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	2		T6	2		T61	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	11		T147	5		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	12		T36	8		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T197	10		T223	14		T251	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	7		T36	16		T197	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	15		T226	3		T204	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T277	6		T163	6		T291	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T58	12		T300	5		T306	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T234	9		T309	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T278	15		T302	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T151	1		T307	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T162	1		T188	1		T308	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T148	1		T155	11		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	2		T51	16		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T39	7		T148	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T59	14		T149	14		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T146	8		T38	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T241	5		T104	7		T263	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T37	1		T149	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	2		T120	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T7	34		T10	2		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T58	14		T59	2		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T240	3		T177	2		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T54	1		T250	11		T245	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	3		T6	2		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	7		T122	10		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	2		T8	13		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T147	1		T148	1		T45	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	1		T146	15		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T2	15		T58	10		T220	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T278	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T307	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T162	11		T308	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T286	9		T227	7		T261	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T40	28		T51	14		T32	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T225	12		T159	2		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T59	15		T32	14		T197	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T154	8		T225	10		T48	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T241	13		T263	7		T169	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T37	2		T233	11		T244	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T196	2		T264	4		T277	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T10	22		T60	24		T55	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T58	4		T36	9		T150	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T240	13		T227	7		T239	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T250	5		T260	8		T310	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	6		T6	4		T61	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	11		T59	7		T61	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	12		T149	9		T177	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T147	5		T45	4		T197	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T6	7		T36	24		T197	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	15		T58	12		T226	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6