Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23478

1

T1

22

T3

45

T6

8

auto[ADC_CTRL_FILTER_COND_OUT]

3348

1

T2

30

T6

6

T8

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21315

1

T1

2

T2

30

T3

45

auto[1]

5511

1

T1

20

T6

8

T7

34

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	214	1			T6	8		T9	1		T166	11
values[0]	29	1			T258	5		T106	10		T186	14
values[1]	711	1			T1	2		T12	2		T72	2
values[2]	2732	1			T1	18		T6	3		T7	34
values[3]	810	1			T1	2		T59	29		T35	11
values[4]	727	1			T146	20		T59	8		T151	1
values[5]	801	1			T3	9		T36	9		T51	30
values[6]	677	1			T2	30		T58	22		T61	43
values[7]	802	1			T8	11		T58	18		T219	1
values[8]	458	1			T220	3		T151	1		T36	10
values[9]	809	1			T6	3		T146	3		T59	2
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	643	1			T6	3		T12	1		T72	1
values[1]	2782	1			T1	18		T7	34		T8	14
values[2]	848	1			T1	2		T59	29		T35	11
values[3]	670	1			T146	20		T59	8		T151	1
values[4]	880	1			T3	9		T61	30		T36	9
values[5]	583	1			T2	30		T58	22		T61	13
values[6]	809	1			T8	11		T58	18		T37	3
values[7]	551	1			T220	3		T151	1		T36	10
values[8]	726	1			T6	11		T9	1		T146	3
values[9]	72	1			T149	20		T234	12		T266	14
minimum	18262	1			T1	2		T3	36		T12	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T72	1		T14	5		T150	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	3		T12	1		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T1	12		T7	3		T10	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	8		T120	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T59	16		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T38	1		T42	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T146	1		T59	8		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T146	1		T151	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	8		T36	9		T240	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T61	15		T51	15		T197	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T58	13		T61	9		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T2	16		T219	1		T46	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	6		T37	3		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T58	5		T196	3		T32	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T151	1		T36	10		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T220	1		T39	1		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	8		T9	1		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	3		T146	1		T40	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T149	10		T234	10		T266	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17966	1			T1	1		T3	35		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T187	1		T295	1		T232	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	1		T155	4		T48	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T122	9		T157	12		T149	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T1	6		T7	31		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T8	6		T250	2		T243	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T59	13		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T42	2		T161	3		T153	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T146	11		T153	7		T159	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	7		T157	1		T239	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	1		T240	2		T177	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T61	15		T51	15		T197	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T58	9		T61	4		T196	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T2	14		T46	2		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	5		T241	4		T48	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T58	13		T196	8		T161	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T197	9		T244	4		T159	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T220	2		T39	6		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T59	1		T226	1		T245	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T146	2		T166	10		T222	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T149	10		T234	2		T266	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	1		T3	1		T64	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T295	11		T232	8		T229	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T6	8		T9	1		T226	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T166	1		T249	14		T296	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T106	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T258	1		T186	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	1		T12	1		T72	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T122	1		T36	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1418	1			T1	12		T7	3		T10	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	3		T8	8		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	1		T59	16		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T42	1		T201	1		T147	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T146	1		T59	8		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T146	1		T151	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T3	8		T36	9		T177	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T51	15		T197	14		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T58	13		T61	9		T240	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	16		T61	15		T226	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	6		T196	1		T241	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T58	5		T219	1		T32	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T151	1		T36	10		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T220	1		T39	1		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T59	1		T149	10		T197	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T6	3		T146	1		T40	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T226	1		T266	8		T319	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T166	10		T296	2		T320	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T106	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T258	4		T186	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	1		T14	1		T155	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T122	9		T157	12		T149	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T1	6		T7	31		T156	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T8	6		T250	2		T18	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T59	13		T44	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T42	2		T161	3		T153	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T146	11		T153	7		T159	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T146	7		T157	1		T225	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T177	12		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T51	15		T197	11		T250	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T58	9		T61	4		T240	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T2	14		T61	15		T226	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	5		T196	7		T241	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T58	13		T161	10		T16	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T262	8		T239	11		T263	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T220	2		T39	6		T166	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T59	1		T149	10		T197	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T146	2		T197	13		T223	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T72	1		T14	6		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T12	1		T122	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T1	7		T7	34		T10	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	7		T120	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	2		T59	14		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T38	1		T42	3		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T146	12		T59	1		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T146	8		T151	1		T157	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	3		T36	1		T240	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T61	16		T51	16		T197	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T58	10		T61	5		T196	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	15		T219	1		T46	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	6		T37	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T58	14		T196	9		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T151	1		T36	1		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T220	3		T39	7		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	1		T9	1		T59	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	1		T146	3		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T149	11		T234	3		T266	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18120	1			T1	2		T3	36		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T187	1		T295	12		T232	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T150	18		T48	5		T251	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	2		T36	16		T40	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1125	1			T1	11		T10	22		T60	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	7		T250	2		T243	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T59	15		T35	10		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T147	11		T225	7		T254	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T59	7		T159	18		T273	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T147	5		T32	15		T239	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	6		T36	8		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	14		T51	14		T197	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T58	12		T61	8		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T2	15		T46	2		T264	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	5		T37	2		T241	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T58	4		T196	2		T32	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T36	9		T197	10		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T197	18		T154	8		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	7		T225	10		T162	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	2		T40	17		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T149	9		T234	9		T266	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T204	2		T235	15		T321	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T229	7		T83	4		T185	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T6	1		T9	1		T226	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T166	11		T249	1		T296	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T106	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T258	5		T186	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	2		T12	1		T72	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T122	10		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T1	7		T7	34		T10	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	1		T8	7		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	2		T59	14		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T42	3		T201	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	12		T59	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T146	8		T151	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	3		T36	1		T177	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T51	16		T197	12		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T58	10		T61	5		T240	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	15		T61	16		T226	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	6		T196	8		T241	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T58	14		T219	1		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T151	1		T36	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T220	3		T39	7		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T59	2		T149	11		T197	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	1		T146	3		T40	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T6	7		T225	10		T266	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T249	13		T320	15		T289	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T106	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T186	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T150	18		T204	2		T48	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T36	16		T40	11		T262	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T1	11		T10	22		T60	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T6	2		T8	7		T250	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T59	15		T35	10		T44	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T147	11		T243	15		T246	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T59	7		T159	18		T277	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T147	5		T32	15		T225	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	6		T36	8		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T51	14		T197	13		T250	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T58	12		T61	8		T240	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T2	15		T61	14		T226	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	5		T241	13		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T58	4		T32	14		T264	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T36	9		T37	2		T262	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T196	2		T154	8		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T149	9		T197	10		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	2		T40	17		T147	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6