Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26826

1

T1

22

T2

30

T3

45

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21083

1

T1

2

T3

40

T6

3

auto[ADC_CTRL_FILTER_COND_OUT]

5743

1

T1

20

T2

30

T3

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21377

1

T1

18

T2

30

T3

45

auto[1]

5449

1

T1

4

T6

8

T7

34

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22910

1

T1

14

T2

16

T3

43

auto[1]

3916

1

T1

8

T2

14

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	402	1			T72	1		T220	3		T40	18
values[0]	27	1			T14	6		T297	21		-	-
values[1]	683	1			T1	20		T157	1		T147	9
values[2]	728	1			T12	1		T59	29		T151	1
values[3]	644	1			T8	14		T146	3		T59	2
values[4]	628	1			T3	4		T6	8		T12	1
values[5]	705	1			T6	3		T146	8		T151	1
values[6]	697	1			T1	2		T157	13		T201	1
values[7]	590	1			T3	5		T146	12		T58	40
values[8]	562	1			T122	10		T45	19		T166	10
values[9]	3104	1			T2	30		T6	3		T7	34
minimum	18056	1			T3	36		T62	40		T63	119

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T1	20		T12	1		T157	3
values[1]	2708	1			T7	34		T10	24		T11	2
values[2]	769	1			T3	4		T8	14		T146	3
values[3]	637	1			T6	11		T12	1		T59	8
values[4]	752	1			T1	2		T146	8		T61	30
values[5]	632	1			T58	18		T39	7		T157	13
values[6]	668	1			T3	5		T146	12		T58	22
values[7]	379	1			T45	19		T166	10		T154	6
values[8]	1013	1			T2	30		T6	3		T8	11
values[9]	322	1			T220	3		T40	18		T15	1
minimum	18223	1			T3	36		T62	40		T63	119

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

3933

1

T1

11

T2

15

T3

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	1		T265	8		T46	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	13		T157	2		T147	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T54	1		T70	1		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1417	1			T7	3		T10	24		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	3		T8	8		T37	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T146	1		T59	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	3		T12	1		T59	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	8		T151	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	1		T33	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T146	1		T61	15		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T157	1		T201	1		T147	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T58	5		T39	1		T149	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T122	1		T196	3		T233	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	5		T146	1		T58	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T273	1		T272	1		T293	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T45	12		T166	1		T154	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T9	1		T61	9		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T2	16		T6	3		T8	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T220	1		T40	18		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T264	5		T273	6		T231	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17962	1			T3	35		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T234	10		T235	1		T322	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T46	2		T243	24		T268	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	7		T157	1		T294	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T261	13		T17	3		T277	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1007	1			T7	31		T156	10		T59	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T8	6		T153	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T146	2		T59	1		T295	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T240	2		T279	13		T228	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T44	2		T155	4		T277	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T196	7		T241	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T146	7		T61	15		T197	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T157	12		T149	21		T177	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T58	13		T39	6		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T122	9		T196	8		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T146	11		T58	9		T51	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T272	2		T259	13		T296	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T45	7		T166	9		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T61	4		T153	4		T305	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	14		T8	5		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T220	2		T197	11		T250	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T273	2		T231	10		T271	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T64	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T234	2		T235	1		T323	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T220	1		T40	18		T178	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T72	1		T153	1		T254	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T14	5		T297	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	3		T243	26		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	13		T157	1		T147	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	1		T70	1		T154	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T59	16		T151	1		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	8		T40	12		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T146	1		T59	1		T36	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	3		T12	1		T59	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	8		T38	1		T44	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	3		T33	1		T148	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T146	1		T151	1		T61	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	1		T157	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T148	1		T54	1		T197	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T149	1		T196	3		T233	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	5		T146	1		T58	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T122	1		T273	1		T266	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T45	12		T166	1		T154	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T9	1		T61	9		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1524	1			T2	16		T6	3		T7	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	35		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T220	2		T250	10		T223	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T153	16		T254	21		T286	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T14	1		T297	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T46	2		T243	24		T224	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	7		T294	9		T262	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T261	13		T17	3		T277	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T59	13		T157	1		T245	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	6		T153	7		T222	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T146	2		T59	1		T295	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T3	1		T240	2		T250	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T44	2		T16	3		T277	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T196	7		T241	4		T204	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T146	7		T61	15		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T157	12		T149	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T197	9		T226	1		T225	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T149	8		T196	8		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T146	11		T58	22		T39	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T122	9		T266	8		T272	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T45	7		T166	9		T223	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T61	4		T197	11		T153	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1112	1			T2	14		T7	31		T8	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T64	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	1		T265	1		T46	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	9		T157	3		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T54	1		T70	1		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1328	1			T7	34		T10	2		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	2		T8	7		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T146	3		T59	2		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T6	1		T12	1		T59	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	1		T151	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	2		T33	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T146	8		T61	16		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T157	13		T201	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T58	14		T39	7		T149	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T122	10		T196	9		T233	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	1		T146	12		T58	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T273	1		T272	3		T293	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T45	15		T166	10		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	1		T61	5		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T2	15		T6	1		T8	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T220	3		T40	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T264	1		T273	3		T231	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18123	1			T3	36		T62	40		T63	119
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T234	3		T235	2		T322	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T265	7		T46	2		T243	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	11		T147	8		T249	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T154	18		T261	10		T17	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1096	1			T10	22		T59	15		T60	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	2		T8	7		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T150	18		T225	10		T264	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T6	2		T59	7		T240	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	7		T44	2		T277	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T241	13		T177	11		T204	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T61	14		T197	18		T248	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T147	5		T177	16		T255	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T58	4		T149	9		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T196	2		T233	11		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	4		T58	12		T51	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T271	5		T321	2		T300	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T45	4		T154	5		T159	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T61	8		T32	15		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	15		T6	2		T8	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T40	17		T197	13		T250	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T264	4		T273	5		T231	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T239	11		T291	2		T269	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T234	9		T322	9		T324	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T220	3		T40	1		T178	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T72	1		T153	17		T254	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T14	6		T297	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	3		T243	26		T224	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	9		T157	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	1		T70	1		T154	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T59	14		T151	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	7		T40	1		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T146	3		T59	2		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	2		T12	1		T59	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	1		T38	1		T44	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T33	1		T148	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T146	8		T151	1		T61	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	2		T157	13		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T148	1		T54	1		T197	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T149	9		T196	9		T233	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T146	12		T58	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T122	10		T273	1		T266	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T45	15		T166	10		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T9	1		T61	5		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1458	1			T2	15		T6	1		T7	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T3	36		T62	40		T63	119
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T40	17		T250	5		T223	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T254	19		T264	4		T286	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T297	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	2		T243	24		T239	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	11		T147	8		T249	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T154	18		T265	7		T261	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T59	15		T35	10		T48	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	7		T40	11		T204	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T36	8		T150	18		T262	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T3	2		T59	7		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	7		T44	2		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	2		T241	13		T204	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T61	14		T149	9		T197	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T147	5		T177	27		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T197	10		T225	7		T246	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T196	2		T233	11		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	4		T58	16		T51	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T266	5		T235	15		T271	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T45	4		T154	5		T223	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T61	8		T32	15		T197	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1178	1			T2	15		T6	2		T8	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22893

1

T1

11

T2

15

T3

39

auto[1]

auto[0]

3933

1

T1

11

T2

15

T3

6