Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.07 96.67 100.00 100.00 98.83 98.33 91.39


Total test records in report: 918
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T797 /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3813459069 Jun 22 05:47:43 PM PDT 24 Jun 22 05:56:02 PM PDT 24 400628481103 ps
T798 /workspace/coverage/default/21.adc_ctrl_poweron_counter.2156023199 Jun 22 05:49:37 PM PDT 24 Jun 22 05:49:42 PM PDT 24 3649158513 ps
T799 /workspace/coverage/default/8.adc_ctrl_alert_test.1665830838 Jun 22 05:45:43 PM PDT 24 Jun 22 05:45:45 PM PDT 24 523792755 ps
T77 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.493043544 Jun 22 04:51:11 PM PDT 24 Jun 22 04:51:16 PM PDT 24 2443528995 ps
T97 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2140109964 Jun 22 04:51:14 PM PDT 24 Jun 22 04:51:17 PM PDT 24 367313196 ps
T78 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3392456074 Jun 22 04:51:02 PM PDT 24 Jun 22 04:51:04 PM PDT 24 517867073 ps
T800 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.462293273 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 437105569 ps
T801 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.280194311 Jun 22 04:51:08 PM PDT 24 Jun 22 04:51:10 PM PDT 24 438374388 ps
T138 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3950547588 Jun 22 04:51:17 PM PDT 24 Jun 22 04:51:18 PM PDT 24 519544292 ps
T123 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2450690246 Jun 22 04:51:07 PM PDT 24 Jun 22 04:51:09 PM PDT 24 327536913 ps
T79 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3535336678 Jun 22 04:51:06 PM PDT 24 Jun 22 04:51:09 PM PDT 24 4729002596 ps
T87 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2304068909 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:27 PM PDT 24 401511426 ps
T124 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4094620048 Jun 22 04:51:06 PM PDT 24 Jun 22 04:51:08 PM PDT 24 353281343 ps
T80 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.717735753 Jun 22 04:51:01 PM PDT 24 Jun 22 04:51:13 PM PDT 24 4195248806 ps
T74 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2708868195 Jun 22 04:51:07 PM PDT 24 Jun 22 04:51:18 PM PDT 24 4268784753 ps
T125 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4099002864 Jun 22 04:51:11 PM PDT 24 Jun 22 04:51:14 PM PDT 24 796894544 ps
T108 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1813074483 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:26 PM PDT 24 497701168 ps
T84 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3069901011 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:37 PM PDT 24 4206414558 ps
T802 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4078163645 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:28 PM PDT 24 392552880 ps
T81 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3688314334 Jun 22 04:51:19 PM PDT 24 Jun 22 04:51:27 PM PDT 24 4388738435 ps
T803 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2000622387 Jun 22 04:51:24 PM PDT 24 Jun 22 04:51:28 PM PDT 24 326494082 ps
T109 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1481694559 Jun 22 04:51:07 PM PDT 24 Jun 22 04:51:10 PM PDT 24 382812121 ps
T95 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1605515093 Jun 22 04:51:16 PM PDT 24 Jun 22 04:51:28 PM PDT 24 4322213303 ps
T804 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2004562931 Jun 22 04:51:30 PM PDT 24 Jun 22 04:51:32 PM PDT 24 416732495 ps
T75 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.34342767 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:36 PM PDT 24 4606750311 ps
T88 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3112633956 Jun 22 04:51:09 PM PDT 24 Jun 22 04:51:12 PM PDT 24 537108356 ps
T126 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3155360915 Jun 22 04:51:04 PM PDT 24 Jun 22 04:51:06 PM PDT 24 1055725087 ps
T805 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1976530664 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:26 PM PDT 24 477786592 ps
T139 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1229763686 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:34 PM PDT 24 2259095816 ps
T76 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1508597038 Jun 22 04:51:03 PM PDT 24 Jun 22 04:51:11 PM PDT 24 2657135263 ps
T806 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.808860675 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:26 PM PDT 24 521039880 ps
T127 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1618627571 Jun 22 04:51:02 PM PDT 24 Jun 22 04:51:06 PM PDT 24 743569754 ps
T140 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1518293992 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 563069708 ps
T807 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4272730628 Jun 22 04:51:02 PM PDT 24 Jun 22 04:51:04 PM PDT 24 435688832 ps
T808 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.445935686 Jun 22 04:51:26 PM PDT 24 Jun 22 04:51:29 PM PDT 24 527760256 ps
T809 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.209186377 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 513442485 ps
T141 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4264729528 Jun 22 04:51:13 PM PDT 24 Jun 22 04:51:17 PM PDT 24 4888067068 ps
T810 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2525707697 Jun 22 04:51:03 PM PDT 24 Jun 22 04:51:05 PM PDT 24 352563465 ps
T811 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3608760755 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:27 PM PDT 24 515116092 ps
T94 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3008404432 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:38 PM PDT 24 8390166926 ps
T142 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2510724392 Jun 22 04:51:13 PM PDT 24 Jun 22 04:51:19 PM PDT 24 2036719079 ps
T812 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4169197748 Jun 22 04:51:30 PM PDT 24 Jun 22 04:51:32 PM PDT 24 324945022 ps
T128 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2514074567 Jun 22 04:51:10 PM PDT 24 Jun 22 04:51:12 PM PDT 24 1298073136 ps
T129 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.593669480 Jun 22 04:51:20 PM PDT 24 Jun 22 04:51:24 PM PDT 24 435236733 ps
T89 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.374636563 Jun 22 04:51:08 PM PDT 24 Jun 22 04:51:16 PM PDT 24 8483588924 ps
T98 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4131154769 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 382289480 ps
T813 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1988072460 Jun 22 04:51:20 PM PDT 24 Jun 22 04:51:22 PM PDT 24 383097813 ps
T814 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3556266888 Jun 22 04:51:19 PM PDT 24 Jun 22 04:51:22 PM PDT 24 409573204 ps
T815 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1318956050 Jun 22 04:51:26 PM PDT 24 Jun 22 04:51:29 PM PDT 24 569302059 ps
T816 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.590534176 Jun 22 04:51:03 PM PDT 24 Jun 22 04:51:05 PM PDT 24 404248116 ps
T90 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3735139108 Jun 22 04:51:11 PM PDT 24 Jun 22 04:51:14 PM PDT 24 510474673 ps
T817 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1547616541 Jun 22 04:51:17 PM PDT 24 Jun 22 04:51:19 PM PDT 24 290663054 ps
T818 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3817101449 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 534274930 ps
T819 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4199937791 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 306765675 ps
T820 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1759746612 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:25 PM PDT 24 493015952 ps
T821 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2201168041 Jun 22 04:51:04 PM PDT 24 Jun 22 04:51:06 PM PDT 24 785008248 ps
T822 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3779396467 Jun 22 04:51:08 PM PDT 24 Jun 22 04:51:09 PM PDT 24 327771407 ps
T130 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2314788878 Jun 22 04:51:08 PM PDT 24 Jun 22 04:51:30 PM PDT 24 29971043294 ps
T131 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1030666375 Jun 22 04:51:11 PM PDT 24 Jun 22 04:51:16 PM PDT 24 1126787433 ps
T823 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4245216793 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 483958959 ps
T824 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3322979033 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 335230966 ps
T825 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2845970114 Jun 22 04:51:20 PM PDT 24 Jun 22 04:51:22 PM PDT 24 447588942 ps
T826 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.194050924 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 391718638 ps
T827 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3338791492 Jun 22 04:51:20 PM PDT 24 Jun 22 04:51:23 PM PDT 24 385448531 ps
T92 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.502427414 Jun 22 04:51:17 PM PDT 24 Jun 22 04:51:21 PM PDT 24 405337803 ps
T132 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3232912354 Jun 22 04:51:10 PM PDT 24 Jun 22 04:51:13 PM PDT 24 536944516 ps
T828 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4141484183 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 371532299 ps
T829 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1781183424 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 346198015 ps
T133 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3275816228 Jun 22 04:51:07 PM PDT 24 Jun 22 04:52:22 PM PDT 24 23568148871 ps
T96 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3625954758 Jun 22 04:51:30 PM PDT 24 Jun 22 04:51:32 PM PDT 24 635872812 ps
T830 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.685284414 Jun 22 04:51:26 PM PDT 24 Jun 22 04:51:29 PM PDT 24 530326553 ps
T831 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3122220517 Jun 22 04:51:15 PM PDT 24 Jun 22 04:51:16 PM PDT 24 530575856 ps
T832 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3761951287 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:26 PM PDT 24 335289084 ps
T833 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2323786064 Jun 22 04:51:06 PM PDT 24 Jun 22 04:51:08 PM PDT 24 517393536 ps
T834 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3997252276 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:26 PM PDT 24 456144730 ps
T835 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2279182113 Jun 22 04:51:15 PM PDT 24 Jun 22 04:51:22 PM PDT 24 4659388982 ps
T836 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1308474781 Jun 22 04:51:17 PM PDT 24 Jun 22 04:51:25 PM PDT 24 8676846993 ps
T837 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.314833989 Jun 22 04:51:01 PM PDT 24 Jun 22 04:51:04 PM PDT 24 849563261 ps
T93 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1690087485 Jun 22 04:51:14 PM PDT 24 Jun 22 04:51:16 PM PDT 24 458960460 ps
T838 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3844721663 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:26 PM PDT 24 2057068531 ps
T839 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1485612857 Jun 22 04:51:28 PM PDT 24 Jun 22 04:51:30 PM PDT 24 324480092 ps
T137 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2809706857 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 511529695 ps
T840 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1772118612 Jun 22 04:51:19 PM PDT 24 Jun 22 04:51:22 PM PDT 24 493240045 ps
T841 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.8756002 Jun 22 04:51:26 PM PDT 24 Jun 22 04:51:30 PM PDT 24 420536721 ps
T842 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2812859841 Jun 22 04:51:17 PM PDT 24 Jun 22 04:51:21 PM PDT 24 525114607 ps
T99 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2727948626 Jun 22 04:51:01 PM PDT 24 Jun 22 04:51:12 PM PDT 24 4384183190 ps
T843 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4277700660 Jun 22 04:51:22 PM PDT 24 Jun 22 04:51:25 PM PDT 24 411149925 ps
T134 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2643613359 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 439595088 ps
T844 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.224864229 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 328481535 ps
T845 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2591508288 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:29 PM PDT 24 8520678973 ps
T846 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2635924549 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 448984741 ps
T847 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.804468733 Jun 22 04:51:08 PM PDT 24 Jun 22 04:51:10 PM PDT 24 331415925 ps
T848 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.387873616 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:26 PM PDT 24 346906769 ps
T849 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2460122212 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:27 PM PDT 24 502643413 ps
T850 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4012942178 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 410904189 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3251289538 Jun 22 04:51:13 PM PDT 24 Jun 22 04:51:15 PM PDT 24 521009593 ps
T852 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1075194188 Jun 22 04:51:26 PM PDT 24 Jun 22 04:51:29 PM PDT 24 321981684 ps
T853 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1091504571 Jun 22 04:51:15 PM PDT 24 Jun 22 04:51:17 PM PDT 24 1979363127 ps
T854 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.996184225 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 314497388 ps
T855 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1960209457 Jun 22 04:51:16 PM PDT 24 Jun 22 04:51:18 PM PDT 24 675080085 ps
T856 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.132936941 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:29 PM PDT 24 4837093753 ps
T857 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2413473089 Jun 22 04:51:03 PM PDT 24 Jun 22 04:51:06 PM PDT 24 560274295 ps
T858 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.628517570 Jun 22 04:51:17 PM PDT 24 Jun 22 04:51:20 PM PDT 24 618050547 ps
T859 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2115501868 Jun 22 04:51:16 PM PDT 24 Jun 22 04:51:26 PM PDT 24 4153244690 ps
T860 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3139761483 Jun 22 04:51:26 PM PDT 24 Jun 22 04:51:29 PM PDT 24 538776973 ps
T861 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.630416314 Jun 22 04:51:01 PM PDT 24 Jun 22 04:51:04 PM PDT 24 409817876 ps
T346 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1910362238 Jun 22 04:51:22 PM PDT 24 Jun 22 04:51:29 PM PDT 24 4384397147 ps
T862 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4139851310 Jun 22 04:51:15 PM PDT 24 Jun 22 04:51:18 PM PDT 24 488174613 ps
T863 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3333651034 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:26 PM PDT 24 448162199 ps
T864 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4149191265 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:26 PM PDT 24 432735156 ps
T135 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3208020817 Jun 22 04:51:00 PM PDT 24 Jun 22 04:51:54 PM PDT 24 25814138660 ps
T865 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1170783046 Jun 22 04:51:16 PM PDT 24 Jun 22 04:51:32 PM PDT 24 4471912990 ps
T866 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1547977534 Jun 22 04:51:00 PM PDT 24 Jun 22 04:51:02 PM PDT 24 569287673 ps
T867 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2660812289 Jun 22 04:51:11 PM PDT 24 Jun 22 04:51:13 PM PDT 24 509831232 ps
T136 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3799721713 Jun 22 04:51:11 PM PDT 24 Jun 22 04:51:16 PM PDT 24 1034681299 ps
T868 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1074314184 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:26 PM PDT 24 336330676 ps
T869 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3117721904 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:28 PM PDT 24 574893501 ps
T870 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.706179310 Jun 22 04:51:10 PM PDT 24 Jun 22 04:51:14 PM PDT 24 479738218 ps
T871 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1052841149 Jun 22 04:51:12 PM PDT 24 Jun 22 04:51:17 PM PDT 24 4455757326 ps
T872 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3983998150 Jun 22 04:51:20 PM PDT 24 Jun 22 04:51:23 PM PDT 24 493858886 ps
T873 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1805874430 Jun 22 04:51:19 PM PDT 24 Jun 22 04:51:23 PM PDT 24 5185186943 ps
T874 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2735548796 Jun 22 04:51:20 PM PDT 24 Jun 22 04:51:23 PM PDT 24 445595778 ps
T875 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.428071260 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 573775188 ps
T100 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1369819854 Jun 22 04:51:07 PM PDT 24 Jun 22 04:51:19 PM PDT 24 7701452011 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2396831387 Jun 22 04:51:11 PM PDT 24 Jun 22 04:51:15 PM PDT 24 368898622 ps
T877 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3763269976 Jun 22 04:51:17 PM PDT 24 Jun 22 04:51:22 PM PDT 24 4615600624 ps
T878 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3255648201 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:22 PM PDT 24 392345757 ps
T879 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1905579587 Jun 22 04:51:17 PM PDT 24 Jun 22 04:51:20 PM PDT 24 308272355 ps
T880 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2895084592 Jun 22 04:51:10 PM PDT 24 Jun 22 04:51:13 PM PDT 24 452183328 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1370852677 Jun 22 04:51:10 PM PDT 24 Jun 22 04:51:59 PM PDT 24 53134698172 ps
T882 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.890199920 Jun 22 04:51:00 PM PDT 24 Jun 22 04:51:04 PM PDT 24 4641474851 ps
T883 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1321186852 Jun 22 04:51:07 PM PDT 24 Jun 22 04:51:09 PM PDT 24 539359772 ps
T884 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3451490187 Jun 22 04:51:24 PM PDT 24 Jun 22 04:51:28 PM PDT 24 402707709 ps
T885 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1663726761 Jun 22 04:51:10 PM PDT 24 Jun 22 04:51:14 PM PDT 24 489288539 ps
T886 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3156681069 Jun 22 04:51:05 PM PDT 24 Jun 22 04:51:09 PM PDT 24 508386338 ps
T887 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3032140927 Jun 22 04:51:10 PM PDT 24 Jun 22 04:51:15 PM PDT 24 736372850 ps
T888 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3044522402 Jun 22 04:51:10 PM PDT 24 Jun 22 04:51:12 PM PDT 24 435986710 ps
T889 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.351785700 Jun 22 04:51:22 PM PDT 24 Jun 22 04:51:29 PM PDT 24 4703905729 ps
T890 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2622150602 Jun 22 04:51:07 PM PDT 24 Jun 22 04:51:10 PM PDT 24 487771894 ps
T891 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.872370766 Jun 22 04:51:17 PM PDT 24 Jun 22 04:51:19 PM PDT 24 662609831 ps
T892 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1606873241 Jun 22 04:51:26 PM PDT 24 Jun 22 04:51:29 PM PDT 24 580815525 ps
T893 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4168786373 Jun 22 04:51:07 PM PDT 24 Jun 22 04:51:09 PM PDT 24 656826935 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3773745496 Jun 22 04:51:03 PM PDT 24 Jun 22 04:51:06 PM PDT 24 2315073834 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4269377661 Jun 22 04:51:14 PM PDT 24 Jun 22 04:51:17 PM PDT 24 2263530451 ps
T896 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3539080101 Jun 22 04:51:09 PM PDT 24 Jun 22 04:51:11 PM PDT 24 574142798 ps
T897 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2929202519 Jun 22 04:51:16 PM PDT 24 Jun 22 04:51:18 PM PDT 24 534559200 ps
T898 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1962623927 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 522349369 ps
T899 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3907662639 Jun 22 04:51:08 PM PDT 24 Jun 22 04:51:11 PM PDT 24 434377224 ps
T900 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.4075090947 Jun 22 04:51:45 PM PDT 24 Jun 22 04:51:47 PM PDT 24 461960825 ps
T901 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1643205345 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:20 PM PDT 24 352020641 ps
T902 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2224973081 Jun 22 04:51:26 PM PDT 24 Jun 22 04:51:29 PM PDT 24 522610845 ps
T903 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3032235643 Jun 22 04:51:02 PM PDT 24 Jun 22 04:51:03 PM PDT 24 470804520 ps
T904 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2045060966 Jun 22 04:51:18 PM PDT 24 Jun 22 04:51:23 PM PDT 24 4572767626 ps
T905 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.792934758 Jun 22 04:51:23 PM PDT 24 Jun 22 04:51:28 PM PDT 24 4788493568 ps
T906 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4098530151 Jun 22 04:51:10 PM PDT 24 Jun 22 04:51:17 PM PDT 24 4881070417 ps
T101 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3800825434 Jun 22 04:51:01 PM PDT 24 Jun 22 04:51:23 PM PDT 24 8461307172 ps
T907 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2606309968 Jun 22 04:51:02 PM PDT 24 Jun 22 04:51:05 PM PDT 24 654151650 ps
T908 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2029238402 Jun 22 04:51:25 PM PDT 24 Jun 22 04:51:29 PM PDT 24 433248352 ps
T909 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4148944975 Jun 22 04:51:03 PM PDT 24 Jun 22 04:51:05 PM PDT 24 484388467 ps
T910 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.909694101 Jun 22 04:51:32 PM PDT 24 Jun 22 04:51:33 PM PDT 24 540689751 ps
T911 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1043115627 Jun 22 04:51:22 PM PDT 24 Jun 22 04:51:27 PM PDT 24 2898827694 ps
T912 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3711245530 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:27 PM PDT 24 714140170 ps
T913 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3583278375 Jun 22 04:51:27 PM PDT 24 Jun 22 04:51:30 PM PDT 24 412359890 ps
T914 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.372242822 Jun 22 04:51:13 PM PDT 24 Jun 22 04:51:26 PM PDT 24 4719556895 ps
T915 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1917403950 Jun 22 04:51:07 PM PDT 24 Jun 22 04:51:19 PM PDT 24 2657598375 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3973638869 Jun 22 04:51:08 PM PDT 24 Jun 22 04:51:21 PM PDT 24 8165986604 ps
T917 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2578475847 Jun 22 04:51:21 PM PDT 24 Jun 22 04:51:44 PM PDT 24 4369786615 ps
T918 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4277460401 Jun 22 04:51:28 PM PDT 24 Jun 22 04:51:31 PM PDT 24 424302888 ps

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.309116558
Short name T6
Test name
Test status
Simulation time 688580738417 ps
CPU time 392.22 seconds
Started Jun 22 05:55:17 PM PDT 24
Finished Jun 22 06:01:50 PM PDT 24
Peak memory 202204 kb
Host smart-c456b0f5-beaa-4b7d-b806-939aeb56c20b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309116558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.309116558
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3364132397
Short name T64
Test name
Test status
Simulation time 208530120852 ps
CPU time 1107.55 seconds
Started Jun 22 05:43:31 PM PDT 24
Finished Jun 22 06:01:59 PM PDT 24
Peak memory 202612 kb
Host smart-9d9a6b84-0989-4c98-aa84-4638496da5e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364132397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3364132397
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.730971110
Short name T1
Test name
Test status
Simulation time 502799960030 ps
CPU time 240.59 seconds
Started Jun 22 05:46:30 PM PDT 24
Finished Jun 22 05:50:31 PM PDT 24
Peak memory 202244 kb
Host smart-26a411a9-8bfe-420c-88d3-f89f338d47ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730971110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.730971110
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2300050797
Short name T16
Test name
Test status
Simulation time 79050662317 ps
CPU time 164.09 seconds
Started Jun 22 05:48:45 PM PDT 24
Finished Jun 22 05:51:29 PM PDT 24
Peak memory 214072 kb
Host smart-aa11fa87-bb4e-4c88-b648-93ee354d1c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300050797 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2300050797
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2722968193
Short name T197
Test name
Test status
Simulation time 548895215884 ps
CPU time 608.4 seconds
Started Jun 22 05:53:27 PM PDT 24
Finished Jun 22 06:03:36 PM PDT 24
Peak memory 202300 kb
Host smart-5888b991-f591-42c7-bc04-d0f13928c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722968193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2722968193
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.419693838
Short name T3
Test name
Test status
Simulation time 425498664636 ps
CPU time 247.11 seconds
Started Jun 22 05:55:53 PM PDT 24
Finished Jun 22 06:00:01 PM PDT 24
Peak memory 202204 kb
Host smart-99633c87-22eb-4007-8c20-18d9e86c3dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419693838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
419693838
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4051754366
Short name T157
Test name
Test status
Simulation time 539227613722 ps
CPU time 110.73 seconds
Started Jun 22 05:43:03 PM PDT 24
Finished Jun 22 05:44:54 PM PDT 24
Peak memory 202344 kb
Host smart-9e88c938-6ed5-4137-9308-b64a39ad50f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051754366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4051754366
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2865998993
Short name T149
Test name
Test status
Simulation time 498140887118 ps
CPU time 586.24 seconds
Started Jun 22 05:45:07 PM PDT 24
Finished Jun 22 05:54:54 PM PDT 24
Peak memory 202252 kb
Host smart-f9df2e74-0be0-40a4-aa50-1530f8097fff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865998993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2865998993
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1569798929
Short name T47
Test name
Test status
Simulation time 23889592075 ps
CPU time 61.4 seconds
Started Jun 22 05:44:16 PM PDT 24
Finished Jun 22 05:45:18 PM PDT 24
Peak memory 210848 kb
Host smart-3b0dfb55-9389-46ec-ad86-36bb1d49e8b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569798929 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1569798929
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.4189440176
Short name T159
Test name
Test status
Simulation time 518309312556 ps
CPU time 241.9 seconds
Started Jun 22 05:44:10 PM PDT 24
Finished Jun 22 05:48:12 PM PDT 24
Peak memory 202204 kb
Host smart-14d8b6a2-23c3-45cf-8390-9122cd56bf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189440176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.4189440176
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3290815998
Short name T177
Test name
Test status
Simulation time 546862721498 ps
CPU time 219.78 seconds
Started Jun 22 05:46:16 PM PDT 24
Finished Jun 22 05:49:56 PM PDT 24
Peak memory 202204 kb
Host smart-2ffadafd-a5d5-4479-80e3-bd8876412427
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290815998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3290815998
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2304068909
Short name T87
Test name
Test status
Simulation time 401511426 ps
CPU time 2.42 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:27 PM PDT 24
Peak memory 209520 kb
Host smart-3384d92d-9006-4465-9e18-458688c470d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304068909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2304068909
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.937886249
Short name T59
Test name
Test status
Simulation time 515635548023 ps
CPU time 383.17 seconds
Started Jun 22 05:52:24 PM PDT 24
Finished Jun 22 05:58:48 PM PDT 24
Peak memory 202216 kb
Host smart-5e844573-c2bd-49eb-a0be-c6a04c8e49ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937886249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.937886249
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.195864417
Short name T5
Test name
Test status
Simulation time 4252638887 ps
CPU time 5.87 seconds
Started Jun 22 05:43:31 PM PDT 24
Finished Jun 22 05:43:38 PM PDT 24
Peak memory 217748 kb
Host smart-5d393bf3-eb19-4ffb-a48e-6d94b83140c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195864417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.195864417
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2118961866
Short name T250
Test name
Test status
Simulation time 329163908293 ps
CPU time 684.39 seconds
Started Jun 22 05:50:15 PM PDT 24
Finished Jun 22 06:01:40 PM PDT 24
Peak memory 202164 kb
Host smart-fa2f82b3-1806-424d-a8f5-5f5d03f8f4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118961866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2118961866
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.244313822
Short name T154
Test name
Test status
Simulation time 638512121889 ps
CPU time 355.74 seconds
Started Jun 22 05:55:46 PM PDT 24
Finished Jun 22 06:01:42 PM PDT 24
Peak memory 202204 kb
Host smart-4b673e80-bbf0-4404-a52a-af614d571dd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244313822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.244313822
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3877265220
Short name T262
Test name
Test status
Simulation time 480628739197 ps
CPU time 1078.91 seconds
Started Jun 22 05:48:32 PM PDT 24
Finished Jun 22 06:06:31 PM PDT 24
Peak memory 202220 kb
Host smart-388b9ac4-4b02-4afd-86cb-2b6a9c7574ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877265220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3877265220
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3392456074
Short name T78
Test name
Test status
Simulation time 517867073 ps
CPU time 1.07 seconds
Started Jun 22 04:51:02 PM PDT 24
Finished Jun 22 04:51:04 PM PDT 24
Peak memory 201156 kb
Host smart-0fce608a-691c-4503-9067-82d232cc3efc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392456074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3392456074
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1090306954
Short name T61
Test name
Test status
Simulation time 349925545116 ps
CPU time 91.06 seconds
Started Jun 22 05:55:55 PM PDT 24
Finished Jun 22 05:57:26 PM PDT 24
Peak memory 202216 kb
Host smart-976b499f-d0f9-4db7-9d82-53caf66297e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090306954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1090306954
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3129252348
Short name T248
Test name
Test status
Simulation time 356582963395 ps
CPU time 401.39 seconds
Started Jun 22 05:49:14 PM PDT 24
Finished Jun 22 05:55:56 PM PDT 24
Peak memory 202232 kb
Host smart-66f85494-b5c0-4c70-b6d7-1023dcdc89c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129252348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3129252348
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3994946858
Short name T204
Test name
Test status
Simulation time 1330381534465 ps
CPU time 3334.17 seconds
Started Jun 22 05:54:32 PM PDT 24
Finished Jun 22 06:50:07 PM PDT 24
Peak memory 213376 kb
Host smart-4599a103-3d7c-4ff8-b6d9-f342c8a58b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994946858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3994946858
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3571446279
Short name T291
Test name
Test status
Simulation time 607908464506 ps
CPU time 1076.42 seconds
Started Jun 22 05:51:04 PM PDT 24
Finished Jun 22 06:09:01 PM PDT 24
Peak memory 202212 kb
Host smart-6b5a1162-ee6e-4413-86dc-c4cdf6011edd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571446279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3571446279
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.61557692
Short name T8
Test name
Test status
Simulation time 391445117493 ps
CPU time 783.39 seconds
Started Jun 22 05:55:47 PM PDT 24
Finished Jun 22 06:08:51 PM PDT 24
Peak memory 202200 kb
Host smart-cababf63-8d3c-483e-8603-5a42dbd88b42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61557692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gatin
g.61557692
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.956357782
Short name T273
Test name
Test status
Simulation time 721871457602 ps
CPU time 1576.72 seconds
Started Jun 22 05:50:32 PM PDT 24
Finished Jun 22 06:16:49 PM PDT 24
Peak memory 202276 kb
Host smart-cec87d2d-b2bf-4f5c-a97a-4ac2f7b51a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956357782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
956357782
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2449880805
Short name T200
Test name
Test status
Simulation time 354474672504 ps
CPU time 243.86 seconds
Started Jun 22 05:51:35 PM PDT 24
Finished Jun 22 05:55:39 PM PDT 24
Peak memory 202212 kb
Host smart-0eff739e-320f-42d0-b793-c81ada69baa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449880805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2449880805
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2152540180
Short name T288
Test name
Test status
Simulation time 530948558229 ps
CPU time 1289.44 seconds
Started Jun 22 05:51:04 PM PDT 24
Finished Jun 22 06:12:34 PM PDT 24
Peak memory 202416 kb
Host smart-fc4f53de-69a7-4c89-9254-101b11ee1c02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152540180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2152540180
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.4164045051
Short name T10
Test name
Test status
Simulation time 405443123804 ps
CPU time 175.35 seconds
Started Jun 22 05:43:46 PM PDT 24
Finished Jun 22 05:46:42 PM PDT 24
Peak memory 202120 kb
Host smart-83e56204-e7e7-422f-bb44-64a392683924
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164045051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.4164045051
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2480280343
Short name T234
Test name
Test status
Simulation time 349592608283 ps
CPU time 391.42 seconds
Started Jun 22 05:45:53 PM PDT 24
Finished Jun 22 05:52:25 PM PDT 24
Peak memory 202224 kb
Host smart-2c328600-ca80-4faa-9c54-ec4ecb4d5019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480280343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2480280343
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3281418044
Short name T226
Test name
Test status
Simulation time 332499168313 ps
CPU time 98.96 seconds
Started Jun 22 05:52:07 PM PDT 24
Finished Jun 22 05:53:46 PM PDT 24
Peak memory 202216 kb
Host smart-bc72ad0e-748e-4281-b6aa-a01f1609d1c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281418044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3281418044
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3678156821
Short name T238
Test name
Test status
Simulation time 344533459357 ps
CPU time 427.58 seconds
Started Jun 22 05:54:27 PM PDT 24
Finished Jun 22 06:01:35 PM PDT 24
Peak memory 202284 kb
Host smart-6ac0104f-6695-4fb3-b040-569bc9c7b2a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678156821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3678156821
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1422556846
Short name T186
Test name
Test status
Simulation time 509728483655 ps
CPU time 221.48 seconds
Started Jun 22 05:48:07 PM PDT 24
Finished Jun 22 05:51:49 PM PDT 24
Peak memory 202156 kb
Host smart-24b91a85-02b1-4f80-b94c-a6555f0912de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422556846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1422556846
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.864006544
Short name T232
Test name
Test status
Simulation time 526620602636 ps
CPU time 1214.26 seconds
Started Jun 22 05:49:25 PM PDT 24
Finished Jun 22 06:09:40 PM PDT 24
Peak memory 202504 kb
Host smart-372902ab-0ee7-48f0-838c-997256680260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864006544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
864006544
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3862241110
Short name T91
Test name
Test status
Simulation time 317483301 ps
CPU time 0.96 seconds
Started Jun 22 05:46:22 PM PDT 24
Finished Jun 22 05:46:24 PM PDT 24
Peak memory 201924 kb
Host smart-a5ca2be6-a5b6-4528-98c9-faae47e20841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862241110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3862241110
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2727948626
Short name T99
Test name
Test status
Simulation time 4384183190 ps
CPU time 9.91 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:12 PM PDT 24
Peak memory 201392 kb
Host smart-c97f3f64-3775-4048-9d00-a6342a6c7cee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727948626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2727948626
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3714633478
Short name T259
Test name
Test status
Simulation time 505202099111 ps
CPU time 1511.95 seconds
Started Jun 22 05:52:18 PM PDT 24
Finished Jun 22 06:17:30 PM PDT 24
Peak memory 212548 kb
Host smart-ed7142b4-a3b1-4626-9ad2-628b847a6d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714633478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3714633478
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.713449988
Short name T167
Test name
Test status
Simulation time 610467516175 ps
CPU time 379.91 seconds
Started Jun 22 05:52:08 PM PDT 24
Finished Jun 22 05:58:29 PM PDT 24
Peak memory 202200 kb
Host smart-e50b6f80-5fb0-4f34-ae40-3bcfd3755795
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713449988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.713449988
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.890199548
Short name T312
Test name
Test status
Simulation time 345370170896 ps
CPU time 339.12 seconds
Started Jun 22 05:48:15 PM PDT 24
Finished Jun 22 05:53:55 PM PDT 24
Peak memory 202192 kb
Host smart-64b24e3a-22d1-49fe-9f56-615e3b91e3a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890199548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
890199548
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2570432799
Short name T269
Test name
Test status
Simulation time 329876085086 ps
CPU time 208.92 seconds
Started Jun 22 05:54:22 PM PDT 24
Finished Jun 22 05:57:51 PM PDT 24
Peak memory 202224 kb
Host smart-b6e34710-76de-4a38-a4d7-cc5299a3299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570432799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2570432799
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1295369716
Short name T228
Test name
Test status
Simulation time 513807776361 ps
CPU time 618.53 seconds
Started Jun 22 05:47:27 PM PDT 24
Finished Jun 22 05:57:46 PM PDT 24
Peak memory 202156 kb
Host smart-5328aadd-6cc8-467e-b9c5-cb1a7c53df5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295369716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1295369716
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3720540510
Short name T188
Test name
Test status
Simulation time 530615366053 ps
CPU time 752.65 seconds
Started Jun 22 05:54:48 PM PDT 24
Finished Jun 22 06:07:21 PM PDT 24
Peak memory 202180 kb
Host smart-71e1de99-3a2a-4425-a13d-fdeaffeb76a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720540510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3720540510
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4141258423
Short name T14
Test name
Test status
Simulation time 81433277300 ps
CPU time 167.79 seconds
Started Jun 22 05:51:27 PM PDT 24
Finished Jun 22 05:54:15 PM PDT 24
Peak memory 219012 kb
Host smart-2e6a9d9a-2ea0-424c-9b6b-bae93c2f56a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141258423 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.4141258423
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1100940638
Short name T58
Test name
Test status
Simulation time 331038959979 ps
CPU time 337.18 seconds
Started Jun 22 05:52:56 PM PDT 24
Finished Jun 22 05:58:34 PM PDT 24
Peak memory 202224 kb
Host smart-c07a9c34-ae33-4d2d-8843-2bc94bc473c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100940638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1100940638
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1508597038
Short name T76
Test name
Test status
Simulation time 2657135263 ps
CPU time 7.16 seconds
Started Jun 22 04:51:03 PM PDT 24
Finished Jun 22 04:51:11 PM PDT 24
Peak memory 201392 kb
Host smart-f1ca4d4a-9842-4d4f-8c34-5fe3cf8c54c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508597038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1508597038
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3257765323
Short name T313
Test name
Test status
Simulation time 191852023934 ps
CPU time 78.46 seconds
Started Jun 22 05:55:18 PM PDT 24
Finished Jun 22 05:56:37 PM PDT 24
Peak memory 210776 kb
Host smart-543bd9c1-2284-4794-9a33-3d7e90b44c83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257765323 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3257765323
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2942360177
Short name T253
Test name
Test status
Simulation time 639978191460 ps
CPU time 325.62 seconds
Started Jun 22 05:42:37 PM PDT 24
Finished Jun 22 05:48:03 PM PDT 24
Peak memory 202184 kb
Host smart-9235f51c-f329-4756-92af-3313f47286a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942360177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2942360177
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3204420431
Short name T285
Test name
Test status
Simulation time 491445884607 ps
CPU time 297.85 seconds
Started Jun 22 05:44:11 PM PDT 24
Finished Jun 22 05:49:10 PM PDT 24
Peak memory 202296 kb
Host smart-cb1df412-0132-416e-99a1-e8780535602d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204420431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3204420431
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3903190055
Short name T278
Test name
Test status
Simulation time 173902680674 ps
CPU time 403.73 seconds
Started Jun 22 05:42:38 PM PDT 24
Finished Jun 22 05:49:22 PM PDT 24
Peak memory 202220 kb
Host smart-1bbc2de6-c039-4e58-bcbe-4f2f51c5db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903190055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3903190055
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3664067066
Short name T40
Test name
Test status
Simulation time 357657747768 ps
CPU time 94.13 seconds
Started Jun 22 05:48:57 PM PDT 24
Finished Jun 22 05:50:31 PM PDT 24
Peak memory 202280 kb
Host smart-dc0d5221-bd23-4f38-8d35-3270d8b49b55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664067066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3664067066
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1312089160
Short name T34
Test name
Test status
Simulation time 549408603581 ps
CPU time 923.18 seconds
Started Jun 22 05:49:45 PM PDT 24
Finished Jun 22 06:05:08 PM PDT 24
Peak memory 210968 kb
Host smart-3f413157-4839-42ca-be8b-283a07fb4beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312089160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1312089160
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.502427414
Short name T92
Test name
Test status
Simulation time 405337803 ps
CPU time 3.12 seconds
Started Jun 22 04:51:17 PM PDT 24
Finished Jun 22 04:51:21 PM PDT 24
Peak memory 217372 kb
Host smart-5c074903-2f92-4bb2-8fc3-b1b8c81ac233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502427414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.502427414
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3274077094
Short name T246
Test name
Test status
Simulation time 497651960411 ps
CPU time 564.72 seconds
Started Jun 22 05:49:28 PM PDT 24
Finished Jun 22 05:58:53 PM PDT 24
Peak memory 202216 kb
Host smart-497acb32-9a07-4673-8ab7-21981c4db36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274077094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3274077094
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3410742143
Short name T270
Test name
Test status
Simulation time 534368925598 ps
CPU time 1283.21 seconds
Started Jun 22 05:43:44 PM PDT 24
Finished Jun 22 06:05:08 PM PDT 24
Peak memory 202284 kb
Host smart-7c5d87f2-a63e-4cc9-8d7e-edd5063abaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410742143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3410742143
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.684654822
Short name T166
Test name
Test status
Simulation time 326708572879 ps
CPU time 192.43 seconds
Started Jun 22 05:53:33 PM PDT 24
Finished Jun 22 05:56:46 PM PDT 24
Peak memory 202224 kb
Host smart-99db73f9-bdde-42ad-ab41-400f6750407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684654822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.684654822
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2670786245
Short name T172
Test name
Test status
Simulation time 495727656780 ps
CPU time 308.12 seconds
Started Jun 22 05:47:52 PM PDT 24
Finished Jun 22 05:53:01 PM PDT 24
Peak memory 202500 kb
Host smart-5e47cc12-d974-470d-97b9-e744c2bc50a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670786245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2670786245
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2276844332
Short name T307
Test name
Test status
Simulation time 325506727438 ps
CPU time 75.26 seconds
Started Jun 22 05:49:54 PM PDT 24
Finished Jun 22 05:51:09 PM PDT 24
Peak memory 202176 kb
Host smart-d9a6f7e4-8b93-43f7-93e3-f94765501b1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276844332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2276844332
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.975996073
Short name T163
Test name
Test status
Simulation time 540846017979 ps
CPU time 338.55 seconds
Started Jun 22 05:45:02 PM PDT 24
Finished Jun 22 05:50:40 PM PDT 24
Peak memory 202224 kb
Host smart-85bddabd-8906-4bd0-87de-69895bfc10d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975996073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.975996073
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2121409498
Short name T336
Test name
Test status
Simulation time 434536232938 ps
CPU time 811.72 seconds
Started Jun 22 05:48:32 PM PDT 24
Finished Jun 22 06:02:04 PM PDT 24
Peak memory 213384 kb
Host smart-ea315f5a-be89-4a86-9878-820c49506896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121409498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2121409498
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2246852961
Short name T308
Test name
Test status
Simulation time 348495382972 ps
CPU time 769.68 seconds
Started Jun 22 05:48:40 PM PDT 24
Finished Jun 22 06:01:30 PM PDT 24
Peak memory 202228 kb
Host smart-2d62c8c1-231e-4c5f-9c45-121a6ddca8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246852961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2246852961
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1152444229
Short name T311
Test name
Test status
Simulation time 366130654007 ps
CPU time 785.31 seconds
Started Jun 22 05:53:50 PM PDT 24
Finished Jun 22 06:06:55 PM PDT 24
Peak memory 202276 kb
Host smart-34661165-2b63-4f55-a2a7-06b2d07ac337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152444229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1152444229
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.817630549
Short name T106
Test name
Test status
Simulation time 151507186462 ps
CPU time 149.14 seconds
Started Jun 22 05:45:22 PM PDT 24
Finished Jun 22 05:47:51 PM PDT 24
Peak memory 211064 kb
Host smart-f78bf396-7a8b-42de-bed2-4d8ea35016ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817630549 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.817630549
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2548469520
Short name T148
Test name
Test status
Simulation time 493125057916 ps
CPU time 118.03 seconds
Started Jun 22 05:50:39 PM PDT 24
Finished Jun 22 05:52:38 PM PDT 24
Peak memory 202308 kb
Host smart-e937d1a9-4b43-418b-95f6-eb85d689cfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548469520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2548469520
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1301403284
Short name T298
Test name
Test status
Simulation time 487350359275 ps
CPU time 285.84 seconds
Started Jun 22 05:50:46 PM PDT 24
Finished Jun 22 05:55:33 PM PDT 24
Peak memory 202288 kb
Host smart-80451c61-80ea-462c-ad2c-fbd7aebd4654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301403284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1301403284
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.4074298168
Short name T281
Test name
Test status
Simulation time 319630200664 ps
CPU time 359.19 seconds
Started Jun 22 05:51:05 PM PDT 24
Finished Jun 22 05:57:05 PM PDT 24
Peak memory 202128 kb
Host smart-0138bcd9-e4a1-4260-b46e-bfc799423771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074298168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.4074298168
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1985026257
Short name T280
Test name
Test status
Simulation time 350377701669 ps
CPU time 837.61 seconds
Started Jun 22 05:52:41 PM PDT 24
Finished Jun 22 06:06:39 PM PDT 24
Peak memory 202228 kb
Host smart-cd6e0bdf-1ab6-43f3-9838-6e38623e80ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985026257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1985026257
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.282593100
Short name T41
Test name
Test status
Simulation time 98583499454 ps
CPU time 555.63 seconds
Started Jun 22 05:54:56 PM PDT 24
Finished Jun 22 06:04:12 PM PDT 24
Peak memory 202556 kb
Host smart-27473089-a697-46cf-8a6d-59d5428b0df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282593100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.282593100
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2978837849
Short name T267
Test name
Test status
Simulation time 123769558047 ps
CPU time 142.71 seconds
Started Jun 22 05:44:43 PM PDT 24
Finished Jun 22 05:47:06 PM PDT 24
Peak memory 210908 kb
Host smart-a4786994-6036-46c5-930a-c000745807d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978837849 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2978837849
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.836288104
Short name T206
Test name
Test status
Simulation time 105652394609 ps
CPU time 349.76 seconds
Started Jun 22 05:42:38 PM PDT 24
Finished Jun 22 05:48:28 PM PDT 24
Peak memory 202480 kb
Host smart-8562ff24-2d08-4be7-8bc4-7558b8aba869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836288104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.836288104
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.977684575
Short name T252
Test name
Test status
Simulation time 264000651668 ps
CPU time 479.77 seconds
Started Jun 22 05:42:45 PM PDT 24
Finished Jun 22 05:50:45 PM PDT 24
Peak memory 218336 kb
Host smart-6786288a-aeee-4f54-858b-9b1988c11d82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977684575 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.977684575
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2333568451
Short name T283
Test name
Test status
Simulation time 495926267427 ps
CPU time 291.06 seconds
Started Jun 22 05:43:14 PM PDT 24
Finished Jun 22 05:48:05 PM PDT 24
Peak memory 202224 kb
Host smart-56819375-ef2c-4f9f-9cd9-96cf2a45c072
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333568451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2333568451
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.596679153
Short name T334
Test name
Test status
Simulation time 332428421815 ps
CPU time 181.09 seconds
Started Jun 22 05:49:05 PM PDT 24
Finished Jun 22 05:52:06 PM PDT 24
Peak memory 202280 kb
Host smart-32b93054-4b58-40d3-a35d-c9decfacf632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596679153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.596679153
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1054794661
Short name T214
Test name
Test status
Simulation time 548760387931 ps
CPU time 1293.41 seconds
Started Jun 22 05:51:29 PM PDT 24
Finished Jun 22 06:13:03 PM PDT 24
Peak memory 210788 kb
Host smart-cd703b9c-94c9-4b38-82cf-2d9fd0ed3b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054794661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1054794661
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1927011868
Short name T171
Test name
Test status
Simulation time 425501788614 ps
CPU time 250.48 seconds
Started Jun 22 05:53:01 PM PDT 24
Finished Jun 22 05:57:12 PM PDT 24
Peak memory 210856 kb
Host smart-fc21a3f7-f414-4048-a151-a8dc110f5c3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927011868 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1927011868
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1012819833
Short name T21
Test name
Test status
Simulation time 1796909471136 ps
CPU time 237.96 seconds
Started Jun 22 05:53:40 PM PDT 24
Finished Jun 22 05:57:38 PM PDT 24
Peak memory 212828 kb
Host smart-40b97fb2-303b-4d41-b3ad-f6a326079fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012819833 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1012819833
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2504614195
Short name T328
Test name
Test status
Simulation time 157880797051 ps
CPU time 35.6 seconds
Started Jun 22 05:45:52 PM PDT 24
Finished Jun 22 05:46:28 PM PDT 24
Peak memory 202304 kb
Host smart-990f2487-970d-44e5-bd60-49cbeb33cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504614195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2504614195
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3008404432
Short name T94
Test name
Test status
Simulation time 8390166926 ps
CPU time 14.61 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:38 PM PDT 24
Peak memory 201284 kb
Host smart-b6e1a3aa-048e-4296-9fde-0837af692ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008404432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3008404432
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.925940641
Short name T759
Test name
Test status
Simulation time 605916175030 ps
CPU time 1138.83 seconds
Started Jun 22 05:42:36 PM PDT 24
Finished Jun 22 06:01:36 PM PDT 24
Peak memory 202204 kb
Host smart-55ca60e4-de7e-408c-bb35-5f9ff1499164
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925940641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.925940641
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.367285445
Short name T209
Test name
Test status
Simulation time 131484387103 ps
CPU time 447.49 seconds
Started Jun 22 05:46:57 PM PDT 24
Finished Jun 22 05:54:24 PM PDT 24
Peak memory 202512 kb
Host smart-7b432409-95c0-4fac-8c06-e9015cc1cc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367285445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.367285445
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1477342347
Short name T51
Test name
Test status
Simulation time 1112478886936 ps
CPU time 2729.78 seconds
Started Jun 22 05:47:12 PM PDT 24
Finished Jun 22 06:32:42 PM PDT 24
Peak memory 210776 kb
Host smart-007c09a0-a5c0-47aa-99bc-b7fa8e29b125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477342347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1477342347
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3571007722
Short name T243
Test name
Test status
Simulation time 329767443293 ps
CPU time 671.48 seconds
Started Jun 22 05:47:40 PM PDT 24
Finished Jun 22 05:58:52 PM PDT 24
Peak memory 202180 kb
Host smart-a0eee793-66b3-4b65-9bf3-0f6dca054d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571007722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3571007722
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.509773937
Short name T211
Test name
Test status
Simulation time 113735512449 ps
CPU time 524.33 seconds
Started Jun 22 05:47:41 PM PDT 24
Finished Jun 22 05:56:25 PM PDT 24
Peak memory 202492 kb
Host smart-84795219-d0b4-4c16-b528-05c94d4bb107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509773937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.509773937
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2577315984
Short name T222
Test name
Test status
Simulation time 333877674009 ps
CPU time 374.97 seconds
Started Jun 22 05:49:06 PM PDT 24
Finished Jun 22 05:55:21 PM PDT 24
Peak memory 202496 kb
Host smart-e7546b28-da8d-499e-9bf6-8a5c2859c4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577315984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2577315984
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1474311746
Short name T327
Test name
Test status
Simulation time 329003962743 ps
CPU time 750.5 seconds
Started Jun 22 05:49:44 PM PDT 24
Finished Jun 22 06:02:14 PM PDT 24
Peak memory 202220 kb
Host smart-110d2d09-abe2-45da-899b-c4e7d40c82db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474311746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1474311746
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3846423400
Short name T36
Test name
Test status
Simulation time 538874497648 ps
CPU time 290.71 seconds
Started Jun 22 05:54:20 PM PDT 24
Finished Jun 22 05:59:11 PM PDT 24
Peak memory 202256 kb
Host smart-3096f977-5363-4db6-8619-2a3841a01629
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846423400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3846423400
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.730369865
Short name T57
Test name
Test status
Simulation time 96053169808 ps
CPU time 408.55 seconds
Started Jun 22 05:54:21 PM PDT 24
Finished Jun 22 06:01:10 PM PDT 24
Peak memory 202816 kb
Host smart-dbcce9e3-5ed3-4417-9088-4591c4150ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730369865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.730369865
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1634841917
Short name T297
Test name
Test status
Simulation time 166325409526 ps
CPU time 397.26 seconds
Started Jun 22 05:54:35 PM PDT 24
Finished Jun 22 06:01:13 PM PDT 24
Peak memory 202216 kb
Host smart-b96f487f-cd68-4c97-8caa-332e6f31ac77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634841917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1634841917
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2219498371
Short name T235
Test name
Test status
Simulation time 496353073435 ps
CPU time 118.3 seconds
Started Jun 22 05:55:28 PM PDT 24
Finished Jun 22 05:57:27 PM PDT 24
Peak memory 202216 kb
Host smart-9f408954-42a1-4c7e-b9b9-7cf40a5ce086
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219498371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2219498371
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2526659194
Short name T351
Test name
Test status
Simulation time 106060187500 ps
CPU time 488.74 seconds
Started Jun 22 05:55:54 PM PDT 24
Finished Jun 22 06:04:03 PM PDT 24
Peak memory 202468 kb
Host smart-a4f4df0e-7a21-438b-a940-5125138b61e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526659194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2526659194
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1618627571
Short name T127
Test name
Test status
Simulation time 743569754 ps
CPU time 3.05 seconds
Started Jun 22 04:51:02 PM PDT 24
Finished Jun 22 04:51:06 PM PDT 24
Peak memory 201256 kb
Host smart-9f36f484-14c8-455b-bffd-cd7e51e566ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618627571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1618627571
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3155360915
Short name T126
Test name
Test status
Simulation time 1055725087 ps
CPU time 1.33 seconds
Started Jun 22 04:51:04 PM PDT 24
Finished Jun 22 04:51:06 PM PDT 24
Peak memory 201116 kb
Host smart-8d8e5b63-2194-41f1-bf89-e5fba2da2d93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155360915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3155360915
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3032235643
Short name T903
Test name
Test status
Simulation time 470804520 ps
CPU time 1.1 seconds
Started Jun 22 04:51:02 PM PDT 24
Finished Jun 22 04:51:03 PM PDT 24
Peak memory 201184 kb
Host smart-c65ad31c-8117-43f3-9808-58a0338f692e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032235643 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3032235643
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4094620048
Short name T124
Test name
Test status
Simulation time 353281343 ps
CPU time 1.49 seconds
Started Jun 22 04:51:06 PM PDT 24
Finished Jun 22 04:51:08 PM PDT 24
Peak memory 200976 kb
Host smart-c00a5962-2194-411a-97b5-dbf360e00a8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094620048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4094620048
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2525707697
Short name T810
Test name
Test status
Simulation time 352563465 ps
CPU time 1.03 seconds
Started Jun 22 04:51:03 PM PDT 24
Finished Jun 22 04:51:05 PM PDT 24
Peak memory 201012 kb
Host smart-c71755a5-4273-4f71-a1c3-7dab167fe9bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525707697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2525707697
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.890199920
Short name T882
Test name
Test status
Simulation time 4641474851 ps
CPU time 3.84 seconds
Started Jun 22 04:51:00 PM PDT 24
Finished Jun 22 04:51:04 PM PDT 24
Peak memory 201404 kb
Host smart-7a76cc0b-bee3-4593-a14f-2d91bb313844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890199920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.890199920
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.630416314
Short name T861
Test name
Test status
Simulation time 409817876 ps
CPU time 2.33 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:04 PM PDT 24
Peak memory 210676 kb
Host smart-19bb7e98-226a-46af-85c0-8ed1ba34e1d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630416314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.630416314
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3800825434
Short name T101
Test name
Test status
Simulation time 8461307172 ps
CPU time 21.57 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:23 PM PDT 24
Peak memory 201380 kb
Host smart-fa048441-a2cd-420a-b6be-b49fd4bb5746
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800825434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3800825434
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.314833989
Short name T837
Test name
Test status
Simulation time 849563261 ps
CPU time 2.03 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:04 PM PDT 24
Peak memory 201212 kb
Host smart-cb5d18c6-5e1e-4d35-acbb-24c7130825d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314833989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.314833989
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3208020817
Short name T135
Test name
Test status
Simulation time 25814138660 ps
CPU time 53.51 seconds
Started Jun 22 04:51:00 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201348 kb
Host smart-7d4f52f0-03b4-4e0c-ab62-8797b93b866c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208020817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3208020817
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2606309968
Short name T907
Test name
Test status
Simulation time 654151650 ps
CPU time 1.27 seconds
Started Jun 22 04:51:02 PM PDT 24
Finished Jun 22 04:51:05 PM PDT 24
Peak memory 201020 kb
Host smart-a868be41-d5eb-4f87-81fc-de95c14f99b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606309968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2606309968
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4148944975
Short name T909
Test name
Test status
Simulation time 484388467 ps
CPU time 1.07 seconds
Started Jun 22 04:51:03 PM PDT 24
Finished Jun 22 04:51:05 PM PDT 24
Peak memory 201220 kb
Host smart-91e2aae5-43f6-4963-bfe8-91b9f7d41a50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148944975 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4148944975
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1547977534
Short name T866
Test name
Test status
Simulation time 569287673 ps
CPU time 2.18 seconds
Started Jun 22 04:51:00 PM PDT 24
Finished Jun 22 04:51:02 PM PDT 24
Peak memory 201160 kb
Host smart-0e2508b4-3d4e-4839-97c1-f90da8e0bc07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547977534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1547977534
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4272730628
Short name T807
Test name
Test status
Simulation time 435688832 ps
CPU time 1.58 seconds
Started Jun 22 04:51:02 PM PDT 24
Finished Jun 22 04:51:04 PM PDT 24
Peak memory 201144 kb
Host smart-bf5ec061-5243-4f34-8bba-90f0eaba077d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272730628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.4272730628
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3773745496
Short name T894
Test name
Test status
Simulation time 2315073834 ps
CPU time 2.25 seconds
Started Jun 22 04:51:03 PM PDT 24
Finished Jun 22 04:51:06 PM PDT 24
Peak memory 201260 kb
Host smart-5f8cb15c-62e5-44bb-93ec-533c3db270ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773745496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3773745496
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2413473089
Short name T857
Test name
Test status
Simulation time 560274295 ps
CPU time 1.73 seconds
Started Jun 22 04:51:03 PM PDT 24
Finished Jun 22 04:51:06 PM PDT 24
Peak memory 201496 kb
Host smart-ed3218c9-8e45-4d6f-8e7e-c20f687c20ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413473089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2413473089
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.872370766
Short name T891
Test name
Test status
Simulation time 662609831 ps
CPU time 1.19 seconds
Started Jun 22 04:51:17 PM PDT 24
Finished Jun 22 04:51:19 PM PDT 24
Peak memory 201192 kb
Host smart-784a49d4-9b22-41d5-9fb2-f43739b2d0df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872370766 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.872370766
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2929202519
Short name T897
Test name
Test status
Simulation time 534559200 ps
CPU time 1.2 seconds
Started Jun 22 04:51:16 PM PDT 24
Finished Jun 22 04:51:18 PM PDT 24
Peak memory 201152 kb
Host smart-ebf485e2-f4ff-42d0-a726-5fde5b360400
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929202519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2929202519
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2845970114
Short name T825
Test name
Test status
Simulation time 447588942 ps
CPU time 0.93 seconds
Started Jun 22 04:51:20 PM PDT 24
Finished Jun 22 04:51:22 PM PDT 24
Peak memory 201120 kb
Host smart-df9715c3-5bac-400c-84c2-407f1e22c4da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845970114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2845970114
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3844721663
Short name T838
Test name
Test status
Simulation time 2057068531 ps
CPU time 2.05 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201120 kb
Host smart-a33d81e3-4d3b-4764-8949-5a6a10c7831a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844721663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3844721663
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2140109964
Short name T97
Test name
Test status
Simulation time 367313196 ps
CPU time 1.94 seconds
Started Jun 22 04:51:14 PM PDT 24
Finished Jun 22 04:51:17 PM PDT 24
Peak memory 201424 kb
Host smart-40096b00-27c9-41ca-9717-a2c7e389cbcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140109964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2140109964
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1605515093
Short name T95
Test name
Test status
Simulation time 4322213303 ps
CPU time 11.51 seconds
Started Jun 22 04:51:16 PM PDT 24
Finished Jun 22 04:51:28 PM PDT 24
Peak memory 201400 kb
Host smart-f9f195e3-441c-4c73-8c0d-69ea3289df3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605515093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1605515093
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3983998150
Short name T872
Test name
Test status
Simulation time 493858886 ps
CPU time 1.39 seconds
Started Jun 22 04:51:20 PM PDT 24
Finished Jun 22 04:51:23 PM PDT 24
Peak memory 201220 kb
Host smart-0852aa1d-5e32-4a1b-a194-1c6f1e1932b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983998150 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3983998150
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2643613359
Short name T134
Test name
Test status
Simulation time 439595088 ps
CPU time 1.3 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 200976 kb
Host smart-6fe46297-3c2c-434c-8cf8-b9f5b570a5ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643613359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2643613359
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.462293273
Short name T800
Test name
Test status
Simulation time 437105569 ps
CPU time 0.85 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 201060 kb
Host smart-86939c5c-604e-4c34-946e-a561735306a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462293273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.462293273
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1805874430
Short name T873
Test name
Test status
Simulation time 5185186943 ps
CPU time 2.39 seconds
Started Jun 22 04:51:19 PM PDT 24
Finished Jun 22 04:51:23 PM PDT 24
Peak memory 201424 kb
Host smart-a81b9b4b-62e1-4092-a3fc-bebc7c0af818
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805874430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1805874430
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1960209457
Short name T855
Test name
Test status
Simulation time 675080085 ps
CPU time 1.45 seconds
Started Jun 22 04:51:16 PM PDT 24
Finished Jun 22 04:51:18 PM PDT 24
Peak memory 201448 kb
Host smart-30a9e9a2-91fb-4c18-b082-cf4956644c27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960209457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1960209457
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1308474781
Short name T836
Test name
Test status
Simulation time 8676846993 ps
CPU time 7.34 seconds
Started Jun 22 04:51:17 PM PDT 24
Finished Jun 22 04:51:25 PM PDT 24
Peak memory 201372 kb
Host smart-4a9f15c6-8e95-4fb8-979a-65d66f84686a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308474781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1308474781
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4141484183
Short name T828
Test name
Test status
Simulation time 371532299 ps
CPU time 1.61 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 201140 kb
Host smart-89fe7e48-03be-4c05-a884-0f448855fc28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141484183 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4141484183
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1905579587
Short name T879
Test name
Test status
Simulation time 308272355 ps
CPU time 1.44 seconds
Started Jun 22 04:51:17 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 201160 kb
Host smart-b5c9a51b-34cd-4ec2-937b-c64714772061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905579587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1905579587
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3338791492
Short name T827
Test name
Test status
Simulation time 385448531 ps
CPU time 1.5 seconds
Started Jun 22 04:51:20 PM PDT 24
Finished Jun 22 04:51:23 PM PDT 24
Peak memory 201052 kb
Host smart-b3d9e4f6-b3fd-438f-842d-557a0a125f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338791492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3338791492
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4269377661
Short name T895
Test name
Test status
Simulation time 2263530451 ps
CPU time 2.95 seconds
Started Jun 22 04:51:14 PM PDT 24
Finished Jun 22 04:51:17 PM PDT 24
Peak memory 201212 kb
Host smart-624e1c5b-c89b-4980-b62a-c5c3cab682d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269377661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.4269377661
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3711245530
Short name T912
Test name
Test status
Simulation time 714140170 ps
CPU time 3.23 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:27 PM PDT 24
Peak memory 217416 kb
Host smart-2cbb1227-f981-4bae-ba0c-447c51b257b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711245530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3711245530
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3556266888
Short name T814
Test name
Test status
Simulation time 409573204 ps
CPU time 1.73 seconds
Started Jun 22 04:51:19 PM PDT 24
Finished Jun 22 04:51:22 PM PDT 24
Peak memory 201220 kb
Host smart-d9318c30-f13c-43c3-ba8b-9982129ebcff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556266888 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3556266888
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1606873241
Short name T892
Test name
Test status
Simulation time 580815525 ps
CPU time 1.24 seconds
Started Jun 22 04:51:26 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201160 kb
Host smart-4455b21f-b1da-4432-a2bc-02e6f1bb5378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606873241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1606873241
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1643205345
Short name T901
Test name
Test status
Simulation time 352020641 ps
CPU time 0.91 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 201152 kb
Host smart-875f026e-b954-4c4f-affd-6c7dc1357667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643205345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1643205345
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.351785700
Short name T889
Test name
Test status
Simulation time 4703905729 ps
CPU time 3.81 seconds
Started Jun 22 04:51:22 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201396 kb
Host smart-0cd0ee2c-b8a5-4ffd-8f0a-acd776ef0160
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351785700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.351785700
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4012942178
Short name T850
Test name
Test status
Simulation time 410904189 ps
CPU time 1.63 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 201420 kb
Host smart-b0bfb237-12b5-4079-a652-b3ae6004b686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012942178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.4012942178
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3763269976
Short name T877
Test name
Test status
Simulation time 4615600624 ps
CPU time 3.46 seconds
Started Jun 22 04:51:17 PM PDT 24
Finished Jun 22 04:51:22 PM PDT 24
Peak memory 201424 kb
Host smart-c7fbf701-ff3c-4df0-bce3-19c2dbf2758b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763269976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3763269976
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1813074483
Short name T108
Test name
Test status
Simulation time 497701168 ps
CPU time 2.09 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201092 kb
Host smart-543511ed-4dc3-423b-9102-7f705b8cb856
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813074483 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1813074483
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2635924549
Short name T846
Test name
Test status
Simulation time 448984741 ps
CPU time 1.06 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 201148 kb
Host smart-35f1261f-86eb-4f77-92be-f45a5ae95f49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635924549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2635924549
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1988072460
Short name T813
Test name
Test status
Simulation time 383097813 ps
CPU time 0.85 seconds
Started Jun 22 04:51:20 PM PDT 24
Finished Jun 22 04:51:22 PM PDT 24
Peak memory 201184 kb
Host smart-bb56f770-e35c-495d-87c7-ac2a90ab2c6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988072460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1988072460
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2578475847
Short name T917
Test name
Test status
Simulation time 4369786615 ps
CPU time 19.73 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:44 PM PDT 24
Peak memory 201356 kb
Host smart-407d8535-6f59-4a98-8878-7c5e6f066c8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578475847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2578475847
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4139851310
Short name T862
Test name
Test status
Simulation time 488174613 ps
CPU time 2.68 seconds
Started Jun 22 04:51:15 PM PDT 24
Finished Jun 22 04:51:18 PM PDT 24
Peak memory 201316 kb
Host smart-0cd4bcd4-e70a-4952-b271-d5aa9a7117f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139851310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4139851310
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3688314334
Short name T81
Test name
Test status
Simulation time 4388738435 ps
CPU time 6.56 seconds
Started Jun 22 04:51:19 PM PDT 24
Finished Jun 22 04:51:27 PM PDT 24
Peak memory 201360 kb
Host smart-de57d8f2-6a04-4def-9a87-f551445e1d81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688314334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3688314334
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1772118612
Short name T840
Test name
Test status
Simulation time 493240045 ps
CPU time 1.99 seconds
Started Jun 22 04:51:19 PM PDT 24
Finished Jun 22 04:51:22 PM PDT 24
Peak memory 201252 kb
Host smart-9a6b0fa7-b0d4-4642-9040-007c4b269288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772118612 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1772118612
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.593669480
Short name T129
Test name
Test status
Simulation time 435236733 ps
CPU time 1.71 seconds
Started Jun 22 04:51:20 PM PDT 24
Finished Jun 22 04:51:24 PM PDT 24
Peak memory 200996 kb
Host smart-60272e50-1c29-4073-ba53-1e0b8b5f1c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593669480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.593669480
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1547616541
Short name T817
Test name
Test status
Simulation time 290663054 ps
CPU time 0.97 seconds
Started Jun 22 04:51:17 PM PDT 24
Finished Jun 22 04:51:19 PM PDT 24
Peak memory 201148 kb
Host smart-9bb01db6-8d39-422d-9fd2-a50f649cda6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547616541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1547616541
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1091504571
Short name T853
Test name
Test status
Simulation time 1979363127 ps
CPU time 2.52 seconds
Started Jun 22 04:51:15 PM PDT 24
Finished Jun 22 04:51:17 PM PDT 24
Peak memory 201156 kb
Host smart-a26c7713-3109-47bc-96df-a2b5c4d1242e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091504571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1091504571
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.628517570
Short name T858
Test name
Test status
Simulation time 618050547 ps
CPU time 2.31 seconds
Started Jun 22 04:51:17 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 209648 kb
Host smart-f760cab8-799a-4d2e-bfe3-88845f118b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628517570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.628517570
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2045060966
Short name T904
Test name
Test status
Simulation time 4572767626 ps
CPU time 4.11 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:23 PM PDT 24
Peak memory 201384 kb
Host smart-513722a9-10a5-4934-82ed-dd3044e67c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045060966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2045060966
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1759746612
Short name T820
Test name
Test status
Simulation time 493015952 ps
CPU time 1.42 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:25 PM PDT 24
Peak memory 201212 kb
Host smart-04c610cf-c70a-4b3c-adb5-ff6fdbcc7662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759746612 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1759746612
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2735548796
Short name T874
Test name
Test status
Simulation time 445595778 ps
CPU time 1.05 seconds
Started Jun 22 04:51:20 PM PDT 24
Finished Jun 22 04:51:23 PM PDT 24
Peak memory 201004 kb
Host smart-3badabbb-14f2-451f-8338-b34c3c39f59c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735548796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2735548796
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.996184225
Short name T854
Test name
Test status
Simulation time 314497388 ps
CPU time 0.85 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 201144 kb
Host smart-e7809781-2df1-42f0-8de6-0c024fa3737a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996184225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.996184225
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1170783046
Short name T865
Test name
Test status
Simulation time 4471912990 ps
CPU time 15.78 seconds
Started Jun 22 04:51:16 PM PDT 24
Finished Jun 22 04:51:32 PM PDT 24
Peak memory 201384 kb
Host smart-bdd324eb-e5e4-4f6f-816e-ab06704df15e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170783046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1170783046
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3255648201
Short name T878
Test name
Test status
Simulation time 392345757 ps
CPU time 3.14 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:22 PM PDT 24
Peak memory 217076 kb
Host smart-42bd704c-da44-4991-a287-4bc6ce981186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255648201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3255648201
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2591508288
Short name T845
Test name
Test status
Simulation time 8520678973 ps
CPU time 6.52 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201360 kb
Host smart-975bc1e6-fad0-4b55-86bc-4e8de449f8ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591508288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2591508288
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3451490187
Short name T884
Test name
Test status
Simulation time 402707709 ps
CPU time 1.44 seconds
Started Jun 22 04:51:24 PM PDT 24
Finished Jun 22 04:51:28 PM PDT 24
Peak memory 201220 kb
Host smart-7d567115-bbad-487c-927c-a4ccaff4bb96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451490187 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3451490187
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1962623927
Short name T898
Test name
Test status
Simulation time 522349369 ps
CPU time 1.81 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201136 kb
Host smart-7aefc15e-186e-4f99-8f36-f326ea25f735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962623927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1962623927
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3322979033
Short name T824
Test name
Test status
Simulation time 335230966 ps
CPU time 1.35 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 201148 kb
Host smart-40a5179c-c9d1-4e97-854f-ba67791c3f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322979033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3322979033
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.34342767
Short name T75
Test name
Test status
Simulation time 4606750311 ps
CPU time 9.77 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:36 PM PDT 24
Peak memory 201448 kb
Host smart-0b2cb3a3-1620-4bb3-b3f0-a1526332baff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34342767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ct
rl_same_csr_outstanding.34342767
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.132936941
Short name T856
Test name
Test status
Simulation time 4837093753 ps
CPU time 4.28 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201408 kb
Host smart-d70325ed-6760-4169-ace2-b7ce254c9dc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132936941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.132936941
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3625954758
Short name T96
Test name
Test status
Simulation time 635872812 ps
CPU time 1.49 seconds
Started Jun 22 04:51:30 PM PDT 24
Finished Jun 22 04:51:32 PM PDT 24
Peak memory 201216 kb
Host smart-0b705e9b-6460-4c16-9ed0-f5f5976af48e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625954758 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3625954758
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1518293992
Short name T140
Test name
Test status
Simulation time 563069708 ps
CPU time 1.33 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201148 kb
Host smart-f119bf57-fb89-4990-8446-9ab81a1b5d2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518293992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1518293992
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3333651034
Short name T863
Test name
Test status
Simulation time 448162199 ps
CPU time 1.3 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201144 kb
Host smart-a02de551-e7ac-426c-8fb5-358bd1957a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333651034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3333651034
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1043115627
Short name T911
Test name
Test status
Simulation time 2898827694 ps
CPU time 2.45 seconds
Started Jun 22 04:51:22 PM PDT 24
Finished Jun 22 04:51:27 PM PDT 24
Peak memory 201448 kb
Host smart-e23a074b-a242-4e02-9953-c1bcbcb87a78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043115627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1043115627
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.194050924
Short name T826
Test name
Test status
Simulation time 391718638 ps
CPU time 1.7 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201628 kb
Host smart-30068432-e01e-4e29-aaca-7aa4900bd655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194050924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.194050924
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1910362238
Short name T346
Test name
Test status
Simulation time 4384397147 ps
CPU time 3.93 seconds
Started Jun 22 04:51:22 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201284 kb
Host smart-6752bde2-b51d-4ce4-9bc3-086cdc83167f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910362238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1910362238
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.428071260
Short name T875
Test name
Test status
Simulation time 573775188 ps
CPU time 1.19 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201364 kb
Host smart-42387e0d-e951-49c9-98df-53e562ee49fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428071260 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.428071260
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2460122212
Short name T849
Test name
Test status
Simulation time 502643413 ps
CPU time 1.01 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:27 PM PDT 24
Peak memory 201156 kb
Host smart-99d97e6c-67ad-4a99-b187-a5825f1fbf8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460122212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2460122212
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1976530664
Short name T805
Test name
Test status
Simulation time 477786592 ps
CPU time 0.93 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201036 kb
Host smart-0ea66604-a41a-46c9-9742-c78dfd5f064c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976530664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1976530664
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.792934758
Short name T905
Test name
Test status
Simulation time 4788493568 ps
CPU time 2.08 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:28 PM PDT 24
Peak memory 201388 kb
Host smart-cef948f5-e882-4907-a0d2-b37458a304f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792934758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.792934758
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3069901011
Short name T84
Test name
Test status
Simulation time 4206414558 ps
CPU time 11.47 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:37 PM PDT 24
Peak memory 201348 kb
Host smart-faa16ded-0c9b-49a1-9521-96f0331b09a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069901011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3069901011
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3799721713
Short name T136
Test name
Test status
Simulation time 1034681299 ps
CPU time 4.65 seconds
Started Jun 22 04:51:11 PM PDT 24
Finished Jun 22 04:51:16 PM PDT 24
Peak memory 201308 kb
Host smart-4823e190-03d7-4c3c-83e9-eb22d7788c8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799721713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3799721713
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1370852677
Short name T881
Test name
Test status
Simulation time 53134698172 ps
CPU time 47.72 seconds
Started Jun 22 04:51:10 PM PDT 24
Finished Jun 22 04:51:59 PM PDT 24
Peak memory 201408 kb
Host smart-554e2b0a-a6b5-4f58-809f-15e6c0c74e3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370852677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1370852677
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2201168041
Short name T821
Test name
Test status
Simulation time 785008248 ps
CPU time 0.84 seconds
Started Jun 22 04:51:04 PM PDT 24
Finished Jun 22 04:51:06 PM PDT 24
Peak memory 200996 kb
Host smart-5073c0fc-d01f-46c1-ac26-a7b38227b6f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201168041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2201168041
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4168786373
Short name T893
Test name
Test status
Simulation time 656826935 ps
CPU time 1.72 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:51:09 PM PDT 24
Peak memory 201224 kb
Host smart-89f90761-84b1-4aad-9662-a41a7fd48b2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168786373 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.4168786373
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.590534176
Short name T816
Test name
Test status
Simulation time 404248116 ps
CPU time 0.82 seconds
Started Jun 22 04:51:03 PM PDT 24
Finished Jun 22 04:51:05 PM PDT 24
Peak memory 201144 kb
Host smart-fcd10325-e925-47fe-9b8c-c402b3838551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590534176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.590534176
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1917403950
Short name T915
Test name
Test status
Simulation time 2657598375 ps
CPU time 10.86 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:51:19 PM PDT 24
Peak memory 201116 kb
Host smart-2d32f731-e033-4a82-8650-71472ef81608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917403950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1917403950
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3156681069
Short name T886
Test name
Test status
Simulation time 508386338 ps
CPU time 3.12 seconds
Started Jun 22 04:51:05 PM PDT 24
Finished Jun 22 04:51:09 PM PDT 24
Peak memory 201412 kb
Host smart-84907110-5dc0-4033-be62-fc00896e5dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156681069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3156681069
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.717735753
Short name T80
Test name
Test status
Simulation time 4195248806 ps
CPU time 11.28 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:13 PM PDT 24
Peak memory 201340 kb
Host smart-30b100b2-5829-427f-860d-26dfa5fa50d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717735753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.717735753
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4245216793
Short name T823
Test name
Test status
Simulation time 483958959 ps
CPU time 1.24 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201128 kb
Host smart-881dc222-f60e-4a28-a059-2db412d41ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245216793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4245216793
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2224973081
Short name T902
Test name
Test status
Simulation time 522610845 ps
CPU time 0.93 seconds
Started Jun 22 04:51:26 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 200992 kb
Host smart-e57d5189-27ca-4797-9e0a-f948d0d7b228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224973081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2224973081
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2004562931
Short name T804
Test name
Test status
Simulation time 416732495 ps
CPU time 1.12 seconds
Started Jun 22 04:51:30 PM PDT 24
Finished Jun 22 04:51:32 PM PDT 24
Peak memory 201136 kb
Host smart-3f73938e-0146-404d-827c-54ecae3980b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004562931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2004562931
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1074314184
Short name T868
Test name
Test status
Simulation time 336330676 ps
CPU time 0.84 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201136 kb
Host smart-a3e2ae8a-972d-4113-918d-5bd6088c3e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074314184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1074314184
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1781183424
Short name T829
Test name
Test status
Simulation time 346198015 ps
CPU time 1.4 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201164 kb
Host smart-60f871df-171e-47fd-9605-70eb26e963c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781183424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1781183424
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1485612857
Short name T839
Test name
Test status
Simulation time 324480092 ps
CPU time 0.76 seconds
Started Jun 22 04:51:28 PM PDT 24
Finished Jun 22 04:51:30 PM PDT 24
Peak memory 201152 kb
Host smart-211ff18f-3b92-4b0d-b469-1e889a2cc89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485612857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1485612857
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3761951287
Short name T832
Test name
Test status
Simulation time 335289084 ps
CPU time 0.8 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201152 kb
Host smart-ea967084-2767-4918-b811-b887eb9a1628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761951287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3761951287
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4078163645
Short name T802
Test name
Test status
Simulation time 392552880 ps
CPU time 0.95 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:28 PM PDT 24
Peak memory 201036 kb
Host smart-30e619a7-a846-4402-a5fe-eade1d9ed43f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078163645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.4078163645
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.808860675
Short name T806
Test name
Test status
Simulation time 521039880 ps
CPU time 0.71 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201124 kb
Host smart-4cd2e75f-091d-4673-b56e-b5ef5acdcad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808860675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.808860675
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4149191265
Short name T864
Test name
Test status
Simulation time 432735156 ps
CPU time 1.13 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201116 kb
Host smart-83abfff0-a546-44d8-b305-d2e99f79a70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149191265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4149191265
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1030666375
Short name T131
Test name
Test status
Simulation time 1126787433 ps
CPU time 3.86 seconds
Started Jun 22 04:51:11 PM PDT 24
Finished Jun 22 04:51:16 PM PDT 24
Peak memory 201144 kb
Host smart-cdedf6db-53fa-472a-aecc-611e61cc2d05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030666375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1030666375
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3275816228
Short name T133
Test name
Test status
Simulation time 23568148871 ps
CPU time 74.14 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:52:22 PM PDT 24
Peak memory 201380 kb
Host smart-cc128022-22fd-4415-a153-3c4ae607a3b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275816228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3275816228
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2514074567
Short name T128
Test name
Test status
Simulation time 1298073136 ps
CPU time 1.46 seconds
Started Jun 22 04:51:10 PM PDT 24
Finished Jun 22 04:51:12 PM PDT 24
Peak memory 201124 kb
Host smart-c4c95ddc-5a46-4fbe-adcb-f0e83f83c7e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514074567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2514074567
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1481694559
Short name T109
Test name
Test status
Simulation time 382812121 ps
CPU time 1.67 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:51:10 PM PDT 24
Peak memory 201220 kb
Host smart-36a505f9-12f6-45b7-85ab-ddbc1a1ed27d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481694559 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1481694559
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2660812289
Short name T867
Test name
Test status
Simulation time 509831232 ps
CPU time 1.12 seconds
Started Jun 22 04:51:11 PM PDT 24
Finished Jun 22 04:51:13 PM PDT 24
Peak memory 201116 kb
Host smart-26b84382-4166-48b8-9ac2-13ccb41da5b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660812289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2660812289
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3779396467
Short name T822
Test name
Test status
Simulation time 327771407 ps
CPU time 1.02 seconds
Started Jun 22 04:51:08 PM PDT 24
Finished Jun 22 04:51:09 PM PDT 24
Peak memory 201152 kb
Host smart-7ec40419-b942-454f-9ad0-86bffbbd7d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779396467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3779396467
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2708868195
Short name T74
Test name
Test status
Simulation time 4268784753 ps
CPU time 10.4 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:51:18 PM PDT 24
Peak memory 201388 kb
Host smart-c7605288-484e-4f08-a551-d6536baf5c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708868195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2708868195
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2396831387
Short name T876
Test name
Test status
Simulation time 368898622 ps
CPU time 2.46 seconds
Started Jun 22 04:51:11 PM PDT 24
Finished Jun 22 04:51:15 PM PDT 24
Peak memory 201412 kb
Host smart-656e07cc-a8e4-4923-ac63-25f33039cbfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396831387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2396831387
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3973638869
Short name T916
Test name
Test status
Simulation time 8165986604 ps
CPU time 12.44 seconds
Started Jun 22 04:51:08 PM PDT 24
Finished Jun 22 04:51:21 PM PDT 24
Peak memory 201320 kb
Host smart-48800966-7013-4074-afcf-82ddcb0875f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973638869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3973638869
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2000622387
Short name T803
Test name
Test status
Simulation time 326494082 ps
CPU time 0.95 seconds
Started Jun 22 04:51:24 PM PDT 24
Finished Jun 22 04:51:28 PM PDT 24
Peak memory 201036 kb
Host smart-e6fdf77a-aac1-40f7-93d7-42748e10c323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000622387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2000622387
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3608760755
Short name T811
Test name
Test status
Simulation time 515116092 ps
CPU time 0.83 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:27 PM PDT 24
Peak memory 201120 kb
Host smart-d40fda99-8b92-4028-a2a0-37e7dfedab93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608760755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3608760755
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.445935686
Short name T808
Test name
Test status
Simulation time 527760256 ps
CPU time 1.03 seconds
Started Jun 22 04:51:26 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201144 kb
Host smart-c633d884-6430-4f6f-8f51-5dfefd5e8931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445935686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.445935686
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4199937791
Short name T819
Test name
Test status
Simulation time 306765675 ps
CPU time 0.82 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201024 kb
Host smart-0c82c3ee-7ab6-4e2f-9ad9-51d02f0844ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199937791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4199937791
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3139761483
Short name T860
Test name
Test status
Simulation time 538776973 ps
CPU time 1.1 seconds
Started Jun 22 04:51:26 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201060 kb
Host smart-5b110d1a-3aee-43ef-b0d6-1a52cf4602b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139761483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3139761483
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3817101449
Short name T818
Test name
Test status
Simulation time 534274930 ps
CPU time 1.2 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201056 kb
Host smart-2c276954-3d34-495d-888b-c73003bd849d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817101449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3817101449
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.224864229
Short name T844
Test name
Test status
Simulation time 328481535 ps
CPU time 0.98 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201140 kb
Host smart-9154b773-a2cf-4182-9839-0544c5dcc7a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224864229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.224864229
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3117721904
Short name T869
Test name
Test status
Simulation time 574893501 ps
CPU time 0.72 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:28 PM PDT 24
Peak memory 201100 kb
Host smart-8c29d29d-c48c-4688-9f3c-0def38b1da3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117721904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3117721904
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1075194188
Short name T852
Test name
Test status
Simulation time 321981684 ps
CPU time 0.98 seconds
Started Jun 22 04:51:26 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 200992 kb
Host smart-b9955863-f6f6-4777-a468-45d78b0b8603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075194188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1075194188
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4277460401
Short name T918
Test name
Test status
Simulation time 424302888 ps
CPU time 1.31 seconds
Started Jun 22 04:51:28 PM PDT 24
Finished Jun 22 04:51:31 PM PDT 24
Peak memory 201144 kb
Host smart-d77896a7-ddb6-4e73-a359-934505d0a514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277460401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.4277460401
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3032140927
Short name T887
Test name
Test status
Simulation time 736372850 ps
CPU time 3.14 seconds
Started Jun 22 04:51:10 PM PDT 24
Finished Jun 22 04:51:15 PM PDT 24
Peak memory 201364 kb
Host smart-aaddd66d-44ba-4f23-b1cb-fa43da3a9be7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032140927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3032140927
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2314788878
Short name T130
Test name
Test status
Simulation time 29971043294 ps
CPU time 20.98 seconds
Started Jun 22 04:51:08 PM PDT 24
Finished Jun 22 04:51:30 PM PDT 24
Peak memory 201356 kb
Host smart-7f7c95d4-dd7c-4947-8b8b-da2586011eee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314788878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2314788878
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4099002864
Short name T125
Test name
Test status
Simulation time 796894544 ps
CPU time 2.44 seconds
Started Jun 22 04:51:11 PM PDT 24
Finished Jun 22 04:51:14 PM PDT 24
Peak memory 201060 kb
Host smart-5ef91a4c-ff92-478a-87a7-9c01671545f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099002864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4099002864
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.706179310
Short name T870
Test name
Test status
Simulation time 479738218 ps
CPU time 1.96 seconds
Started Jun 22 04:51:10 PM PDT 24
Finished Jun 22 04:51:14 PM PDT 24
Peak memory 201116 kb
Host smart-64059e26-929c-4ffb-b3bd-e8581c9af1b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706179310 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.706179310
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3251289538
Short name T851
Test name
Test status
Simulation time 521009593 ps
CPU time 0.99 seconds
Started Jun 22 04:51:13 PM PDT 24
Finished Jun 22 04:51:15 PM PDT 24
Peak memory 201136 kb
Host smart-63a22162-720f-49f0-a274-cc106a548637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251289538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3251289538
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1321186852
Short name T883
Test name
Test status
Simulation time 539359772 ps
CPU time 0.95 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:51:09 PM PDT 24
Peak memory 201152 kb
Host smart-fe4f0ccc-6942-4b22-aea0-320b732c23ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321186852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1321186852
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.493043544
Short name T77
Test name
Test status
Simulation time 2443528995 ps
CPU time 3.35 seconds
Started Jun 22 04:51:11 PM PDT 24
Finished Jun 22 04:51:16 PM PDT 24
Peak memory 201120 kb
Host smart-9a5997c3-c4bd-41ce-a14c-ec9323138d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493043544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.493043544
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3112633956
Short name T88
Test name
Test status
Simulation time 537108356 ps
CPU time 2.01 seconds
Started Jun 22 04:51:09 PM PDT 24
Finished Jun 22 04:51:12 PM PDT 24
Peak memory 201572 kb
Host smart-7e3b4667-6bfc-41d7-be54-0f4d1cb89c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112633956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3112633956
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3535336678
Short name T79
Test name
Test status
Simulation time 4729002596 ps
CPU time 2.92 seconds
Started Jun 22 04:51:06 PM PDT 24
Finished Jun 22 04:51:09 PM PDT 24
Peak memory 201416 kb
Host smart-17d5197b-ac34-4dc3-8e44-0b834a28a2fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535336678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3535336678
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3583278375
Short name T913
Test name
Test status
Simulation time 412359890 ps
CPU time 1.53 seconds
Started Jun 22 04:51:27 PM PDT 24
Finished Jun 22 04:51:30 PM PDT 24
Peak memory 201152 kb
Host smart-181e1e80-70c3-496c-bee2-89625deabacd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583278375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3583278375
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.685284414
Short name T830
Test name
Test status
Simulation time 530326553 ps
CPU time 1 seconds
Started Jun 22 04:51:26 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201144 kb
Host smart-100bc9b4-e46f-4895-acad-a5980800c08e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685284414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.685284414
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1318956050
Short name T815
Test name
Test status
Simulation time 569302059 ps
CPU time 0.84 seconds
Started Jun 22 04:51:26 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201144 kb
Host smart-a8187a0c-fd2f-4094-beac-251803b70770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318956050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1318956050
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.387873616
Short name T848
Test name
Test status
Simulation time 346906769 ps
CPU time 1.02 seconds
Started Jun 22 04:51:23 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201152 kb
Host smart-c78833e6-08dc-47ce-bfb1-6dd064b302b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387873616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.387873616
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.209186377
Short name T809
Test name
Test status
Simulation time 513442485 ps
CPU time 1.75 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201128 kb
Host smart-287f5362-c83e-4efe-901c-f6b6a301c225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209186377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.209186377
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.8756002
Short name T841
Test name
Test status
Simulation time 420536721 ps
CPU time 1.66 seconds
Started Jun 22 04:51:26 PM PDT 24
Finished Jun 22 04:51:30 PM PDT 24
Peak memory 201000 kb
Host smart-7b65220b-f3ee-4b21-b1ca-534b5c1281a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8756002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.8756002
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2029238402
Short name T908
Test name
Test status
Simulation time 433248352 ps
CPU time 0.91 seconds
Started Jun 22 04:51:25 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 201052 kb
Host smart-e19e3e7a-7f49-4ab9-9c78-e11c543a58cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029238402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2029238402
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4169197748
Short name T812
Test name
Test status
Simulation time 324945022 ps
CPU time 1.27 seconds
Started Jun 22 04:51:30 PM PDT 24
Finished Jun 22 04:51:32 PM PDT 24
Peak memory 201132 kb
Host smart-bab32f49-7e11-410e-836c-8fe931a3da19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169197748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4169197748
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.4075090947
Short name T900
Test name
Test status
Simulation time 461960825 ps
CPU time 0.86 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:47 PM PDT 24
Peak memory 201144 kb
Host smart-a8d635f3-b9f8-4fb0-b960-b465a3681fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075090947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.4075090947
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.909694101
Short name T910
Test name
Test status
Simulation time 540689751 ps
CPU time 1.01 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:51:33 PM PDT 24
Peak memory 201124 kb
Host smart-d3435bb6-b00f-4f8b-b11b-26c086bf090a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909694101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.909694101
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3539080101
Short name T896
Test name
Test status
Simulation time 574142798 ps
CPU time 1.48 seconds
Started Jun 22 04:51:09 PM PDT 24
Finished Jun 22 04:51:11 PM PDT 24
Peak memory 201220 kb
Host smart-ef87d553-b018-4acd-88e6-03a7de12b143
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539080101 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3539080101
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3950547588
Short name T138
Test name
Test status
Simulation time 519544292 ps
CPU time 1.18 seconds
Started Jun 22 04:51:17 PM PDT 24
Finished Jun 22 04:51:18 PM PDT 24
Peak memory 201072 kb
Host smart-16596347-dd3d-4f0e-8a30-b16f5bf61d52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950547588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3950547588
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2895084592
Short name T880
Test name
Test status
Simulation time 452183328 ps
CPU time 1.62 seconds
Started Jun 22 04:51:10 PM PDT 24
Finished Jun 22 04:51:13 PM PDT 24
Peak memory 201140 kb
Host smart-bb4633fe-1f17-4ef9-b220-1d0fc0d22533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895084592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2895084592
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4098530151
Short name T906
Test name
Test status
Simulation time 4881070417 ps
CPU time 5.46 seconds
Started Jun 22 04:51:10 PM PDT 24
Finished Jun 22 04:51:17 PM PDT 24
Peak memory 201348 kb
Host smart-fc3b4102-fd45-438e-82b1-90bea5e0d96e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098530151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4098530151
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1663726761
Short name T885
Test name
Test status
Simulation time 489288539 ps
CPU time 2.68 seconds
Started Jun 22 04:51:10 PM PDT 24
Finished Jun 22 04:51:14 PM PDT 24
Peak memory 201272 kb
Host smart-fb2ecb6f-0d66-42ef-bc98-0700fbb4a7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663726761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1663726761
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.372242822
Short name T914
Test name
Test status
Simulation time 4719556895 ps
CPU time 12.51 seconds
Started Jun 22 04:51:13 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201412 kb
Host smart-01e850fd-e255-4ae7-bc08-4bb957f91ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372242822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.372242822
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3907662639
Short name T899
Test name
Test status
Simulation time 434377224 ps
CPU time 1.45 seconds
Started Jun 22 04:51:08 PM PDT 24
Finished Jun 22 04:51:11 PM PDT 24
Peak memory 201236 kb
Host smart-87888d33-0d75-4707-b54f-cf1b4fcc1ce2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907662639 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3907662639
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2450690246
Short name T123
Test name
Test status
Simulation time 327536913 ps
CPU time 1.13 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:51:09 PM PDT 24
Peak memory 201128 kb
Host smart-031e75d0-98e8-454a-aef9-4285a9822dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450690246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2450690246
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3044522402
Short name T888
Test name
Test status
Simulation time 435986710 ps
CPU time 0.86 seconds
Started Jun 22 04:51:10 PM PDT 24
Finished Jun 22 04:51:12 PM PDT 24
Peak memory 201116 kb
Host smart-7fc8bce3-76c0-4c07-bf4d-3476c778d5ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044522402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3044522402
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2510724392
Short name T142
Test name
Test status
Simulation time 2036719079 ps
CPU time 5.44 seconds
Started Jun 22 04:51:13 PM PDT 24
Finished Jun 22 04:51:19 PM PDT 24
Peak memory 201148 kb
Host smart-6673ad8c-baa9-4968-8c71-e569c105afce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510724392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2510724392
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3735139108
Short name T90
Test name
Test status
Simulation time 510474673 ps
CPU time 2.45 seconds
Started Jun 22 04:51:11 PM PDT 24
Finished Jun 22 04:51:14 PM PDT 24
Peak memory 201292 kb
Host smart-b2527847-c46f-4c61-8656-d28e82a9161f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735139108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3735139108
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.374636563
Short name T89
Test name
Test status
Simulation time 8483588924 ps
CPU time 7.05 seconds
Started Jun 22 04:51:08 PM PDT 24
Finished Jun 22 04:51:16 PM PDT 24
Peak memory 201364 kb
Host smart-83e939ed-1908-42ef-9a5b-2e8f622b3b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374636563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.374636563
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.804468733
Short name T847
Test name
Test status
Simulation time 331415925 ps
CPU time 1.14 seconds
Started Jun 22 04:51:08 PM PDT 24
Finished Jun 22 04:51:10 PM PDT 24
Peak memory 201220 kb
Host smart-f6c65383-0c5d-45ce-8c3e-83b912a95dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804468733 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.804468733
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3232912354
Short name T132
Test name
Test status
Simulation time 536944516 ps
CPU time 1.14 seconds
Started Jun 22 04:51:10 PM PDT 24
Finished Jun 22 04:51:13 PM PDT 24
Peak memory 201048 kb
Host smart-28b6d46d-bd43-49b3-9909-268bce094b3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232912354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3232912354
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.280194311
Short name T801
Test name
Test status
Simulation time 438374388 ps
CPU time 1.7 seconds
Started Jun 22 04:51:08 PM PDT 24
Finished Jun 22 04:51:10 PM PDT 24
Peak memory 201320 kb
Host smart-1022a091-3a68-45a5-b452-59a3382a98cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280194311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.280194311
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4264729528
Short name T141
Test name
Test status
Simulation time 4888067068 ps
CPU time 3.84 seconds
Started Jun 22 04:51:13 PM PDT 24
Finished Jun 22 04:51:17 PM PDT 24
Peak memory 201412 kb
Host smart-168c3850-e5ea-45fe-ace9-1aa641f378d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264729528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4264729528
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2622150602
Short name T890
Test name
Test status
Simulation time 487771894 ps
CPU time 2.55 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:51:10 PM PDT 24
Peak memory 209584 kb
Host smart-069d0337-1353-4a3c-b6db-7a72530d1143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622150602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2622150602
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1369819854
Short name T100
Test name
Test status
Simulation time 7701452011 ps
CPU time 11.6 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:51:19 PM PDT 24
Peak memory 201336 kb
Host smart-e521de65-f2c0-4fe4-bdbf-ed053cfa1290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369819854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1369819854
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3997252276
Short name T834
Test name
Test status
Simulation time 456144730 ps
CPU time 1.3 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201220 kb
Host smart-540308c1-1f6b-40b7-8312-18c234f18094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997252276 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3997252276
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3122220517
Short name T831
Test name
Test status
Simulation time 530575856 ps
CPU time 1.07 seconds
Started Jun 22 04:51:15 PM PDT 24
Finished Jun 22 04:51:16 PM PDT 24
Peak memory 201144 kb
Host smart-4b3021c3-83f1-466b-8c77-ddb32e27f121
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122220517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3122220517
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2323786064
Short name T833
Test name
Test status
Simulation time 517393536 ps
CPU time 1.26 seconds
Started Jun 22 04:51:06 PM PDT 24
Finished Jun 22 04:51:08 PM PDT 24
Peak memory 201144 kb
Host smart-2b5cfcf2-5afa-4e79-ad54-aa117d89e0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323786064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2323786064
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1229763686
Short name T139
Test name
Test status
Simulation time 2259095816 ps
CPU time 11.43 seconds
Started Jun 22 04:51:21 PM PDT 24
Finished Jun 22 04:51:34 PM PDT 24
Peak memory 201212 kb
Host smart-07009981-c49c-41f7-8fbb-ec4da0e920fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229763686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1229763686
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1690087485
Short name T93
Test name
Test status
Simulation time 458960460 ps
CPU time 1.99 seconds
Started Jun 22 04:51:14 PM PDT 24
Finished Jun 22 04:51:16 PM PDT 24
Peak memory 201408 kb
Host smart-4dc068d4-16e9-4840-9b7c-d9d7b9af5c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690087485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1690087485
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1052841149
Short name T871
Test name
Test status
Simulation time 4455757326 ps
CPU time 4.19 seconds
Started Jun 22 04:51:12 PM PDT 24
Finished Jun 22 04:51:17 PM PDT 24
Peak memory 201380 kb
Host smart-5f789500-e9e2-4693-9378-8a31e89ec9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052841149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1052841149
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4131154769
Short name T98
Test name
Test status
Simulation time 382289480 ps
CPU time 1.39 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 201112 kb
Host smart-f89b4d97-5817-400d-bc6b-f780f0ed55ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131154769 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.4131154769
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2809706857
Short name T137
Test name
Test status
Simulation time 511529695 ps
CPU time 1.26 seconds
Started Jun 22 04:51:18 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 200956 kb
Host smart-48c1d65a-75a3-4c38-8978-910296960496
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809706857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2809706857
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4277700660
Short name T843
Test name
Test status
Simulation time 411149925 ps
CPU time 0.78 seconds
Started Jun 22 04:51:22 PM PDT 24
Finished Jun 22 04:51:25 PM PDT 24
Peak memory 201120 kb
Host smart-cdfbd54a-02da-4622-8276-a2b29b256997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277700660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4277700660
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2279182113
Short name T835
Test name
Test status
Simulation time 4659388982 ps
CPU time 7.13 seconds
Started Jun 22 04:51:15 PM PDT 24
Finished Jun 22 04:51:22 PM PDT 24
Peak memory 201412 kb
Host smart-d26fc281-53d4-467b-a75f-1281c1190da8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279182113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2279182113
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2812859841
Short name T842
Test name
Test status
Simulation time 525114607 ps
CPU time 3.03 seconds
Started Jun 22 04:51:17 PM PDT 24
Finished Jun 22 04:51:21 PM PDT 24
Peak memory 201452 kb
Host smart-bd59b8fd-c83c-4685-b5f8-f2f8fa3276c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812859841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2812859841
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2115501868
Short name T859
Test name
Test status
Simulation time 4153244690 ps
CPU time 9.93 seconds
Started Jun 22 04:51:16 PM PDT 24
Finished Jun 22 04:51:26 PM PDT 24
Peak memory 201388 kb
Host smart-ddfe7bd4-cf2c-4736-ad02-bb74e1f68133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115501868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2115501868
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2742045001
Short name T637
Test name
Test status
Simulation time 565285794 ps
CPU time 0.75 seconds
Started Jun 22 05:42:48 PM PDT 24
Finished Jun 22 05:42:49 PM PDT 24
Peak memory 202068 kb
Host smart-88db797e-d90e-48cb-bc45-11a5114d91a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742045001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2742045001
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.412947244
Short name T295
Test name
Test status
Simulation time 163177818978 ps
CPU time 97.88 seconds
Started Jun 22 05:42:37 PM PDT 24
Finished Jun 22 05:44:16 PM PDT 24
Peak memory 202284 kb
Host smart-c0892014-2e4e-49bd-abd1-6d09fbfd6a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412947244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.412947244
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.223318892
Short name T566
Test name
Test status
Simulation time 494488045020 ps
CPU time 1131.07 seconds
Started Jun 22 05:42:39 PM PDT 24
Finished Jun 22 06:01:31 PM PDT 24
Peak memory 202472 kb
Host smart-0121dc76-620a-4988-a384-e3e8b361b23e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=223318892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.223318892
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2234928847
Short name T506
Test name
Test status
Simulation time 167896415388 ps
CPU time 365.13 seconds
Started Jun 22 05:42:31 PM PDT 24
Finished Jun 22 05:48:36 PM PDT 24
Peak memory 202248 kb
Host smart-902b8d47-3175-4cb0-ab48-2679765a2f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234928847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2234928847
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3404964220
Short name T772
Test name
Test status
Simulation time 497115887105 ps
CPU time 722.8 seconds
Started Jun 22 05:42:29 PM PDT 24
Finished Jun 22 05:54:32 PM PDT 24
Peak memory 202268 kb
Host smart-be558e90-84b9-42e8-a54d-b55389bd182d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404964220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3404964220
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.96096385
Short name T428
Test name
Test status
Simulation time 193953582512 ps
CPU time 439.8 seconds
Started Jun 22 05:42:38 PM PDT 24
Finished Jun 22 05:49:59 PM PDT 24
Peak memory 202260 kb
Host smart-d7bccc89-8e25-4714-8cd5-b93c230b50ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96096385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ad
c_ctrl_filters_wakeup_fixed.96096385
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2721628902
Short name T659
Test name
Test status
Simulation time 34716914638 ps
CPU time 36.9 seconds
Started Jun 22 05:42:38 PM PDT 24
Finished Jun 22 05:43:15 PM PDT 24
Peak memory 202040 kb
Host smart-65e76335-2808-4091-8259-09564f4ed798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721628902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2721628902
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1689883737
Short name T24
Test name
Test status
Simulation time 3125011105 ps
CPU time 4.05 seconds
Started Jun 22 05:42:37 PM PDT 24
Finished Jun 22 05:42:42 PM PDT 24
Peak memory 202064 kb
Host smart-93ac5aae-b8ea-43e6-864d-b887859fb1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689883737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1689883737
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3269445026
Short name T86
Test name
Test status
Simulation time 3794376692 ps
CPU time 5.39 seconds
Started Jun 22 05:42:46 PM PDT 24
Finished Jun 22 05:42:51 PM PDT 24
Peak memory 217812 kb
Host smart-7f9f17fb-364e-4065-a4ab-859bbfe0bb94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269445026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3269445026
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3469575125
Short name T716
Test name
Test status
Simulation time 5922237135 ps
CPU time 2.43 seconds
Started Jun 22 05:42:31 PM PDT 24
Finished Jun 22 05:42:34 PM PDT 24
Peak memory 201992 kb
Host smart-2093d9ba-7d77-4a8a-aaf2-dc8b5fa49137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469575125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3469575125
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1734089711
Short name T452
Test name
Test status
Simulation time 174949195660 ps
CPU time 773.88 seconds
Started Jun 22 05:42:48 PM PDT 24
Finished Jun 22 05:55:43 PM PDT 24
Peak memory 210924 kb
Host smart-e0202bcc-8f40-443c-907a-98ea54ab66d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734089711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1734089711
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3598006714
Short name T373
Test name
Test status
Simulation time 498767208 ps
CPU time 0.88 seconds
Started Jun 22 05:43:06 PM PDT 24
Finished Jun 22 05:43:08 PM PDT 24
Peak memory 201924 kb
Host smart-2a07bea3-7cda-4d9a-912b-0fb8bc8815c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598006714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3598006714
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3108931267
Short name T198
Test name
Test status
Simulation time 353484003734 ps
CPU time 215.61 seconds
Started Jun 22 05:42:59 PM PDT 24
Finished Jun 22 05:46:35 PM PDT 24
Peak memory 202296 kb
Host smart-fd7dd450-3ada-46cd-be4b-8b51251ac2d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108931267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3108931267
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1402553184
Short name T724
Test name
Test status
Simulation time 186591815405 ps
CPU time 328.38 seconds
Started Jun 22 05:42:59 PM PDT 24
Finished Jun 22 05:48:28 PM PDT 24
Peak memory 202216 kb
Host smart-9297118a-9f3f-4bcd-b0ea-44e530e3fa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402553184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1402553184
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.427950535
Short name T754
Test name
Test status
Simulation time 497105727152 ps
CPU time 1143.47 seconds
Started Jun 22 05:42:44 PM PDT 24
Finished Jun 22 06:01:47 PM PDT 24
Peak memory 202140 kb
Host smart-01c16e63-78af-45bf-a29f-90d60f33188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427950535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.427950535
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2469390977
Short name T704
Test name
Test status
Simulation time 165610005245 ps
CPU time 104.11 seconds
Started Jun 22 05:42:51 PM PDT 24
Finished Jun 22 05:44:35 PM PDT 24
Peak memory 202112 kb
Host smart-954f6090-74a4-492b-8138-f1f991287143
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469390977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2469390977
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1088518752
Short name T292
Test name
Test status
Simulation time 326864282386 ps
CPU time 742.33 seconds
Started Jun 22 05:42:44 PM PDT 24
Finished Jun 22 05:55:06 PM PDT 24
Peak memory 202296 kb
Host smart-a49af359-6574-4bd1-ba11-c18a44e8d42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088518752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1088518752
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3434935091
Short name T377
Test name
Test status
Simulation time 331601714647 ps
CPU time 709.19 seconds
Started Jun 22 05:42:46 PM PDT 24
Finished Jun 22 05:54:35 PM PDT 24
Peak memory 202084 kb
Host smart-8baf4c6d-de9c-4d8e-8af3-5a2ecf47497b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434935091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3434935091
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1996280778
Short name T301
Test name
Test status
Simulation time 526511849628 ps
CPU time 496.18 seconds
Started Jun 22 05:42:51 PM PDT 24
Finished Jun 22 05:51:08 PM PDT 24
Peak memory 202288 kb
Host smart-02c68e63-b410-448a-a411-62f4a8d0af8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996280778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1996280778
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.699052834
Short name T439
Test name
Test status
Simulation time 404964662669 ps
CPU time 51.87 seconds
Started Jun 22 05:42:57 PM PDT 24
Finished Jun 22 05:43:49 PM PDT 24
Peak memory 202356 kb
Host smart-7f7ecc62-809e-4186-8a72-d62cf6915a84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699052834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.699052834
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1403461634
Short name T202
Test name
Test status
Simulation time 129611633988 ps
CPU time 443.08 seconds
Started Jun 22 05:43:03 PM PDT 24
Finished Jun 22 05:50:26 PM PDT 24
Peak memory 202732 kb
Host smart-a2c9a7de-2f58-4af7-aaf8-f17f0684cf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403461634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1403461634
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1946976168
Short name T175
Test name
Test status
Simulation time 23624597194 ps
CPU time 13.78 seconds
Started Jun 22 05:42:59 PM PDT 24
Finished Jun 22 05:43:13 PM PDT 24
Peak memory 202004 kb
Host smart-854d01a1-85cd-475d-acb0-275f82c4b26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946976168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1946976168
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.839901322
Short name T73
Test name
Test status
Simulation time 2956363271 ps
CPU time 3.13 seconds
Started Jun 22 05:42:58 PM PDT 24
Finished Jun 22 05:43:01 PM PDT 24
Peak memory 202052 kb
Host smart-3809804e-e448-4ffa-bce1-a66f77dc3181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839901322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.839901322
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1367859570
Short name T85
Test name
Test status
Simulation time 8053556483 ps
CPU time 9.33 seconds
Started Jun 22 05:43:07 PM PDT 24
Finished Jun 22 05:43:16 PM PDT 24
Peak memory 218788 kb
Host smart-b923fff3-ac33-4ced-a767-e1a796a9952d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367859570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1367859570
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.609738838
Short name T403
Test name
Test status
Simulation time 5806021353 ps
CPU time 12.9 seconds
Started Jun 22 05:42:45 PM PDT 24
Finished Jun 22 05:42:58 PM PDT 24
Peak memory 202272 kb
Host smart-87ed4118-8cb8-4a26-90d7-d9db774b25df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609738838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.609738838
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3473614384
Short name T613
Test name
Test status
Simulation time 100854903041 ps
CPU time 235.49 seconds
Started Jun 22 05:42:59 PM PDT 24
Finished Jun 22 05:46:55 PM PDT 24
Peak memory 218620 kb
Host smart-426f78a3-8bd3-43f9-abad-e72148790ced
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473614384 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3473614384
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2301525829
Short name T191
Test name
Test status
Simulation time 384449477014 ps
CPU time 919.79 seconds
Started Jun 22 05:46:14 PM PDT 24
Finished Jun 22 06:01:34 PM PDT 24
Peak memory 202220 kb
Host smart-fe44426a-3819-4b1d-a4c5-77de53eb49a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301525829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2301525829
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1789385241
Short name T337
Test name
Test status
Simulation time 166091567146 ps
CPU time 362.87 seconds
Started Jun 22 05:46:07 PM PDT 24
Finished Jun 22 05:52:10 PM PDT 24
Peak memory 202304 kb
Host smart-fde647d6-1e14-4d82-b394-e740bbb20159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789385241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1789385241
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3879763117
Short name T774
Test name
Test status
Simulation time 327294356469 ps
CPU time 791.4 seconds
Started Jun 22 05:46:08 PM PDT 24
Finished Jun 22 05:59:19 PM PDT 24
Peak memory 202084 kb
Host smart-574a2bd8-97f4-4669-b7ba-0ace7d4512aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879763117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3879763117
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2994866948
Short name T776
Test name
Test status
Simulation time 330124156986 ps
CPU time 724.34 seconds
Started Jun 22 05:46:06 PM PDT 24
Finished Jun 22 05:58:11 PM PDT 24
Peak memory 202272 kb
Host smart-66b1806a-322a-4c44-98cc-6ba133a3b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994866948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2994866948
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2455990510
Short name T480
Test name
Test status
Simulation time 164536712872 ps
CPU time 381.45 seconds
Started Jun 22 05:46:13 PM PDT 24
Finished Jun 22 05:52:35 PM PDT 24
Peak memory 202160 kb
Host smart-ad3c7c8a-5b0a-4944-965a-ec48b58cd49d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455990510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2455990510
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.492468913
Short name T185
Test name
Test status
Simulation time 548462232693 ps
CPU time 127.86 seconds
Started Jun 22 05:46:07 PM PDT 24
Finished Jun 22 05:48:15 PM PDT 24
Peak memory 202276 kb
Host smart-108f1007-8128-4e5f-bb6e-4c25e66b59d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492468913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.492468913
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3518895908
Short name T560
Test name
Test status
Simulation time 610290137857 ps
CPU time 187.74 seconds
Started Jun 22 05:46:15 PM PDT 24
Finished Jun 22 05:49:23 PM PDT 24
Peak memory 202260 kb
Host smart-eee84b76-b215-470a-a261-f6786acb76f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518895908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3518895908
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2891574482
Short name T789
Test name
Test status
Simulation time 109174208519 ps
CPU time 423.16 seconds
Started Jun 22 05:46:14 PM PDT 24
Finished Jun 22 05:53:18 PM PDT 24
Peak memory 202604 kb
Host smart-45574cdf-b022-4a05-a99a-b9d903794bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891574482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2891574482
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2459662147
Short name T763
Test name
Test status
Simulation time 26113658465 ps
CPU time 11.27 seconds
Started Jun 22 05:46:16 PM PDT 24
Finished Jun 22 05:46:28 PM PDT 24
Peak memory 202060 kb
Host smart-a47d9452-bbc6-4169-985c-88a311dd64e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459662147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2459662147
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3293870237
Short name T646
Test name
Test status
Simulation time 4363067638 ps
CPU time 3.08 seconds
Started Jun 22 05:46:15 PM PDT 24
Finished Jun 22 05:46:18 PM PDT 24
Peak memory 202036 kb
Host smart-0106cbcc-18aa-4aaa-b64c-0c2e19e0a72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293870237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3293870237
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.630518609
Short name T639
Test name
Test status
Simulation time 5948034282 ps
CPU time 15.3 seconds
Started Jun 22 05:46:06 PM PDT 24
Finished Jun 22 05:46:22 PM PDT 24
Peak memory 202056 kb
Host smart-c6360bc3-11ee-4b04-a591-1e3016ebe0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630518609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.630518609
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.673995803
Short name T539
Test name
Test status
Simulation time 500416496753 ps
CPU time 1104.87 seconds
Started Jun 22 05:46:22 PM PDT 24
Finished Jun 22 06:04:48 PM PDT 24
Peak memory 202216 kb
Host smart-739de8cb-9f20-417e-b780-4e5454ced87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673995803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
673995803
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1579198750
Short name T83
Test name
Test status
Simulation time 89095918686 ps
CPU time 57.69 seconds
Started Jun 22 05:46:29 PM PDT 24
Finished Jun 22 05:47:27 PM PDT 24
Peak memory 202412 kb
Host smart-0155a63b-8211-4348-88a9-498e415316cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579198750 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1579198750
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3853339280
Short name T389
Test name
Test status
Simulation time 532278638 ps
CPU time 1.27 seconds
Started Jun 22 05:46:50 PM PDT 24
Finished Jun 22 05:46:52 PM PDT 24
Peak memory 201892 kb
Host smart-dd7f4d4c-d95c-4480-af12-95e3d61543f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853339280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3853339280
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2909178597
Short name T258
Test name
Test status
Simulation time 163201700885 ps
CPU time 106.68 seconds
Started Jun 22 05:46:30 PM PDT 24
Finished Jun 22 05:48:17 PM PDT 24
Peak memory 202220 kb
Host smart-1beaae55-8f58-4cc5-99b3-0b0337e2d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909178597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2909178597
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2135305930
Short name T274
Test name
Test status
Simulation time 325899193616 ps
CPU time 506.68 seconds
Started Jun 22 05:46:24 PM PDT 24
Finished Jun 22 05:54:51 PM PDT 24
Peak memory 202228 kb
Host smart-b342e58c-710e-492d-81d7-e3fec6e5f7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135305930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2135305930
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2358559881
Short name T419
Test name
Test status
Simulation time 321782582004 ps
CPU time 368.56 seconds
Started Jun 22 05:46:24 PM PDT 24
Finished Jun 22 05:52:33 PM PDT 24
Peak memory 202256 kb
Host smart-d1c2970d-f418-4574-9999-c21e23679a03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358559881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2358559881
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.624449533
Short name T460
Test name
Test status
Simulation time 168701816242 ps
CPU time 389.48 seconds
Started Jun 22 05:46:23 PM PDT 24
Finished Jun 22 05:52:53 PM PDT 24
Peak memory 202188 kb
Host smart-63be2717-5057-4fca-9259-6417be9eaee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624449533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.624449533
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2072448538
Short name T365
Test name
Test status
Simulation time 320357281672 ps
CPU time 158.5 seconds
Started Jun 22 05:46:25 PM PDT 24
Finished Jun 22 05:49:04 PM PDT 24
Peak memory 202088 kb
Host smart-560d5111-b140-4eb1-b323-23306c4e8883
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072448538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2072448538
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1883222190
Short name T287
Test name
Test status
Simulation time 179222348557 ps
CPU time 78.28 seconds
Started Jun 22 05:46:28 PM PDT 24
Finished Jun 22 05:47:47 PM PDT 24
Peak memory 202136 kb
Host smart-cf6ac966-7ef9-46a3-8d05-0e4786cfe16c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883222190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1883222190
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1799479045
Short name T498
Test name
Test status
Simulation time 406697315928 ps
CPU time 248.88 seconds
Started Jun 22 05:46:31 PM PDT 24
Finished Jun 22 05:50:41 PM PDT 24
Peak memory 202164 kb
Host smart-b3549e5f-70c6-4761-92be-4a5893c7aceb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799479045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1799479045
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2686052024
Short name T562
Test name
Test status
Simulation time 123787039577 ps
CPU time 406.67 seconds
Started Jun 22 05:46:37 PM PDT 24
Finished Jun 22 05:53:24 PM PDT 24
Peak memory 202496 kb
Host smart-1d76c9c1-08bf-419c-ad1f-f68d0b33903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686052024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2686052024
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3670749398
Short name T681
Test name
Test status
Simulation time 28205580759 ps
CPU time 29.76 seconds
Started Jun 22 05:46:41 PM PDT 24
Finished Jun 22 05:47:12 PM PDT 24
Peak memory 202024 kb
Host smart-2207c6b9-417f-4dff-9d0a-25029bc4dc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670749398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3670749398
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.4217161769
Short name T486
Test name
Test status
Simulation time 3893379364 ps
CPU time 2.32 seconds
Started Jun 22 05:46:29 PM PDT 24
Finished Jun 22 05:46:32 PM PDT 24
Peak memory 202016 kb
Host smart-9b0e15c0-d5b6-4d8b-9284-1df4ae3e1d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217161769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.4217161769
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1710470729
Short name T674
Test name
Test status
Simulation time 5592285222 ps
CPU time 13.4 seconds
Started Jun 22 05:46:25 PM PDT 24
Finished Jun 22 05:46:39 PM PDT 24
Peak memory 201936 kb
Host smart-c8f9506b-e27a-4c47-8494-34fbcc5e4a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710470729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1710470729
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1604168198
Short name T215
Test name
Test status
Simulation time 141392071850 ps
CPU time 680.75 seconds
Started Jun 22 05:46:50 PM PDT 24
Finished Jun 22 05:58:11 PM PDT 24
Peak memory 210688 kb
Host smart-63c1b10b-5baf-4242-a85a-90c4f0fb7d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604168198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1604168198
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2171101022
Short name T554
Test name
Test status
Simulation time 53565256441 ps
CPU time 156.58 seconds
Started Jun 22 05:46:40 PM PDT 24
Finished Jun 22 05:49:17 PM PDT 24
Peak memory 210928 kb
Host smart-8c0c70c1-4af0-4f44-9321-456988599d36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171101022 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2171101022
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2842240376
Short name T447
Test name
Test status
Simulation time 401558905 ps
CPU time 1.11 seconds
Started Jun 22 05:46:57 PM PDT 24
Finished Jun 22 05:46:59 PM PDT 24
Peak memory 201936 kb
Host smart-8900b79c-2ddc-407b-9cd3-5d5a923320dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842240376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2842240376
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3538760747
Short name T644
Test name
Test status
Simulation time 354003865225 ps
CPU time 403.67 seconds
Started Jun 22 05:46:57 PM PDT 24
Finished Jun 22 05:53:42 PM PDT 24
Peak memory 202212 kb
Host smart-d5c11e4e-6501-437b-acaa-cf9746b32acd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538760747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3538760747
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.756505663
Short name T691
Test name
Test status
Simulation time 162425790487 ps
CPU time 374.25 seconds
Started Jun 22 05:46:57 PM PDT 24
Finished Jun 22 05:53:12 PM PDT 24
Peak memory 202304 kb
Host smart-758dcfd0-3dfc-4741-ac11-d49d6574f536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756505663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.756505663
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1397392407
Short name T521
Test name
Test status
Simulation time 164600980522 ps
CPU time 181.37 seconds
Started Jun 22 05:46:50 PM PDT 24
Finished Jun 22 05:49:52 PM PDT 24
Peak memory 202288 kb
Host smart-10ca1d5c-8acc-4aa4-9a46-efe69307acb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397392407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1397392407
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.32851063
Short name T7
Test name
Test status
Simulation time 483428761559 ps
CPU time 1032.33 seconds
Started Jun 22 05:46:48 PM PDT 24
Finished Jun 22 06:04:01 PM PDT 24
Peak memory 202068 kb
Host smart-d3a006d5-5dce-4f65-a3db-6a60d0669155
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=32851063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt
_fixed.32851063
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3497160417
Short name T54
Test name
Test status
Simulation time 489690896000 ps
CPU time 214.68 seconds
Started Jun 22 05:46:50 PM PDT 24
Finished Jun 22 05:50:25 PM PDT 24
Peak memory 202292 kb
Host smart-a9149521-6a23-4f59-a1cb-f108cca693c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497160417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3497160417
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1991182583
Short name T617
Test name
Test status
Simulation time 326130758278 ps
CPU time 61.45 seconds
Started Jun 22 05:46:48 PM PDT 24
Finished Jun 22 05:47:49 PM PDT 24
Peak memory 202196 kb
Host smart-218a7788-ad14-49ee-803b-082af47c7685
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991182583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1991182583
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3906525269
Short name T596
Test name
Test status
Simulation time 350160919263 ps
CPU time 730.23 seconds
Started Jun 22 05:46:49 PM PDT 24
Finished Jun 22 05:59:00 PM PDT 24
Peak memory 202284 kb
Host smart-4234e4cd-7dc7-41e1-af5a-733bf1d7b499
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906525269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3906525269
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2291677525
Short name T465
Test name
Test status
Simulation time 198654272614 ps
CPU time 443.56 seconds
Started Jun 22 05:46:57 PM PDT 24
Finished Jun 22 05:54:21 PM PDT 24
Peak memory 202188 kb
Host smart-488f31bd-af18-40cb-8084-207267df21f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291677525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2291677525
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1418455389
Short name T446
Test name
Test status
Simulation time 33145921723 ps
CPU time 7.8 seconds
Started Jun 22 05:46:55 PM PDT 24
Finished Jun 22 05:47:03 PM PDT 24
Peak memory 202028 kb
Host smart-12a04130-66d9-4867-8891-66598569c6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418455389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1418455389
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3795200830
Short name T29
Test name
Test status
Simulation time 5316759187 ps
CPU time 1.85 seconds
Started Jun 22 05:46:57 PM PDT 24
Finished Jun 22 05:46:59 PM PDT 24
Peak memory 202024 kb
Host smart-ed4eabdb-0d5d-4601-9700-fd95c90d2d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795200830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3795200830
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1766490692
Short name T28
Test name
Test status
Simulation time 6007525753 ps
CPU time 14.42 seconds
Started Jun 22 05:46:50 PM PDT 24
Finished Jun 22 05:47:05 PM PDT 24
Peak memory 201980 kb
Host smart-3aa65104-b8a1-4adf-bd6b-4dc33aad66e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766490692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1766490692
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2280380358
Short name T317
Test name
Test status
Simulation time 492303984348 ps
CPU time 1144.7 seconds
Started Jun 22 05:46:55 PM PDT 24
Finished Jun 22 06:06:00 PM PDT 24
Peak memory 202280 kb
Host smart-b4c1945d-5720-4c36-995c-c97ec6f8d4b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280380358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2280380358
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3163020364
Short name T23
Test name
Test status
Simulation time 24670362256 ps
CPU time 59.27 seconds
Started Jun 22 05:46:56 PM PDT 24
Finished Jun 22 05:47:55 PM PDT 24
Peak memory 202312 kb
Host smart-7a2030b6-f134-41bc-972d-3a5d92e248a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163020364 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3163020364
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.444504425
Short name T648
Test name
Test status
Simulation time 535067110 ps
CPU time 0.96 seconds
Started Jun 22 05:47:12 PM PDT 24
Finished Jun 22 05:47:13 PM PDT 24
Peak memory 201916 kb
Host smart-87ab7ca2-3019-4403-a45d-a09a69cca236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444504425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.444504425
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2167407641
Short name T633
Test name
Test status
Simulation time 514126103982 ps
CPU time 277 seconds
Started Jun 22 05:47:12 PM PDT 24
Finished Jun 22 05:51:49 PM PDT 24
Peak memory 202296 kb
Host smart-c43d9827-b9d1-4dc5-93e1-9af98bbcc11d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167407641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2167407641
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3296219708
Short name T320
Test name
Test status
Simulation time 179969605675 ps
CPU time 374.51 seconds
Started Jun 22 05:47:15 PM PDT 24
Finished Jun 22 05:53:29 PM PDT 24
Peak memory 202448 kb
Host smart-071f2b97-304a-4184-b454-f4ac5111996b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296219708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3296219708
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3893669155
Short name T343
Test name
Test status
Simulation time 328081873317 ps
CPU time 154.51 seconds
Started Jun 22 05:47:06 PM PDT 24
Finished Jun 22 05:49:40 PM PDT 24
Peak memory 202140 kb
Host smart-1890aa2d-4b4e-424d-847e-53bd34150fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893669155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3893669155
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2250614218
Short name T458
Test name
Test status
Simulation time 167211469253 ps
CPU time 185.58 seconds
Started Jun 22 05:47:07 PM PDT 24
Finished Jun 22 05:50:13 PM PDT 24
Peak memory 202176 kb
Host smart-c154c2dc-c61d-4dc4-bafc-0769f0a435f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250614218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2250614218
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1769695160
Short name T625
Test name
Test status
Simulation time 493716789117 ps
CPU time 357.32 seconds
Started Jun 22 05:47:05 PM PDT 24
Finished Jun 22 05:53:03 PM PDT 24
Peak memory 202308 kb
Host smart-58c4e91e-30d6-4e40-849b-63be03fe811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769695160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1769695160
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3283947652
Short name T655
Test name
Test status
Simulation time 325527876027 ps
CPU time 358.13 seconds
Started Jun 22 05:47:05 PM PDT 24
Finished Jun 22 05:53:04 PM PDT 24
Peak memory 202192 kb
Host smart-ea97d4b6-dda2-4bee-815a-782b4a725285
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283947652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3283947652
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2956066926
Short name T218
Test name
Test status
Simulation time 176591123838 ps
CPU time 398.02 seconds
Started Jun 22 05:47:05 PM PDT 24
Finished Jun 22 05:53:43 PM PDT 24
Peak memory 202204 kb
Host smart-1363a5e0-990b-42f8-9bcd-12abaaafebd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956066926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2956066926
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3476407868
Short name T469
Test name
Test status
Simulation time 397464171062 ps
CPU time 748.6 seconds
Started Jun 22 05:47:06 PM PDT 24
Finished Jun 22 05:59:35 PM PDT 24
Peak memory 202272 kb
Host smart-c3028c16-990e-4dda-9d46-63c54b57eb63
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476407868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3476407868
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3329741483
Short name T410
Test name
Test status
Simulation time 129581581765 ps
CPU time 435.26 seconds
Started Jun 22 05:47:14 PM PDT 24
Finished Jun 22 05:54:30 PM PDT 24
Peak memory 202520 kb
Host smart-76cb6301-fe62-4970-9bab-5571eeb46969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329741483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3329741483
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3877917794
Short name T407
Test name
Test status
Simulation time 45982897678 ps
CPU time 26.46 seconds
Started Jun 22 05:47:12 PM PDT 24
Finished Jun 22 05:47:39 PM PDT 24
Peak memory 202036 kb
Host smart-62b6273c-915b-490b-904f-cfa391340429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877917794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3877917794
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2477211897
Short name T495
Test name
Test status
Simulation time 3810148173 ps
CPU time 9.41 seconds
Started Jun 22 05:47:14 PM PDT 24
Finished Jun 22 05:47:24 PM PDT 24
Peak memory 202020 kb
Host smart-c23dfe06-284a-4b4f-a502-d6fbc822f19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477211897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2477211897
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1100421270
Short name T470
Test name
Test status
Simulation time 5879292939 ps
CPU time 3.55 seconds
Started Jun 22 05:46:57 PM PDT 24
Finished Jun 22 05:47:01 PM PDT 24
Peak memory 202012 kb
Host smart-aaccce2c-0179-4f2e-b667-0ca50cf297c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100421270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1100421270
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1995377961
Short name T758
Test name
Test status
Simulation time 40361976181 ps
CPU time 97.01 seconds
Started Jun 22 05:47:13 PM PDT 24
Finished Jun 22 05:48:50 PM PDT 24
Peak memory 210832 kb
Host smart-cb26ac56-79a8-44a5-a430-dba89fc37299
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995377961 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1995377961
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.133993580
Short name T607
Test name
Test status
Simulation time 331588731 ps
CPU time 0.71 seconds
Started Jun 22 05:47:35 PM PDT 24
Finished Jun 22 05:47:36 PM PDT 24
Peak memory 201852 kb
Host smart-f56f46f2-d709-43c8-82ad-934040b94ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133993580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.133993580
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1488380313
Short name T306
Test name
Test status
Simulation time 211460055507 ps
CPU time 113.53 seconds
Started Jun 22 05:47:28 PM PDT 24
Finished Jun 22 05:49:22 PM PDT 24
Peak memory 202188 kb
Host smart-84da6e80-3838-45b0-9f7f-a5f2e598f232
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488380313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1488380313
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.665894051
Short name T161
Test name
Test status
Simulation time 331750948469 ps
CPU time 172.92 seconds
Started Jun 22 05:47:18 PM PDT 24
Finished Jun 22 05:50:11 PM PDT 24
Peak memory 202260 kb
Host smart-f0ccf31e-151a-4beb-ad7c-906716c0c565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665894051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.665894051
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1646180433
Short name T424
Test name
Test status
Simulation time 331269169768 ps
CPU time 807.62 seconds
Started Jun 22 05:47:19 PM PDT 24
Finished Jun 22 06:00:47 PM PDT 24
Peak memory 202168 kb
Host smart-8fe9eb6a-79d2-4979-a99d-0f35f9ac5750
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646180433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1646180433
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2514547383
Short name T635
Test name
Test status
Simulation time 165474959437 ps
CPU time 264.9 seconds
Started Jun 22 05:47:20 PM PDT 24
Finished Jun 22 05:51:45 PM PDT 24
Peak memory 202240 kb
Host smart-d1d969b8-f965-452e-8d84-94fcfbcd6586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514547383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2514547383
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2599020147
Short name T782
Test name
Test status
Simulation time 324095663192 ps
CPU time 148.87 seconds
Started Jun 22 05:47:20 PM PDT 24
Finished Jun 22 05:49:49 PM PDT 24
Peak memory 202316 kb
Host smart-55e6d432-6d1e-4bf5-b653-ba6d60c0e7e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599020147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2599020147
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2166078975
Short name T310
Test name
Test status
Simulation time 194763218400 ps
CPU time 470.89 seconds
Started Jun 22 05:47:22 PM PDT 24
Finished Jun 22 05:55:14 PM PDT 24
Peak memory 202452 kb
Host smart-bc650171-e10b-43dd-a439-f9a9db0e285a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166078975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2166078975
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3369221431
Short name T505
Test name
Test status
Simulation time 207230256774 ps
CPU time 146.1 seconds
Started Jun 22 05:47:29 PM PDT 24
Finished Jun 22 05:49:56 PM PDT 24
Peak memory 202196 kb
Host smart-13ae3523-0f32-4c13-ab5a-f1610459319a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369221431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3369221431
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2859170062
Short name T216
Test name
Test status
Simulation time 61925986121 ps
CPU time 364.47 seconds
Started Jun 22 05:47:27 PM PDT 24
Finished Jun 22 05:53:32 PM PDT 24
Peak memory 202520 kb
Host smart-b3b86677-f9d6-40e9-aeea-d0aa4621be23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859170062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2859170062
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3037581388
Short name T640
Test name
Test status
Simulation time 29784238898 ps
CPU time 27.91 seconds
Started Jun 22 05:47:28 PM PDT 24
Finished Jun 22 05:47:57 PM PDT 24
Peak memory 201960 kb
Host smart-c01210c3-0f76-4d8c-a2e1-e2f3aad1eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037581388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3037581388
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.4219264845
Short name T417
Test name
Test status
Simulation time 2817591944 ps
CPU time 7.22 seconds
Started Jun 22 05:47:27 PM PDT 24
Finished Jun 22 05:47:35 PM PDT 24
Peak memory 202016 kb
Host smart-07f2a8bc-8cf0-4dfb-8ce9-c790aacdb4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219264845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.4219264845
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1644936943
Short name T590
Test name
Test status
Simulation time 6074995584 ps
CPU time 4.48 seconds
Started Jun 22 05:47:20 PM PDT 24
Finished Jun 22 05:47:24 PM PDT 24
Peak memory 201960 kb
Host smart-8cbfa817-dab0-46e8-89a5-dc836e5972d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644936943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1644936943
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2525871421
Short name T42
Test name
Test status
Simulation time 282554101553 ps
CPU time 562.83 seconds
Started Jun 22 05:47:35 PM PDT 24
Finished Jun 22 05:56:59 PM PDT 24
Peak memory 213116 kb
Host smart-e3b7f5ae-58bc-4d02-a825-9852c086bca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525871421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2525871421
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3315785492
Short name T17
Test name
Test status
Simulation time 76416697436 ps
CPU time 258.74 seconds
Started Jun 22 05:47:28 PM PDT 24
Finished Jun 22 05:51:47 PM PDT 24
Peak memory 210908 kb
Host smart-c9c3c9c6-0b27-418c-8405-cbe0ce875bed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315785492 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3315785492
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.660820951
Short name T409
Test name
Test status
Simulation time 343448867 ps
CPU time 0.84 seconds
Started Jun 22 05:47:51 PM PDT 24
Finished Jun 22 05:47:52 PM PDT 24
Peak memory 201908 kb
Host smart-1546ced3-130a-46f9-be21-1698f587f43e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660820951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.660820951
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1070662905
Short name T263
Test name
Test status
Simulation time 334654361129 ps
CPU time 122.94 seconds
Started Jun 22 05:47:42 PM PDT 24
Finished Jun 22 05:49:45 PM PDT 24
Peak memory 202212 kb
Host smart-7779419d-4bc9-4904-a622-e1095409c6e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070662905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1070662905
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1955701326
Short name T170
Test name
Test status
Simulation time 321594024567 ps
CPU time 117.13 seconds
Started Jun 22 05:47:37 PM PDT 24
Finished Jun 22 05:49:35 PM PDT 24
Peak memory 202200 kb
Host smart-416af352-22cc-437f-bd30-1b0a57460613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955701326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1955701326
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.532855348
Short name T787
Test name
Test status
Simulation time 163133954047 ps
CPU time 183.62 seconds
Started Jun 22 05:47:37 PM PDT 24
Finished Jun 22 05:50:41 PM PDT 24
Peak memory 202168 kb
Host smart-c214ab3b-739e-4c79-806f-f5e283d9cad3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=532855348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.532855348
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3297998172
Short name T540
Test name
Test status
Simulation time 157609547517 ps
CPU time 91.97 seconds
Started Jun 22 05:47:35 PM PDT 24
Finished Jun 22 05:49:07 PM PDT 24
Peak memory 202204 kb
Host smart-273e61ff-2b20-435f-82b8-dac154467203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297998172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3297998172
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.711138650
Short name T27
Test name
Test status
Simulation time 332679341030 ps
CPU time 756.06 seconds
Started Jun 22 05:47:36 PM PDT 24
Finished Jun 22 06:00:13 PM PDT 24
Peak memory 202260 kb
Host smart-601204a0-df40-4168-b93e-9843d305ed76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=711138650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.711138650
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2380034703
Short name T666
Test name
Test status
Simulation time 166808426014 ps
CPU time 229.4 seconds
Started Jun 22 05:47:41 PM PDT 24
Finished Jun 22 05:51:31 PM PDT 24
Peak memory 202212 kb
Host smart-9cbd7d07-8e35-4afb-8376-9799d81d6e5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380034703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2380034703
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3813459069
Short name T797
Test name
Test status
Simulation time 400628481103 ps
CPU time 499.38 seconds
Started Jun 22 05:47:43 PM PDT 24
Finished Jun 22 05:56:02 PM PDT 24
Peak memory 202212 kb
Host smart-86a4279d-32f7-4326-8b6d-19d1fc7c30aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813459069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3813459069
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3536818121
Short name T474
Test name
Test status
Simulation time 39150920436 ps
CPU time 96.42 seconds
Started Jun 22 05:47:42 PM PDT 24
Finished Jun 22 05:49:19 PM PDT 24
Peak memory 202040 kb
Host smart-87d265c6-00da-4839-923d-11d77063a46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536818121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3536818121
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.4282782262
Short name T391
Test name
Test status
Simulation time 2934257868 ps
CPU time 7.07 seconds
Started Jun 22 05:47:41 PM PDT 24
Finished Jun 22 05:47:49 PM PDT 24
Peak memory 202036 kb
Host smart-1d2d7e89-ee9c-4bc6-a2c7-fa37d4ecee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282782262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.4282782262
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.716072651
Short name T706
Test name
Test status
Simulation time 5831488096 ps
CPU time 14.33 seconds
Started Jun 22 05:47:36 PM PDT 24
Finished Jun 22 05:47:50 PM PDT 24
Peak memory 202056 kb
Host smart-700e9ce1-189e-4365-8db5-556f518d9395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716072651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.716072651
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1756665721
Short name T496
Test name
Test status
Simulation time 55988989855 ps
CPU time 70.25 seconds
Started Jun 22 05:47:55 PM PDT 24
Finished Jun 22 05:49:05 PM PDT 24
Peak memory 202040 kb
Host smart-64d5e8d7-10ee-48f3-997e-1ab0d61e3d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756665721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1756665721
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1422415593
Short name T729
Test name
Test status
Simulation time 581450571 ps
CPU time 0.79 seconds
Started Jun 22 05:48:14 PM PDT 24
Finished Jun 22 05:48:15 PM PDT 24
Peak memory 201900 kb
Host smart-f5bb0261-d114-42bc-a888-9bf552c7158b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422415593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1422415593
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2743420198
Short name T173
Test name
Test status
Simulation time 347753076098 ps
CPU time 826.51 seconds
Started Jun 22 05:48:06 PM PDT 24
Finished Jun 22 06:01:53 PM PDT 24
Peak memory 202296 kb
Host smart-48fa78eb-9aaf-4027-8039-734703b07e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743420198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2743420198
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.670405332
Short name T153
Test name
Test status
Simulation time 490321412935 ps
CPU time 1091.97 seconds
Started Jun 22 05:47:58 PM PDT 24
Finished Jun 22 06:06:11 PM PDT 24
Peak memory 202232 kb
Host smart-2dbb314b-9631-42c3-9d37-3b5c7e013214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670405332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.670405332
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1482421191
Short name T392
Test name
Test status
Simulation time 321758395932 ps
CPU time 357.51 seconds
Started Jun 22 05:48:11 PM PDT 24
Finished Jun 22 05:54:09 PM PDT 24
Peak memory 202188 kb
Host smart-8be00a21-22de-40ee-b572-82f5a70703dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482421191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1482421191
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1286780951
Short name T781
Test name
Test status
Simulation time 328678773953 ps
CPU time 775.05 seconds
Started Jun 22 05:47:58 PM PDT 24
Finished Jun 22 06:00:53 PM PDT 24
Peak memory 202120 kb
Host smart-df9b468e-6bc9-4c88-adf3-a4ad4abf112f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286780951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1286780951
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1539111792
Short name T324
Test name
Test status
Simulation time 390924502964 ps
CPU time 151.96 seconds
Started Jun 22 05:47:58 PM PDT 24
Finished Jun 22 05:50:31 PM PDT 24
Peak memory 202216 kb
Host smart-dfdbb502-dae3-44e9-9ed8-310b57b7def1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539111792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1539111792
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1844092383
Short name T388
Test name
Test status
Simulation time 388382535049 ps
CPU time 348.34 seconds
Started Jun 22 05:48:09 PM PDT 24
Finished Jun 22 05:53:58 PM PDT 24
Peak memory 202140 kb
Host smart-50f34ea9-e7a4-43ba-b874-5082c485f42f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844092383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1844092383
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3601255976
Short name T563
Test name
Test status
Simulation time 133053401164 ps
CPU time 687.86 seconds
Started Jun 22 05:48:06 PM PDT 24
Finished Jun 22 05:59:35 PM PDT 24
Peak memory 202524 kb
Host smart-7708c408-5c6b-493d-bbd7-0537cad7cfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601255976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3601255976
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.346249977
Short name T367
Test name
Test status
Simulation time 32370313768 ps
CPU time 17.91 seconds
Started Jun 22 05:48:06 PM PDT 24
Finished Jun 22 05:48:25 PM PDT 24
Peak memory 202000 kb
Host smart-b455c891-0dbd-4fdd-b450-6062680f3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346249977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.346249977
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4258358309
Short name T511
Test name
Test status
Simulation time 5448899887 ps
CPU time 3.46 seconds
Started Jun 22 05:48:06 PM PDT 24
Finished Jun 22 05:48:10 PM PDT 24
Peak memory 202032 kb
Host smart-d8df7ac2-0dd1-4ecc-a466-6832189eba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258358309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4258358309
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.846637856
Short name T483
Test name
Test status
Simulation time 5924320790 ps
CPU time 14.19 seconds
Started Jun 22 05:47:52 PM PDT 24
Finished Jun 22 05:48:06 PM PDT 24
Peak memory 202068 kb
Host smart-7a04a14f-5916-4750-ae81-27bf3df1eeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846637856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.846637856
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3570853881
Short name T520
Test name
Test status
Simulation time 180442155228 ps
CPU time 101.01 seconds
Started Jun 22 05:48:06 PM PDT 24
Finished Jun 22 05:49:47 PM PDT 24
Peak memory 210616 kb
Host smart-f5e4d9ac-e35d-40f8-a9a8-c6634849938f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570853881 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3570853881
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3039166147
Short name T376
Test name
Test status
Simulation time 345874018 ps
CPU time 1.32 seconds
Started Jun 22 05:48:32 PM PDT 24
Finished Jun 22 05:48:34 PM PDT 24
Peak memory 201924 kb
Host smart-bb807271-023b-40d2-8038-8113213d82b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039166147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3039166147
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3843971261
Short name T268
Test name
Test status
Simulation time 355621972520 ps
CPU time 368.27 seconds
Started Jun 22 05:48:28 PM PDT 24
Finished Jun 22 05:54:37 PM PDT 24
Peak memory 202288 kb
Host smart-c7f9e80c-1d1a-4998-8476-7edefdfc12ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843971261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3843971261
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3807604178
Short name T668
Test name
Test status
Simulation time 171635145961 ps
CPU time 109.47 seconds
Started Jun 22 05:48:22 PM PDT 24
Finished Jun 22 05:50:12 PM PDT 24
Peak memory 202220 kb
Host smart-d65aba24-2207-43fe-8ea8-5f08ebf4ff25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807604178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3807604178
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1199501501
Short name T558
Test name
Test status
Simulation time 493237180930 ps
CPU time 567.92 seconds
Started Jun 22 05:48:23 PM PDT 24
Finished Jun 22 05:57:51 PM PDT 24
Peak memory 202248 kb
Host smart-9ec1e8da-36a0-47fd-9171-8d7484c8d63c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199501501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1199501501
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2527919448
Short name T618
Test name
Test status
Simulation time 492802855376 ps
CPU time 575.93 seconds
Started Jun 22 05:48:22 PM PDT 24
Finished Jun 22 05:57:58 PM PDT 24
Peak memory 202316 kb
Host smart-3db2fff0-4cb1-4ae8-b234-7081f204e9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527919448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2527919448
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.565351650
Short name T702
Test name
Test status
Simulation time 488291613594 ps
CPU time 1054.76 seconds
Started Jun 22 05:48:22 PM PDT 24
Finished Jun 22 06:05:58 PM PDT 24
Peak memory 202120 kb
Host smart-34ac8aa9-8d3d-4efa-863c-c484d7d84b21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=565351650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.565351650
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.979859601
Short name T32
Test name
Test status
Simulation time 410540286638 ps
CPU time 726.99 seconds
Started Jun 22 05:48:23 PM PDT 24
Finished Jun 22 06:00:30 PM PDT 24
Peak memory 202264 kb
Host smart-66d46b10-925f-4021-85ac-4d3b3007a5da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979859601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.979859601
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3494812265
Short name T737
Test name
Test status
Simulation time 406748760644 ps
CPU time 102.43 seconds
Started Jun 22 05:48:24 PM PDT 24
Finished Jun 22 05:50:07 PM PDT 24
Peak memory 202140 kb
Host smart-7f557290-0764-4026-b8cb-2ae1a3dac1c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494812265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3494812265
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1540390506
Short name T598
Test name
Test status
Simulation time 114406828974 ps
CPU time 309.44 seconds
Started Jun 22 05:48:31 PM PDT 24
Finished Jun 22 05:53:41 PM PDT 24
Peak memory 202464 kb
Host smart-85fffdfa-ba0c-4f16-a699-83210e843803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540390506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1540390506
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3565258311
Short name T679
Test name
Test status
Simulation time 39878542805 ps
CPU time 14.98 seconds
Started Jun 22 05:48:30 PM PDT 24
Finished Jun 22 05:48:46 PM PDT 24
Peak memory 202040 kb
Host smart-84689d52-5b40-4574-b6bc-9ff04fe54a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565258311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3565258311
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2760588164
Short name T436
Test name
Test status
Simulation time 3374732150 ps
CPU time 7.32 seconds
Started Jun 22 05:48:31 PM PDT 24
Finished Jun 22 05:48:39 PM PDT 24
Peak memory 202000 kb
Host smart-7ba9ef55-cfe3-4b74-b0da-b78b9a4a648f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760588164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2760588164
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.210128096
Short name T733
Test name
Test status
Simulation time 5859709653 ps
CPU time 14.46 seconds
Started Jun 22 05:48:16 PM PDT 24
Finished Jun 22 05:48:31 PM PDT 24
Peak memory 202000 kb
Host smart-793f6175-a930-4426-8ff2-a4c9e1e2745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210128096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.210128096
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3149481918
Short name T575
Test name
Test status
Simulation time 34713187201 ps
CPU time 111.19 seconds
Started Jun 22 05:48:33 PM PDT 24
Finished Jun 22 05:50:24 PM PDT 24
Peak memory 210996 kb
Host smart-4d3e5d2c-d3cb-4c31-bf7b-fad8243d6290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149481918 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3149481918
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3572411710
Short name T582
Test name
Test status
Simulation time 397789391 ps
CPU time 1.08 seconds
Started Jun 22 05:48:47 PM PDT 24
Finished Jun 22 05:48:49 PM PDT 24
Peak memory 201908 kb
Host smart-81a1f721-24b0-44b4-aed0-54d9b1d9fd8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572411710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3572411710
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.977209009
Short name T164
Test name
Test status
Simulation time 350967948809 ps
CPU time 83.21 seconds
Started Jun 22 05:48:40 PM PDT 24
Finished Jun 22 05:50:03 PM PDT 24
Peak memory 202268 kb
Host smart-3eedf138-ede8-4276-be4f-7f8a974f6a59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977209009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.977209009
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.184995167
Short name T502
Test name
Test status
Simulation time 164248498106 ps
CPU time 209.07 seconds
Started Jun 22 05:48:44 PM PDT 24
Finished Jun 22 05:52:14 PM PDT 24
Peak memory 202220 kb
Host smart-225451e9-e1bf-4a5c-ab73-85f5c78f81e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184995167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.184995167
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.4253468989
Short name T707
Test name
Test status
Simulation time 329827260945 ps
CPU time 787.43 seconds
Started Jun 22 05:48:38 PM PDT 24
Finished Jun 22 06:01:46 PM PDT 24
Peak memory 202196 kb
Host smart-2c23cb98-32a0-4f26-a53c-35f94923b4b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253468989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.4253468989
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2767092187
Short name T9
Test name
Test status
Simulation time 165874880977 ps
CPU time 103.99 seconds
Started Jun 22 05:48:30 PM PDT 24
Finished Jun 22 05:50:15 PM PDT 24
Peak memory 202236 kb
Host smart-47bb513f-cd3b-4a00-b14f-dab980e4614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767092187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2767092187
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.130402012
Short name T393
Test name
Test status
Simulation time 164599307860 ps
CPU time 91.32 seconds
Started Jun 22 05:48:32 PM PDT 24
Finished Jun 22 05:50:04 PM PDT 24
Peak memory 202164 kb
Host smart-5e038696-8eff-40f7-ae3a-b0f24c9ff4bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=130402012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.130402012
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2901755613
Short name T735
Test name
Test status
Simulation time 173083650961 ps
CPU time 398.49 seconds
Started Jun 22 05:48:38 PM PDT 24
Finished Jun 22 05:55:17 PM PDT 24
Peak memory 202164 kb
Host smart-e272ab8c-0aa4-4d56-8291-eee6183c7274
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901755613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2901755613
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1264940601
Short name T517
Test name
Test status
Simulation time 393090526715 ps
CPU time 832.23 seconds
Started Jun 22 05:48:40 PM PDT 24
Finished Jun 22 06:02:33 PM PDT 24
Peak memory 202260 kb
Host smart-e1eec694-0f62-4b88-adee-43a20b15443b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264940601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1264940601
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2069630578
Short name T775
Test name
Test status
Simulation time 90972445711 ps
CPU time 488.2 seconds
Started Jun 22 05:48:41 PM PDT 24
Finished Jun 22 05:56:49 PM PDT 24
Peak memory 202568 kb
Host smart-c7d08565-c54d-418c-975d-67d52e89707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069630578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2069630578
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.171772612
Short name T441
Test name
Test status
Simulation time 25470895890 ps
CPU time 16.77 seconds
Started Jun 22 05:48:38 PM PDT 24
Finished Jun 22 05:48:55 PM PDT 24
Peak memory 202064 kb
Host smart-bf100e09-929c-4c98-835d-5da97ac66125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171772612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.171772612
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2745708749
Short name T192
Test name
Test status
Simulation time 4680708177 ps
CPU time 3.69 seconds
Started Jun 22 05:48:37 PM PDT 24
Finished Jun 22 05:48:41 PM PDT 24
Peak memory 202044 kb
Host smart-6f3b0c04-e38d-45ff-be4f-9cff3ca63fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745708749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2745708749
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3985209125
Short name T751
Test name
Test status
Simulation time 6090276378 ps
CPU time 1.54 seconds
Started Jun 22 05:48:29 PM PDT 24
Finished Jun 22 05:48:31 PM PDT 24
Peak memory 202260 kb
Host smart-eeea0128-ee0d-41fb-abbb-00513aee3b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985209125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3985209125
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3102463941
Short name T779
Test name
Test status
Simulation time 142536967176 ps
CPU time 447.21 seconds
Started Jun 22 05:48:47 PM PDT 24
Finished Jun 22 05:56:14 PM PDT 24
Peak memory 202456 kb
Host smart-eb3bbbaa-9a1b-4f1a-9713-133cc791661f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102463941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3102463941
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3740645102
Short name T597
Test name
Test status
Simulation time 548946957 ps
CPU time 0.95 seconds
Started Jun 22 05:49:06 PM PDT 24
Finished Jun 22 05:49:07 PM PDT 24
Peak memory 202160 kb
Host smart-0ea924ee-268f-49be-b6c1-9ac24ff99176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740645102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3740645102
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.581998738
Short name T225
Test name
Test status
Simulation time 568424724511 ps
CPU time 267.96 seconds
Started Jun 22 05:49:04 PM PDT 24
Finished Jun 22 05:53:33 PM PDT 24
Peak memory 202196 kb
Host smart-2554bdf5-88ca-45d7-bfb4-c39de1ccba3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581998738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.581998738
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.590901051
Short name T453
Test name
Test status
Simulation time 362985844818 ps
CPU time 217.8 seconds
Started Jun 22 05:48:57 PM PDT 24
Finished Jun 22 05:52:35 PM PDT 24
Peak memory 202224 kb
Host smart-d1f3fd69-8e23-4d31-83c9-64de738f73dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590901051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.590901051
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2550727658
Short name T275
Test name
Test status
Simulation time 492245336167 ps
CPU time 316.76 seconds
Started Jun 22 05:49:04 PM PDT 24
Finished Jun 22 05:54:22 PM PDT 24
Peak memory 202196 kb
Host smart-ae4850a4-8876-4407-80e5-e0dad83ef9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550727658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2550727658
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.626327432
Short name T641
Test name
Test status
Simulation time 162621983987 ps
CPU time 106.99 seconds
Started Jun 22 05:49:04 PM PDT 24
Finished Jun 22 05:50:52 PM PDT 24
Peak memory 202148 kb
Host smart-a9b23e85-1d9a-41e2-b30c-bef56ae4466b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=626327432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.626327432
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1940726286
Short name T749
Test name
Test status
Simulation time 494111706313 ps
CPU time 617.99 seconds
Started Jun 22 05:48:57 PM PDT 24
Finished Jun 22 05:59:15 PM PDT 24
Peak memory 202156 kb
Host smart-0f94fa8c-8cfa-4065-8813-d489882be6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940726286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1940726286
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2750074558
Short name T786
Test name
Test status
Simulation time 330316313828 ps
CPU time 355.27 seconds
Started Jun 22 05:48:58 PM PDT 24
Finished Jun 22 05:54:53 PM PDT 24
Peak memory 202192 kb
Host smart-c901b376-ff6f-4f6d-8c94-c33ed06df90b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750074558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2750074558
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1119070196
Short name T475
Test name
Test status
Simulation time 197088991345 ps
CPU time 386.05 seconds
Started Jun 22 05:48:56 PM PDT 24
Finished Jun 22 05:55:23 PM PDT 24
Peak memory 202276 kb
Host smart-9d826b9e-dfd4-4d73-b71f-15214f75d733
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119070196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1119070196
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4181628005
Short name T550
Test name
Test status
Simulation time 112892820598 ps
CPU time 447.38 seconds
Started Jun 22 05:48:56 PM PDT 24
Finished Jun 22 05:56:24 PM PDT 24
Peak memory 202556 kb
Host smart-556e1a45-78da-4a56-b15d-ed61dd10cb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181628005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4181628005
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2178879598
Short name T685
Test name
Test status
Simulation time 33002745135 ps
CPU time 22.41 seconds
Started Jun 22 05:48:56 PM PDT 24
Finished Jun 22 05:49:19 PM PDT 24
Peak memory 202052 kb
Host smart-94f24f1d-2b58-43cc-affc-9147969b380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178879598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2178879598
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2178041128
Short name T432
Test name
Test status
Simulation time 4510004325 ps
CPU time 10.96 seconds
Started Jun 22 05:49:03 PM PDT 24
Finished Jun 22 05:49:15 PM PDT 24
Peak memory 202004 kb
Host smart-04e9b4ab-bb09-42c1-949a-a9761fb31678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178041128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2178041128
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2135157324
Short name T375
Test name
Test status
Simulation time 6010907143 ps
CPU time 7.34 seconds
Started Jun 22 05:48:48 PM PDT 24
Finished Jun 22 05:48:55 PM PDT 24
Peak memory 201932 kb
Host smart-ec6edb25-00fb-4075-b2d4-1b650bd70cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135157324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2135157324
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.145590040
Short name T62
Test name
Test status
Simulation time 12388671361 ps
CPU time 8.47 seconds
Started Jun 22 05:49:04 PM PDT 24
Finished Jun 22 05:49:13 PM PDT 24
Peak memory 202268 kb
Host smart-79d007b6-68b0-42da-be68-749269a37483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145590040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
145590040
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1030358704
Short name T48
Test name
Test status
Simulation time 232172612847 ps
CPU time 223.29 seconds
Started Jun 22 05:49:04 PM PDT 24
Finished Jun 22 05:52:48 PM PDT 24
Peak memory 211012 kb
Host smart-b45ff2df-0d33-4229-9e89-3d6b71eb1a7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030358704 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1030358704
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2729130411
Short name T174
Test name
Test status
Simulation time 376187984 ps
CPU time 1.07 seconds
Started Jun 22 05:43:37 PM PDT 24
Finished Jun 22 05:43:39 PM PDT 24
Peak memory 201916 kb
Host smart-922cc1b3-85c2-4f6b-8d59-62f2268f8a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729130411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2729130411
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2024031267
Short name T230
Test name
Test status
Simulation time 339151598967 ps
CPU time 827.73 seconds
Started Jun 22 05:43:14 PM PDT 24
Finished Jun 22 05:57:03 PM PDT 24
Peak memory 202160 kb
Host smart-0008159b-d7df-4568-98c2-1fe8aabe8748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024031267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2024031267
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3749347597
Short name T485
Test name
Test status
Simulation time 160802966450 ps
CPU time 371.8 seconds
Started Jun 22 05:43:06 PM PDT 24
Finished Jun 22 05:49:19 PM PDT 24
Peak memory 202196 kb
Host smart-9adb4d11-0653-403d-a7db-5648803ebc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749347597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3749347597
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2907824245
Short name T315
Test name
Test status
Simulation time 493255171218 ps
CPU time 150.94 seconds
Started Jun 22 05:43:05 PM PDT 24
Finished Jun 22 05:45:37 PM PDT 24
Peak memory 202188 kb
Host smart-b4468dce-d9a7-400c-9d03-d876e43d34b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907824245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2907824245
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.780866081
Short name T397
Test name
Test status
Simulation time 328146151765 ps
CPU time 812.14 seconds
Started Jun 22 05:43:07 PM PDT 24
Finished Jun 22 05:56:39 PM PDT 24
Peak memory 202228 kb
Host smart-5cfc1be0-ed6b-4908-8780-9015daf7d0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780866081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.780866081
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2271183793
Short name T493
Test name
Test status
Simulation time 485343435236 ps
CPU time 366.93 seconds
Started Jun 22 05:43:08 PM PDT 24
Finished Jun 22 05:49:15 PM PDT 24
Peak memory 202256 kb
Host smart-e9cd1ea5-9bbf-472a-b7a0-db9de7bae5a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271183793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2271183793
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2683216121
Short name T190
Test name
Test status
Simulation time 344971384395 ps
CPU time 96.64 seconds
Started Jun 22 05:43:07 PM PDT 24
Finished Jun 22 05:44:44 PM PDT 24
Peak memory 202268 kb
Host smart-a36f2f51-a1e6-4c96-8042-8a17ab503982
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683216121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2683216121
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2750724272
Short name T565
Test name
Test status
Simulation time 204531357903 ps
CPU time 482.12 seconds
Started Jun 22 05:43:15 PM PDT 24
Finished Jun 22 05:51:18 PM PDT 24
Peak memory 202200 kb
Host smart-8c897aae-2d40-4043-b3dd-42890f9bd4aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750724272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2750724272
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2244967094
Short name T516
Test name
Test status
Simulation time 71199320642 ps
CPU time 417.59 seconds
Started Jun 22 05:43:31 PM PDT 24
Finished Jun 22 05:50:29 PM PDT 24
Peak memory 202492 kb
Host smart-4edd374a-a3d0-4f61-a52c-f5e7a6228582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244967094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2244967094
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3749109180
Short name T194
Test name
Test status
Simulation time 30789445770 ps
CPU time 20.67 seconds
Started Jun 22 05:43:21 PM PDT 24
Finished Jun 22 05:43:42 PM PDT 24
Peak memory 202040 kb
Host smart-ebca40eb-af05-4cf7-b86e-729f4c952b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749109180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3749109180
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2150180782
Short name T116
Test name
Test status
Simulation time 3546154257 ps
CPU time 4.4 seconds
Started Jun 22 05:43:23 PM PDT 24
Finished Jun 22 05:43:27 PM PDT 24
Peak memory 202064 kb
Host smart-ef53b167-83d6-40dc-9289-1159ad08f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150180782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2150180782
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2272671872
Short name T608
Test name
Test status
Simulation time 6029447705 ps
CPU time 7.8 seconds
Started Jun 22 05:43:06 PM PDT 24
Finished Jun 22 05:43:14 PM PDT 24
Peak memory 201980 kb
Host smart-c06f5ce3-85f3-4174-a745-e01dc5475976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272671872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2272671872
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.499421445
Short name T82
Test name
Test status
Simulation time 395919045829 ps
CPU time 712.69 seconds
Started Jun 22 05:43:31 PM PDT 24
Finished Jun 22 05:55:24 PM PDT 24
Peak memory 210840 kb
Host smart-68050bfb-b114-47a6-a1ee-59f1e9c25209
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499421445 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.499421445
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3150693221
Short name T193
Test name
Test status
Simulation time 464885062 ps
CPU time 1.63 seconds
Started Jun 22 05:49:25 PM PDT 24
Finished Jun 22 05:49:27 PM PDT 24
Peak memory 201924 kb
Host smart-342c31b0-6de5-4c97-86ad-f54ea7053588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150693221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3150693221
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4072615164
Short name T690
Test name
Test status
Simulation time 560806335551 ps
CPU time 1338.65 seconds
Started Jun 22 05:49:11 PM PDT 24
Finished Jun 22 06:11:30 PM PDT 24
Peak memory 202164 kb
Host smart-387f4127-1cfd-4f18-83a9-7158339b4437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072615164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4072615164
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2214836784
Short name T443
Test name
Test status
Simulation time 334062756577 ps
CPU time 422.1 seconds
Started Jun 22 05:49:12 PM PDT 24
Finished Jun 22 05:56:15 PM PDT 24
Peak memory 202252 kb
Host smart-f4b0a48e-09c5-4907-a780-30866adf8bfa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214836784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2214836784
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2484686246
Short name T479
Test name
Test status
Simulation time 163535567030 ps
CPU time 345.64 seconds
Started Jun 22 05:49:05 PM PDT 24
Finished Jun 22 05:54:51 PM PDT 24
Peak memory 202168 kb
Host smart-aba2a577-87da-4c4a-b3a8-4132519ebdb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484686246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2484686246
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.465082371
Short name T289
Test name
Test status
Simulation time 348113048003 ps
CPU time 755.07 seconds
Started Jun 22 05:49:13 PM PDT 24
Finished Jun 22 06:01:48 PM PDT 24
Peak memory 202200 kb
Host smart-07e92590-6710-438e-b13d-9b2cf916e82a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465082371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.465082371
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.41462409
Short name T380
Test name
Test status
Simulation time 414481258625 ps
CPU time 58.37 seconds
Started Jun 22 05:49:13 PM PDT 24
Finished Jun 22 05:50:12 PM PDT 24
Peak memory 202196 kb
Host smart-ae7eeb71-a982-4083-b7ea-74dcf7ea31a5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41462409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.a
dc_ctrl_filters_wakeup_fixed.41462409
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2947040678
Short name T63
Test name
Test status
Simulation time 80937891622 ps
CPU time 414.18 seconds
Started Jun 22 05:49:23 PM PDT 24
Finished Jun 22 05:56:18 PM PDT 24
Peak memory 202572 kb
Host smart-97f0c7d0-d975-417d-bca1-1b43f91796a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947040678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2947040678
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1377934039
Short name T677
Test name
Test status
Simulation time 39022935650 ps
CPU time 18.69 seconds
Started Jun 22 05:49:25 PM PDT 24
Finished Jun 22 05:49:44 PM PDT 24
Peak memory 202040 kb
Host smart-80e29e29-b824-4b6f-88f3-790f8488e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377934039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1377934039
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2217599183
Short name T705
Test name
Test status
Simulation time 4701876290 ps
CPU time 3.88 seconds
Started Jun 22 05:49:17 PM PDT 24
Finished Jun 22 05:49:22 PM PDT 24
Peak memory 202004 kb
Host smart-84a05801-3c58-4819-aef4-765efb9a9873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217599183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2217599183
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.37009485
Short name T379
Test name
Test status
Simulation time 5765921292 ps
CPU time 9.17 seconds
Started Jun 22 05:49:03 PM PDT 24
Finished Jun 22 05:49:13 PM PDT 24
Peak memory 202024 kb
Host smart-c506db19-9e7b-4215-81cb-16b66f6e5c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37009485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.37009485
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.996451155
Short name T44
Test name
Test status
Simulation time 33044817770 ps
CPU time 69.58 seconds
Started Jun 22 05:49:27 PM PDT 24
Finished Jun 22 05:50:37 PM PDT 24
Peak memory 210524 kb
Host smart-bb19be51-f104-442e-b288-e617e1ad4544
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996451155 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.996451155
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1019784435
Short name T708
Test name
Test status
Simulation time 531059318 ps
CPU time 0.7 seconds
Started Jun 22 05:49:46 PM PDT 24
Finished Jun 22 05:49:47 PM PDT 24
Peak memory 201924 kb
Host smart-a06fef8c-86ac-4557-9052-c179c073482c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019784435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1019784435
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3239820909
Short name T574
Test name
Test status
Simulation time 407136843305 ps
CPU time 282.79 seconds
Started Jun 22 05:49:30 PM PDT 24
Finished Jun 22 05:54:13 PM PDT 24
Peak memory 202216 kb
Host smart-94bbf116-5e29-4b4d-880d-f127c04e93c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239820909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3239820909
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3354083174
Short name T155
Test name
Test status
Simulation time 325289953984 ps
CPU time 774.73 seconds
Started Jun 22 05:49:36 PM PDT 24
Finished Jun 22 06:02:31 PM PDT 24
Peak memory 202200 kb
Host smart-d60684de-a6db-422a-88ff-c3d42e836c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354083174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3354083174
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3135568530
Short name T473
Test name
Test status
Simulation time 489005580116 ps
CPU time 318.55 seconds
Started Jun 22 05:49:27 PM PDT 24
Finished Jun 22 05:54:46 PM PDT 24
Peak memory 202188 kb
Host smart-f3c33eac-bf3b-4811-bfdd-7a667bcfa8e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135568530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3135568530
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2928902865
Short name T326
Test name
Test status
Simulation time 485019446193 ps
CPU time 841.39 seconds
Started Jun 22 05:49:25 PM PDT 24
Finished Jun 22 06:03:27 PM PDT 24
Peak memory 202280 kb
Host smart-72429135-322b-4a87-9de9-8c8730f55bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928902865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2928902865
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.401664996
Short name T595
Test name
Test status
Simulation time 498043607200 ps
CPU time 1197.82 seconds
Started Jun 22 05:49:27 PM PDT 24
Finished Jun 22 06:09:26 PM PDT 24
Peak memory 202168 kb
Host smart-31f061ff-0913-47fb-800b-8266b473c304
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=401664996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.401664996
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3945438783
Short name T656
Test name
Test status
Simulation time 430897649721 ps
CPU time 1011.95 seconds
Started Jun 22 05:49:29 PM PDT 24
Finished Jun 22 06:06:22 PM PDT 24
Peak memory 202452 kb
Host smart-53408f21-35b3-4c37-9b57-aece004f5a6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945438783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3945438783
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.745572340
Short name T416
Test name
Test status
Simulation time 205016325933 ps
CPU time 122.41 seconds
Started Jun 22 05:49:30 PM PDT 24
Finished Jun 22 05:51:33 PM PDT 24
Peak memory 202176 kb
Host smart-71b71ee4-ce3f-45b6-9092-a75edcb37a13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745572340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.745572340
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.518878241
Short name T667
Test name
Test status
Simulation time 136718088412 ps
CPU time 469.74 seconds
Started Jun 22 05:49:36 PM PDT 24
Finished Jun 22 05:57:27 PM PDT 24
Peak memory 202572 kb
Host smart-7bcebe90-bc10-4938-b7dc-0597544a5ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518878241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.518878241
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1638491048
Short name T548
Test name
Test status
Simulation time 37376463223 ps
CPU time 15.49 seconds
Started Jun 22 05:49:37 PM PDT 24
Finished Jun 22 05:49:53 PM PDT 24
Peak memory 202028 kb
Host smart-a93ea7c4-65cc-422f-9ff8-54e57b352e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638491048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1638491048
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2156023199
Short name T798
Test name
Test status
Simulation time 3649158513 ps
CPU time 5.13 seconds
Started Jun 22 05:49:37 PM PDT 24
Finished Jun 22 05:49:42 PM PDT 24
Peak memory 202000 kb
Host smart-c986d109-d161-48e7-9f41-aabccf7e1927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156023199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2156023199
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1352807630
Short name T727
Test name
Test status
Simulation time 5648323105 ps
CPU time 12.56 seconds
Started Jun 22 05:49:23 PM PDT 24
Finished Jun 22 05:49:36 PM PDT 24
Peak memory 202020 kb
Host smart-77ef65fc-43de-4370-b432-a18131a87370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352807630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1352807630
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2526203342
Short name T760
Test name
Test status
Simulation time 114856066371 ps
CPU time 38.26 seconds
Started Jun 22 05:49:39 PM PDT 24
Finished Jun 22 05:50:17 PM PDT 24
Peak memory 210540 kb
Host smart-1b3cb501-b07c-4274-b9fa-c9734b37dc5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526203342 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2526203342
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4195126985
Short name T425
Test name
Test status
Simulation time 319973146 ps
CPU time 1.36 seconds
Started Jun 22 05:50:01 PM PDT 24
Finished Jun 22 05:50:03 PM PDT 24
Peak memory 201936 kb
Host smart-219a4106-e620-4708-8d42-3138905ef931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195126985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4195126985
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1715888573
Short name T231
Test name
Test status
Simulation time 484323852545 ps
CPU time 209.44 seconds
Started Jun 22 05:49:52 PM PDT 24
Finished Jun 22 05:53:22 PM PDT 24
Peak memory 202188 kb
Host smart-60f7bae7-8cb5-4a9b-af57-83279b733e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715888573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1715888573
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3294405913
Short name T420
Test name
Test status
Simulation time 498191605568 ps
CPU time 116.05 seconds
Started Jun 22 05:49:52 PM PDT 24
Finished Jun 22 05:51:49 PM PDT 24
Peak memory 202180 kb
Host smart-9d9129d2-884a-4ee7-8a42-4673f1cec14f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294405913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3294405913
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.669697815
Short name T302
Test name
Test status
Simulation time 338124024687 ps
CPU time 414.69 seconds
Started Jun 22 05:49:44 PM PDT 24
Finished Jun 22 05:56:39 PM PDT 24
Peak memory 202196 kb
Host smart-1bbebafb-028c-4c56-a140-82806d7f2974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669697815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.669697815
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2669119543
Short name T604
Test name
Test status
Simulation time 493860847582 ps
CPU time 597.24 seconds
Started Jun 22 05:49:45 PM PDT 24
Finished Jun 22 05:59:43 PM PDT 24
Peak memory 202276 kb
Host smart-76834827-c22d-4d64-be30-9fd915c6be6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669119543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2669119543
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.245696233
Short name T264
Test name
Test status
Simulation time 514132354060 ps
CPU time 599.49 seconds
Started Jun 22 05:49:52 PM PDT 24
Finished Jun 22 05:59:52 PM PDT 24
Peak memory 202256 kb
Host smart-bc4da6dd-231c-4840-83b6-7dd8aae27e5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245696233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.245696233
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2805800858
Short name T796
Test name
Test status
Simulation time 613875239259 ps
CPU time 1265.31 seconds
Started Jun 22 05:49:52 PM PDT 24
Finished Jun 22 06:10:58 PM PDT 24
Peak memory 202256 kb
Host smart-201e1263-4ebc-4fcb-b1c7-af5ab16e3d06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805800858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2805800858
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2600407461
Short name T650
Test name
Test status
Simulation time 99229823410 ps
CPU time 327.7 seconds
Started Jun 22 05:50:01 PM PDT 24
Finished Jun 22 05:55:29 PM PDT 24
Peak memory 202588 kb
Host smart-f68ce156-e9fc-4bed-a4cc-f7b1a66a9523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600407461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2600407461
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1206644019
Short name T382
Test name
Test status
Simulation time 30395309551 ps
CPU time 14.93 seconds
Started Jun 22 05:49:52 PM PDT 24
Finished Jun 22 05:50:07 PM PDT 24
Peak memory 202040 kb
Host smart-b04dd594-38f2-45f8-aa1e-8a0b6317e5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206644019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1206644019
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.101117669
Short name T415
Test name
Test status
Simulation time 3794124896 ps
CPU time 9.87 seconds
Started Jun 22 05:49:52 PM PDT 24
Finished Jun 22 05:50:02 PM PDT 24
Peak memory 202060 kb
Host smart-a5758c59-82a3-42be-8147-008802097f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101117669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.101117669
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.709973913
Short name T664
Test name
Test status
Simulation time 5837658018 ps
CPU time 3.88 seconds
Started Jun 22 05:49:44 PM PDT 24
Finished Jun 22 05:49:48 PM PDT 24
Peak memory 202036 kb
Host smart-cfab5e2a-204f-4fc7-9e6e-0ade62fac3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709973913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.709973913
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1973643539
Short name T689
Test name
Test status
Simulation time 219929947988 ps
CPU time 202.83 seconds
Started Jun 22 05:50:01 PM PDT 24
Finished Jun 22 05:53:25 PM PDT 24
Peak memory 202212 kb
Host smart-c8692bb0-f2fe-4a8f-baf3-00fc435a56c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973643539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1973643539
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.768092343
Short name T104
Test name
Test status
Simulation time 59023547160 ps
CPU time 113.79 seconds
Started Jun 22 05:50:02 PM PDT 24
Finished Jun 22 05:51:56 PM PDT 24
Peak memory 210536 kb
Host smart-bad9a682-bc1c-4d17-9723-32ba1ff78cc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768092343 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.768092343
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.622350531
Short name T195
Test name
Test status
Simulation time 521224298 ps
CPU time 1.68 seconds
Started Jun 22 05:50:17 PM PDT 24
Finished Jun 22 05:50:19 PM PDT 24
Peak memory 201880 kb
Host smart-1749de9b-e839-4382-b63e-8eb92d3890ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622350531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.622350531
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1641799273
Short name T182
Test name
Test status
Simulation time 346057721438 ps
CPU time 156.74 seconds
Started Jun 22 05:50:07 PM PDT 24
Finished Jun 22 05:52:44 PM PDT 24
Peak memory 202216 kb
Host smart-09590411-0087-4836-b0f4-c3c90dbcd144
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641799273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1641799273
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.4052242903
Short name T700
Test name
Test status
Simulation time 320237100856 ps
CPU time 207.34 seconds
Started Jun 22 05:50:00 PM PDT 24
Finished Jun 22 05:53:28 PM PDT 24
Peak memory 202224 kb
Host smart-0356d910-a2ce-4528-b19f-2f585f96e2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052242903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.4052242903
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3618641604
Short name T553
Test name
Test status
Simulation time 168801418093 ps
CPU time 355.32 seconds
Started Jun 22 05:50:00 PM PDT 24
Finished Jun 22 05:55:56 PM PDT 24
Peak memory 202400 kb
Host smart-f46aebfc-4b5e-4fad-b916-6625ddf20911
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618641604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3618641604
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.443379430
Short name T158
Test name
Test status
Simulation time 165310379957 ps
CPU time 99.79 seconds
Started Jun 22 05:50:01 PM PDT 24
Finished Jun 22 05:51:41 PM PDT 24
Peak memory 202248 kb
Host smart-3cd79d43-7f09-4c32-9b53-e39e86f13af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443379430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.443379430
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1287955807
Short name T795
Test name
Test status
Simulation time 159475839860 ps
CPU time 130.43 seconds
Started Jun 22 05:50:02 PM PDT 24
Finished Jun 22 05:52:12 PM PDT 24
Peak memory 202196 kb
Host smart-318856d3-3f52-4032-b3b7-dd7d714b31cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287955807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1287955807
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2591110550
Short name T314
Test name
Test status
Simulation time 496906296214 ps
CPU time 559.84 seconds
Started Jun 22 05:50:03 PM PDT 24
Finished Jun 22 05:59:24 PM PDT 24
Peak memory 202272 kb
Host smart-db580595-c4dd-4cb6-95ad-f9bb89390277
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591110550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2591110550
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1569488396
Short name T793
Test name
Test status
Simulation time 419420908291 ps
CPU time 895.78 seconds
Started Jun 22 05:50:07 PM PDT 24
Finished Jun 22 06:05:03 PM PDT 24
Peak memory 202196 kb
Host smart-c5020507-7772-44dc-9446-a56ad81bae48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569488396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1569488396
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1480731982
Short name T65
Test name
Test status
Simulation time 85563005004 ps
CPU time 425.71 seconds
Started Jun 22 05:50:17 PM PDT 24
Finished Jun 22 05:57:23 PM PDT 24
Peak memory 202604 kb
Host smart-63e53e2e-980f-45bf-8f36-2523739dab34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480731982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1480731982
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2235142413
Short name T176
Test name
Test status
Simulation time 27012576883 ps
CPU time 63.23 seconds
Started Jun 22 05:50:16 PM PDT 24
Finished Jun 22 05:51:20 PM PDT 24
Peak memory 201964 kb
Host smart-166603a0-d382-45c3-b656-024c4f4e35de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235142413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2235142413
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3804499381
Short name T477
Test name
Test status
Simulation time 3465755078 ps
CPU time 2.67 seconds
Started Jun 22 05:50:09 PM PDT 24
Finished Jun 22 05:50:12 PM PDT 24
Peak memory 201988 kb
Host smart-e8219fe4-7f97-410e-bf01-a12d6d2804b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804499381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3804499381
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1048009709
Short name T610
Test name
Test status
Simulation time 6049082961 ps
CPU time 8.15 seconds
Started Jun 22 05:50:01 PM PDT 24
Finished Jun 22 05:50:09 PM PDT 24
Peak memory 201996 kb
Host smart-ea934fe2-cf3a-40b1-8cd5-ed3a66541262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048009709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1048009709
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2169445559
Short name T790
Test name
Test status
Simulation time 173702998912 ps
CPU time 201.08 seconds
Started Jun 22 05:50:20 PM PDT 24
Finished Jun 22 05:53:41 PM PDT 24
Peak memory 202284 kb
Host smart-92fca25a-4342-4240-a704-364900355f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169445559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2169445559
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2816685822
Short name T518
Test name
Test status
Simulation time 95448660368 ps
CPU time 187.82 seconds
Started Jun 22 05:50:16 PM PDT 24
Finished Jun 22 05:53:25 PM PDT 24
Peak memory 210844 kb
Host smart-2e42d2e1-5dc1-433f-a106-9322a0d539d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816685822 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2816685822
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2620909983
Short name T4
Test name
Test status
Simulation time 411007296 ps
CPU time 1.22 seconds
Started Jun 22 05:50:32 PM PDT 24
Finished Jun 22 05:50:33 PM PDT 24
Peak memory 201920 kb
Host smart-38d32cda-9204-4b4c-b36a-0d3590aec674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620909983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2620909983
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2650332958
Short name T229
Test name
Test status
Simulation time 371840800443 ps
CPU time 821.48 seconds
Started Jun 22 05:50:23 PM PDT 24
Finished Jun 22 06:04:05 PM PDT 24
Peak memory 202196 kb
Host smart-e2167880-a840-4fca-89c3-5b6ab75b1e1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650332958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2650332958
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.510792471
Short name T279
Test name
Test status
Simulation time 168160591627 ps
CPU time 185.67 seconds
Started Jun 22 05:50:23 PM PDT 24
Finished Jun 22 05:53:29 PM PDT 24
Peak memory 202344 kb
Host smart-d5986fa1-ab0c-4966-81b1-bbec9307cf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510792471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.510792471
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2028895269
Short name T683
Test name
Test status
Simulation time 492822085391 ps
CPU time 1233.2 seconds
Started Jun 22 05:50:23 PM PDT 24
Finished Jun 22 06:10:57 PM PDT 24
Peak memory 202224 kb
Host smart-280aea25-8f1c-4db0-b0ca-62e46220d904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028895269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2028895269
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3189518167
Short name T156
Test name
Test status
Simulation time 162076476742 ps
CPU time 85.53 seconds
Started Jun 22 05:50:24 PM PDT 24
Finished Jun 22 05:51:50 PM PDT 24
Peak memory 202172 kb
Host smart-48ec2af0-c1e5-4627-8421-8d95ae53442f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189518167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3189518167
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.350471608
Short name T303
Test name
Test status
Simulation time 492247903259 ps
CPU time 570.03 seconds
Started Jun 22 05:50:27 PM PDT 24
Finished Jun 22 05:59:58 PM PDT 24
Peak memory 202296 kb
Host smart-26b6974b-c42f-4664-92bd-4f02e3e2f9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350471608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.350471608
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1386334314
Short name T593
Test name
Test status
Simulation time 489299055511 ps
CPU time 280.27 seconds
Started Jun 22 05:50:24 PM PDT 24
Finished Jun 22 05:55:05 PM PDT 24
Peak memory 202276 kb
Host smart-52230d05-940a-40a1-b06d-7c81346a1315
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386334314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1386334314
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1820270255
Short name T181
Test name
Test status
Simulation time 523372542899 ps
CPU time 104.97 seconds
Started Jun 22 05:50:25 PM PDT 24
Finished Jun 22 05:52:10 PM PDT 24
Peak memory 202180 kb
Host smart-994765a0-0b9c-4cbe-a930-2d7e572cf58a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820270255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1820270255
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1286252337
Short name T686
Test name
Test status
Simulation time 389747239962 ps
CPU time 411.42 seconds
Started Jun 22 05:50:24 PM PDT 24
Finished Jun 22 05:57:16 PM PDT 24
Peak memory 202192 kb
Host smart-e4766624-1713-41a0-883d-aef297977606
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286252337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1286252337
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3455123183
Short name T53
Test name
Test status
Simulation time 71151097246 ps
CPU time 282.22 seconds
Started Jun 22 05:50:31 PM PDT 24
Finished Jun 22 05:55:14 PM PDT 24
Peak memory 202604 kb
Host smart-c4698149-b459-4d78-a939-7b25edba7974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455123183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3455123183
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.482891201
Short name T551
Test name
Test status
Simulation time 42025821005 ps
CPU time 49.28 seconds
Started Jun 22 05:50:31 PM PDT 24
Finished Jun 22 05:51:21 PM PDT 24
Peak memory 202032 kb
Host smart-b9970fc8-c9f1-45f1-b7e8-84bbf560ffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482891201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.482891201
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.575286212
Short name T678
Test name
Test status
Simulation time 3685579254 ps
CPU time 4.52 seconds
Started Jun 22 05:50:31 PM PDT 24
Finished Jun 22 05:50:35 PM PDT 24
Peak memory 202000 kb
Host smart-0881b1f2-aef1-49ed-868e-3f7f430faf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575286212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.575286212
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.605896765
Short name T31
Test name
Test status
Simulation time 5716462157 ps
CPU time 3.69 seconds
Started Jun 22 05:50:22 PM PDT 24
Finished Jun 22 05:50:26 PM PDT 24
Peak memory 202040 kb
Host smart-94f9ee45-7fb9-4d64-b7af-0899a02e3849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605896765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.605896765
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3753549928
Short name T107
Test name
Test status
Simulation time 336043640391 ps
CPU time 229.21 seconds
Started Jun 22 05:50:32 PM PDT 24
Finished Jun 22 05:54:21 PM PDT 24
Peak memory 218456 kb
Host smart-ab70903a-1eb9-4e0c-b130-9ea6c1954994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753549928 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3753549928
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3260977763
Short name T368
Test name
Test status
Simulation time 315475298 ps
CPU time 1.02 seconds
Started Jun 22 05:50:53 PM PDT 24
Finished Jun 22 05:50:54 PM PDT 24
Peak memory 201916 kb
Host smart-0de3e36e-fdc7-477d-a887-2ccbf65e30e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260977763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3260977763
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1301981987
Short name T344
Test name
Test status
Simulation time 522956669176 ps
CPU time 922.24 seconds
Started Jun 22 05:50:39 PM PDT 24
Finished Jun 22 06:06:02 PM PDT 24
Peak memory 202208 kb
Host smart-a2141f1f-427b-4bf6-862c-bbe187909b7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301981987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1301981987
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3865101160
Short name T730
Test name
Test status
Simulation time 162944583658 ps
CPU time 88.02 seconds
Started Jun 22 05:50:43 PM PDT 24
Finished Jun 22 05:52:11 PM PDT 24
Peak memory 202200 kb
Host smart-1924db45-16cf-4477-b463-fcda7e9416a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865101160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3865101160
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3940000611
Short name T38
Test name
Test status
Simulation time 162547425559 ps
CPU time 357.93 seconds
Started Jun 22 05:50:38 PM PDT 24
Finished Jun 22 05:56:37 PM PDT 24
Peak memory 202212 kb
Host smart-60fbe369-92d8-4556-b805-e775a07a6cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940000611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3940000611
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3317872637
Short name T463
Test name
Test status
Simulation time 504174319365 ps
CPU time 841.33 seconds
Started Jun 22 05:50:38 PM PDT 24
Finished Jun 22 06:04:40 PM PDT 24
Peak memory 202188 kb
Host smart-100267d2-777d-4450-bf36-a18fc96eca1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317872637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3317872637
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3321503172
Short name T119
Test name
Test status
Simulation time 488879614635 ps
CPU time 276.21 seconds
Started Jun 22 05:50:38 PM PDT 24
Finished Jun 22 05:55:15 PM PDT 24
Peak memory 202196 kb
Host smart-7ae49176-dfb5-47c2-887f-646960b7c546
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321503172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3321503172
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1640078388
Short name T37
Test name
Test status
Simulation time 279559021614 ps
CPU time 158.52 seconds
Started Jun 22 05:50:38 PM PDT 24
Finished Jun 22 05:53:18 PM PDT 24
Peak memory 202204 kb
Host smart-e25c069a-b944-4c54-889f-d38f3b5a1881
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640078388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1640078388
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.4224729603
Short name T628
Test name
Test status
Simulation time 211528539208 ps
CPU time 480.52 seconds
Started Jun 22 05:50:37 PM PDT 24
Finished Jun 22 05:58:38 PM PDT 24
Peak memory 202180 kb
Host smart-420ec2e0-15d8-42a6-a6a1-641c7d75f2ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224729603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.4224729603
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4035063040
Short name T69
Test name
Test status
Simulation time 140318670811 ps
CPU time 451.09 seconds
Started Jun 22 05:50:48 PM PDT 24
Finished Jun 22 05:58:19 PM PDT 24
Peak memory 202492 kb
Host smart-c6c534eb-6f19-4ebb-b331-4a5b7b6f3af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035063040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4035063040
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.327583901
Short name T429
Test name
Test status
Simulation time 33699961475 ps
CPU time 18.43 seconds
Started Jun 22 05:50:40 PM PDT 24
Finished Jun 22 05:50:59 PM PDT 24
Peak memory 202036 kb
Host smart-2e311577-6879-4258-85bf-d1adaeb604ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327583901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.327583901
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3547655466
Short name T528
Test name
Test status
Simulation time 2944614051 ps
CPU time 7.72 seconds
Started Jun 22 05:50:41 PM PDT 24
Finished Jun 22 05:50:49 PM PDT 24
Peak memory 202016 kb
Host smart-cbdb7487-85a9-408e-a1e8-50fb00d0eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547655466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3547655466
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1047976266
Short name T451
Test name
Test status
Simulation time 6113527403 ps
CPU time 4.46 seconds
Started Jun 22 05:50:32 PM PDT 24
Finished Jun 22 05:50:37 PM PDT 24
Peak memory 202048 kb
Host smart-41bfa91d-db1f-4277-ab6b-da204c6e5ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047976266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1047976266
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1442680455
Short name T794
Test name
Test status
Simulation time 191716608841 ps
CPU time 80.01 seconds
Started Jun 22 05:50:46 PM PDT 24
Finished Jun 22 05:52:06 PM PDT 24
Peak memory 202156 kb
Host smart-9269af55-77c9-4c5c-b91f-3944ed01bd92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442680455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1442680455
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1045768596
Short name T45
Test name
Test status
Simulation time 175622245452 ps
CPU time 155.95 seconds
Started Jun 22 05:50:47 PM PDT 24
Finished Jun 22 05:53:23 PM PDT 24
Peak memory 210828 kb
Host smart-64af7323-3e68-43a2-aab0-aef235745489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045768596 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1045768596
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.704400609
Short name T383
Test name
Test status
Simulation time 467402943 ps
CPU time 1.74 seconds
Started Jun 22 05:51:04 PM PDT 24
Finished Jun 22 05:51:06 PM PDT 24
Peak memory 201916 kb
Host smart-d75f4a7c-7ce1-4b5b-8c30-23f4ef65b0cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704400609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.704400609
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1488287290
Short name T2
Test name
Test status
Simulation time 200904522980 ps
CPU time 242.21 seconds
Started Jun 22 05:50:58 PM PDT 24
Finished Jun 22 05:55:00 PM PDT 24
Peak memory 202216 kb
Host smart-4f0859ca-be28-4000-a459-84904f2964fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488287290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1488287290
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.364853563
Short name T240
Test name
Test status
Simulation time 169655563042 ps
CPU time 366.3 seconds
Started Jun 22 05:50:57 PM PDT 24
Finished Jun 22 05:57:04 PM PDT 24
Peak memory 202188 kb
Host smart-1f169ea0-9c58-4539-ad5d-c3b3491f191c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364853563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.364853563
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2544060822
Short name T394
Test name
Test status
Simulation time 493507478229 ps
CPU time 259.56 seconds
Started Jun 22 05:50:47 PM PDT 24
Finished Jun 22 05:55:07 PM PDT 24
Peak memory 202152 kb
Host smart-94049ad9-691e-41ed-8a24-d609b472a05e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544060822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2544060822
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2076378864
Short name T338
Test name
Test status
Simulation time 169441417418 ps
CPU time 403.16 seconds
Started Jun 22 05:50:47 PM PDT 24
Finished Jun 22 05:57:31 PM PDT 24
Peak memory 202308 kb
Host smart-a2547fd6-c61c-424a-aca0-fe5e6a108be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076378864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2076378864
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3276088415
Short name T449
Test name
Test status
Simulation time 165477468584 ps
CPU time 51.06 seconds
Started Jun 22 05:50:47 PM PDT 24
Finished Jun 22 05:51:39 PM PDT 24
Peak memory 202196 kb
Host smart-8f2e65b1-70e6-4ea4-8b02-9b8fd39d090a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276088415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3276088415
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3423534882
Short name T726
Test name
Test status
Simulation time 466510415267 ps
CPU time 456.09 seconds
Started Jun 22 05:50:55 PM PDT 24
Finished Jun 22 05:58:31 PM PDT 24
Peak memory 202232 kb
Host smart-a6aa5d4e-99da-4991-8a49-3d846b25ae98
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423534882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3423534882
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1482031203
Short name T400
Test name
Test status
Simulation time 398412782210 ps
CPU time 544.29 seconds
Started Jun 22 05:50:55 PM PDT 24
Finished Jun 22 06:00:00 PM PDT 24
Peak memory 202152 kb
Host smart-de1f44b3-78d7-4a5e-9774-caa0e8e0c20b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482031203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1482031203
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.358140760
Short name T785
Test name
Test status
Simulation time 85966205597 ps
CPU time 293.6 seconds
Started Jun 22 05:50:53 PM PDT 24
Finished Jun 22 05:55:46 PM PDT 24
Peak memory 202596 kb
Host smart-33c6b09f-f0e3-4158-845f-63f68adee66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358140760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.358140760
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3887494559
Short name T481
Test name
Test status
Simulation time 40782074077 ps
CPU time 14.48 seconds
Started Jun 22 05:50:56 PM PDT 24
Finished Jun 22 05:51:11 PM PDT 24
Peak memory 202040 kb
Host smart-71a291cc-5992-4d2f-8c4f-1e46e1011392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887494559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3887494559
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4056137139
Short name T356
Test name
Test status
Simulation time 3167432147 ps
CPU time 8.24 seconds
Started Jun 22 05:50:55 PM PDT 24
Finished Jun 22 05:51:04 PM PDT 24
Peak memory 202064 kb
Host smart-de301d92-f6a0-4f36-9e5c-fe1cc197f559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056137139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4056137139
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1990144053
Short name T390
Test name
Test status
Simulation time 5677348733 ps
CPU time 5.07 seconds
Started Jun 22 05:50:48 PM PDT 24
Finished Jun 22 05:50:53 PM PDT 24
Peak memory 201996 kb
Host smart-969dbd69-9d82-423d-bdd2-757892e9905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990144053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1990144053
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3543589618
Short name T319
Test name
Test status
Simulation time 330175318682 ps
CPU time 208.52 seconds
Started Jun 22 05:50:53 PM PDT 24
Finished Jun 22 05:54:22 PM PDT 24
Peak memory 202192 kb
Host smart-183ece7e-fa3a-445c-a13b-6446b8df2405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543589618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3543589618
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1750929905
Short name T621
Test name
Test status
Simulation time 237594691148 ps
CPU time 650.17 seconds
Started Jun 22 05:50:56 PM PDT 24
Finished Jun 22 06:01:46 PM PDT 24
Peak memory 210884 kb
Host smart-f69be69f-fc33-46b3-8add-456f0a4a2699
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750929905 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1750929905
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2853155125
Short name T461
Test name
Test status
Simulation time 493281803 ps
CPU time 0.79 seconds
Started Jun 22 05:51:11 PM PDT 24
Finished Jun 22 05:51:13 PM PDT 24
Peak memory 201852 kb
Host smart-7cf263e4-0c82-4f39-a54c-6e91571b0a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853155125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2853155125
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3779504830
Short name T290
Test name
Test status
Simulation time 161062684907 ps
CPU time 180.72 seconds
Started Jun 22 05:51:02 PM PDT 24
Finished Jun 22 05:54:03 PM PDT 24
Peak memory 202208 kb
Host smart-2bcbed40-d4ef-4608-a5b1-8932a976dc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779504830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3779504830
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2377961955
Short name T663
Test name
Test status
Simulation time 324449117782 ps
CPU time 140.79 seconds
Started Jun 22 05:51:04 PM PDT 24
Finished Jun 22 05:53:25 PM PDT 24
Peak memory 202252 kb
Host smart-80b83efe-7da4-4ee4-a301-ef1904aaef12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377961955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2377961955
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2772615096
Short name T488
Test name
Test status
Simulation time 494359121934 ps
CPU time 265.5 seconds
Started Jun 22 05:51:03 PM PDT 24
Finished Jun 22 05:55:29 PM PDT 24
Peak memory 202208 kb
Host smart-2531d404-07b7-4ebe-9545-cb3eae4353de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772615096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2772615096
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2318164522
Short name T620
Test name
Test status
Simulation time 164594655516 ps
CPU time 339.93 seconds
Started Jun 22 05:51:04 PM PDT 24
Finished Jun 22 05:56:45 PM PDT 24
Peak memory 202176 kb
Host smart-65599a2d-6232-41ad-b94b-d8b644f08236
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318164522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2318164522
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2585715660
Short name T791
Test name
Test status
Simulation time 583178148984 ps
CPU time 79.6 seconds
Started Jun 22 05:51:05 PM PDT 24
Finished Jun 22 05:52:25 PM PDT 24
Peak memory 202176 kb
Host smart-f66fc062-9c27-44c0-ad6a-4cd71e7ed012
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585715660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2585715660
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2047993776
Short name T352
Test name
Test status
Simulation time 96849449065 ps
CPU time 287.32 seconds
Started Jun 22 05:51:12 PM PDT 24
Finished Jun 22 05:55:59 PM PDT 24
Peak memory 202584 kb
Host smart-97fdaf84-ef12-4902-b6ec-ccb8e40e45b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047993776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2047993776
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1841069389
Short name T527
Test name
Test status
Simulation time 39270628945 ps
CPU time 85.51 seconds
Started Jun 22 05:51:12 PM PDT 24
Finished Jun 22 05:52:38 PM PDT 24
Peak memory 202012 kb
Host smart-b28d067d-3ff9-4f3a-a58a-e9df3070e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841069389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1841069389
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.978791044
Short name T411
Test name
Test status
Simulation time 3152155227 ps
CPU time 4.21 seconds
Started Jun 22 05:51:12 PM PDT 24
Finished Jun 22 05:51:16 PM PDT 24
Peak memory 202064 kb
Host smart-ecc635ed-4733-49a2-9b31-fd92eba6e382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978791044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.978791044
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3582332496
Short name T359
Test name
Test status
Simulation time 5728229445 ps
CPU time 7.15 seconds
Started Jun 22 05:51:04 PM PDT 24
Finished Jun 22 05:51:11 PM PDT 24
Peak memory 202036 kb
Host smart-fdcb4c3a-70a5-415d-890f-73709e218240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582332496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3582332496
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3108378221
Short name T242
Test name
Test status
Simulation time 675134000089 ps
CPU time 400.26 seconds
Started Jun 22 05:51:22 PM PDT 24
Finished Jun 22 05:58:02 PM PDT 24
Peak memory 202136 kb
Host smart-c2225e4b-d598-40a7-b040-e0f294b079c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108378221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3108378221
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.175770694
Short name T18
Test name
Test status
Simulation time 85900455096 ps
CPU time 197.87 seconds
Started Jun 22 05:51:12 PM PDT 24
Finished Jun 22 05:54:31 PM PDT 24
Peak memory 210896 kb
Host smart-49228ded-ca78-4dfc-b151-b49204e327a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175770694 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.175770694
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.483999620
Short name T771
Test name
Test status
Simulation time 464632881 ps
CPU time 0.82 seconds
Started Jun 22 05:51:29 PM PDT 24
Finished Jun 22 05:51:30 PM PDT 24
Peak memory 201920 kb
Host smart-72570474-755c-4ae8-917e-0629a5791119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483999620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.483999620
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.4030413981
Short name T654
Test name
Test status
Simulation time 499696119533 ps
CPU time 565.03 seconds
Started Jun 22 05:51:20 PM PDT 24
Finished Jun 22 06:00:46 PM PDT 24
Peak memory 202204 kb
Host smart-f3b68adb-a077-46a3-882c-91ce85baa093
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030413981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.4030413981
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.982666035
Short name T329
Test name
Test status
Simulation time 163913029896 ps
CPU time 77.18 seconds
Started Jun 22 05:51:19 PM PDT 24
Finished Jun 22 05:52:36 PM PDT 24
Peak memory 202276 kb
Host smart-3f77a41c-d902-4d12-9891-02d387d3c6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982666035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.982666035
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3929703385
Short name T557
Test name
Test status
Simulation time 321143875155 ps
CPU time 748.7 seconds
Started Jun 22 05:51:11 PM PDT 24
Finished Jun 22 06:03:41 PM PDT 24
Peak memory 202224 kb
Host smart-06a08e18-8213-440b-bf8f-5df28ab4be9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929703385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3929703385
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2098635193
Short name T653
Test name
Test status
Simulation time 321614371661 ps
CPU time 186.34 seconds
Started Jun 22 05:51:11 PM PDT 24
Finished Jun 22 05:54:18 PM PDT 24
Peak memory 202252 kb
Host smart-9a67d429-919a-4221-9ccb-784e2db2e75e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098635193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2098635193
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1909131826
Short name T642
Test name
Test status
Simulation time 332959516234 ps
CPU time 721.19 seconds
Started Jun 22 05:51:13 PM PDT 24
Finished Jun 22 06:03:14 PM PDT 24
Peak memory 202212 kb
Host smart-3f792cd9-92bd-4c16-8a56-904c9ea872b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909131826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1909131826
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1166328526
Short name T395
Test name
Test status
Simulation time 167231652294 ps
CPU time 393.89 seconds
Started Jun 22 05:51:11 PM PDT 24
Finished Jun 22 05:57:45 PM PDT 24
Peak memory 202184 kb
Host smart-805847c4-95ec-421c-8368-5e0b2a844cee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166328526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1166328526
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2214003211
Short name T150
Test name
Test status
Simulation time 170226636355 ps
CPU time 97.01 seconds
Started Jun 22 05:51:21 PM PDT 24
Finished Jun 22 05:52:58 PM PDT 24
Peak memory 202268 kb
Host smart-ddae0598-4237-4069-8323-ce6021ab63ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214003211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2214003211
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2875854663
Short name T508
Test name
Test status
Simulation time 199675329714 ps
CPU time 95.23 seconds
Started Jun 22 05:51:20 PM PDT 24
Finished Jun 22 05:52:55 PM PDT 24
Peak memory 202204 kb
Host smart-2f15f05f-9de3-46e0-80d1-379334771ed3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875854663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2875854663
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2884298222
Short name T354
Test name
Test status
Simulation time 123112798906 ps
CPU time 409.8 seconds
Started Jun 22 05:51:19 PM PDT 24
Finished Jun 22 05:58:09 PM PDT 24
Peak memory 202532 kb
Host smart-84519c36-f957-412a-8994-c57ba6ab7cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884298222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2884298222
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2084819242
Short name T584
Test name
Test status
Simulation time 31383800307 ps
CPU time 32.79 seconds
Started Jun 22 05:51:19 PM PDT 24
Finished Jun 22 05:51:52 PM PDT 24
Peak memory 202012 kb
Host smart-8c7377f2-415b-4477-93ca-ca438258d790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084819242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2084819242
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2111512979
Short name T725
Test name
Test status
Simulation time 4795172993 ps
CPU time 6.35 seconds
Started Jun 22 05:51:19 PM PDT 24
Finished Jun 22 05:51:26 PM PDT 24
Peak memory 202032 kb
Host smart-1042fbae-4545-4111-a858-79affe68a9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111512979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2111512979
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1705384845
Short name T561
Test name
Test status
Simulation time 6107491127 ps
CPU time 3.99 seconds
Started Jun 22 05:51:13 PM PDT 24
Finished Jun 22 05:51:17 PM PDT 24
Peak memory 202000 kb
Host smart-0640bded-6881-41ce-b907-484d42ae3539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705384845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1705384845
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.862109281
Short name T25
Test name
Test status
Simulation time 444653083 ps
CPU time 1.26 seconds
Started Jun 22 05:51:41 PM PDT 24
Finished Jun 22 05:51:43 PM PDT 24
Peak memory 201916 kb
Host smart-69f07887-f9f7-4d41-8893-5d79b80f687b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862109281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.862109281
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1953727761
Short name T233
Test name
Test status
Simulation time 175800691725 ps
CPU time 215.35 seconds
Started Jun 22 05:51:35 PM PDT 24
Finished Jun 22 05:55:11 PM PDT 24
Peak memory 202216 kb
Host smart-ecbdd9c8-2bab-4ea5-8756-5194ef47a40c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953727761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1953727761
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.678764631
Short name T323
Test name
Test status
Simulation time 167184994914 ps
CPU time 73.41 seconds
Started Jun 22 05:51:31 PM PDT 24
Finished Jun 22 05:52:44 PM PDT 24
Peak memory 202284 kb
Host smart-27cb52ba-c41a-4a15-8efe-a1488007c35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678764631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.678764631
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.188186361
Short name T661
Test name
Test status
Simulation time 482889134783 ps
CPU time 292.8 seconds
Started Jun 22 05:51:34 PM PDT 24
Finished Jun 22 05:56:28 PM PDT 24
Peak memory 202252 kb
Host smart-57a7460d-5269-404c-81b7-a5efa6a27442
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=188186361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.188186361
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.519357885
Short name T773
Test name
Test status
Simulation time 327241046901 ps
CPU time 760.56 seconds
Started Jun 22 05:51:27 PM PDT 24
Finished Jun 22 06:04:08 PM PDT 24
Peak memory 202256 kb
Host smart-bf199c67-08d2-4e66-b58a-b40109b930c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519357885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.519357885
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.243255716
Short name T750
Test name
Test status
Simulation time 164092627338 ps
CPU time 102.19 seconds
Started Jun 22 05:51:27 PM PDT 24
Finished Jun 22 05:53:10 PM PDT 24
Peak memory 202148 kb
Host smart-eb86b9b0-66f6-44df-bb07-cc111a10ce37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=243255716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.243255716
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3624394540
Short name T251
Test name
Test status
Simulation time 537230758839 ps
CPU time 305.38 seconds
Started Jun 22 05:51:34 PM PDT 24
Finished Jun 22 05:56:40 PM PDT 24
Peak memory 202244 kb
Host smart-27ad30c7-65a5-4728-8a6f-64cb5750c6ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624394540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3624394540
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3460596746
Short name T497
Test name
Test status
Simulation time 189848761627 ps
CPU time 110.62 seconds
Started Jun 22 05:51:34 PM PDT 24
Finished Jun 22 05:53:25 PM PDT 24
Peak memory 202196 kb
Host smart-618d3a10-f5b3-4bb3-8339-f9a1c14e9819
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460596746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3460596746
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.322239810
Short name T350
Test name
Test status
Simulation time 113902186331 ps
CPU time 421.24 seconds
Started Jun 22 05:51:47 PM PDT 24
Finished Jun 22 05:58:49 PM PDT 24
Peak memory 202472 kb
Host smart-fbfd083f-5174-458c-84b0-0a7e48a0fa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322239810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.322239810
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1351175431
Short name T756
Test name
Test status
Simulation time 25902741229 ps
CPU time 60.09 seconds
Started Jun 22 05:51:47 PM PDT 24
Finished Jun 22 05:52:48 PM PDT 24
Peak memory 202068 kb
Host smart-4c7543b0-206f-4d32-a0a3-fde111686084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351175431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1351175431
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3191936675
Short name T605
Test name
Test status
Simulation time 3621907326 ps
CPU time 3.31 seconds
Started Jun 22 05:51:41 PM PDT 24
Finished Jun 22 05:51:45 PM PDT 24
Peak memory 201992 kb
Host smart-191ab4b0-a0c4-4d28-8450-e108c5e64d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191936675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3191936675
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3981907234
Short name T360
Test name
Test status
Simulation time 5958343973 ps
CPU time 14.9 seconds
Started Jun 22 05:51:29 PM PDT 24
Finished Jun 22 05:51:44 PM PDT 24
Peak memory 202036 kb
Host smart-78e1f7a0-44c3-4be6-b2dd-6308153e15ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981907234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3981907234
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.79093447
Short name T757
Test name
Test status
Simulation time 172858826878 ps
CPU time 371.76 seconds
Started Jun 22 05:51:41 PM PDT 24
Finished Jun 22 05:57:53 PM PDT 24
Peak memory 202268 kb
Host smart-c200825a-2f04-4493-9e8a-579784f8996c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79093447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.79093447
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1913873210
Short name T345
Test name
Test status
Simulation time 31784836456 ps
CPU time 36.57 seconds
Started Jun 22 05:51:42 PM PDT 24
Finished Jun 22 05:52:19 PM PDT 24
Peak memory 210532 kb
Host smart-fe84db43-b7de-4570-9d96-d148d92aa4a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913873210 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1913873210
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1523715175
Short name T555
Test name
Test status
Simulation time 441382407 ps
CPU time 0.69 seconds
Started Jun 22 05:44:05 PM PDT 24
Finished Jun 22 05:44:07 PM PDT 24
Peak memory 201924 kb
Host smart-e6568d03-e2d0-49fc-888c-4e7d1719538c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523715175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1523715175
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.4229001747
Short name T271
Test name
Test status
Simulation time 520784060894 ps
CPU time 267.27 seconds
Started Jun 22 05:43:46 PM PDT 24
Finished Jun 22 05:48:13 PM PDT 24
Peak memory 202104 kb
Host smart-226fd273-76d8-47af-b8e3-d8f031178f8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229001747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.4229001747
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.971624171
Short name T39
Test name
Test status
Simulation time 164581734535 ps
CPU time 103.65 seconds
Started Jun 22 05:43:37 PM PDT 24
Finished Jun 22 05:45:21 PM PDT 24
Peak memory 202212 kb
Host smart-4c494933-a8c2-41d8-bb8f-8b95646dca8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971624171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.971624171
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2230838077
Short name T778
Test name
Test status
Simulation time 491204898695 ps
CPU time 180.08 seconds
Started Jun 22 05:43:38 PM PDT 24
Finished Jun 22 05:46:38 PM PDT 24
Peak memory 202176 kb
Host smart-b9c38a13-adad-4fb4-80a6-c32eba14ef86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230838077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2230838077
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3458009242
Short name T588
Test name
Test status
Simulation time 485674612131 ps
CPU time 570.47 seconds
Started Jun 22 05:43:39 PM PDT 24
Finished Jun 22 05:53:09 PM PDT 24
Peak memory 202336 kb
Host smart-c3df9d03-2df3-4dd4-95f0-338be0057b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458009242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3458009242
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2845784869
Short name T606
Test name
Test status
Simulation time 333849253766 ps
CPU time 161.25 seconds
Started Jun 22 05:43:38 PM PDT 24
Finished Jun 22 05:46:20 PM PDT 24
Peak memory 202180 kb
Host smart-dff0ddbc-45c3-46c5-af7c-d6e1f8d19d59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845784869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2845784869
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.954533332
Short name T492
Test name
Test status
Simulation time 442511782528 ps
CPU time 1004.56 seconds
Started Jun 22 05:43:46 PM PDT 24
Finished Jun 22 06:00:31 PM PDT 24
Peak memory 202224 kb
Host smart-ede14ca1-6b98-49f4-9b6e-7d7207cbde09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954533332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.954533332
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2831508592
Short name T547
Test name
Test status
Simulation time 112585051318 ps
CPU time 397.4 seconds
Started Jun 22 05:43:53 PM PDT 24
Finished Jun 22 05:50:31 PM PDT 24
Peak memory 202556 kb
Host smart-b7fd5f3e-3484-4610-82f7-e526c6b531e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831508592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2831508592
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1775808686
Short name T571
Test name
Test status
Simulation time 22175110717 ps
CPU time 55.3 seconds
Started Jun 22 05:43:46 PM PDT 24
Finished Jun 22 05:44:41 PM PDT 24
Peak memory 202040 kb
Host smart-857a523b-f3d3-4793-a540-65ea70674260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775808686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1775808686
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.759620555
Short name T614
Test name
Test status
Simulation time 3731750523 ps
CPU time 9.6 seconds
Started Jun 22 05:43:45 PM PDT 24
Finished Jun 22 05:43:55 PM PDT 24
Peak memory 202044 kb
Host smart-06764fd0-4df5-480f-823d-8c7e4349d323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759620555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.759620555
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.665247721
Short name T103
Test name
Test status
Simulation time 4612314416 ps
CPU time 1.38 seconds
Started Jun 22 05:43:52 PM PDT 24
Finished Jun 22 05:43:54 PM PDT 24
Peak memory 217744 kb
Host smart-44c407d1-d1c8-40f2-8d68-1aa2403c03ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665247721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.665247721
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2974405983
Short name T670
Test name
Test status
Simulation time 5897972856 ps
CPU time 4.44 seconds
Started Jun 22 05:43:37 PM PDT 24
Finished Jun 22 05:43:41 PM PDT 24
Peak memory 202056 kb
Host smart-b42d1e31-c0f8-4948-9701-a5cd4fa0cb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974405983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2974405983
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3512100915
Short name T169
Test name
Test status
Simulation time 837622386880 ps
CPU time 1900.05 seconds
Started Jun 22 05:43:53 PM PDT 24
Finished Jun 22 06:15:34 PM PDT 24
Peak memory 202456 kb
Host smart-1971b312-e12c-4bea-9571-78e96824605d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512100915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3512100915
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2553500787
Short name T110
Test name
Test status
Simulation time 108806531757 ps
CPU time 62.72 seconds
Started Jun 22 05:43:53 PM PDT 24
Finished Jun 22 05:44:56 PM PDT 24
Peak memory 210536 kb
Host smart-4867fe16-5969-4887-87cc-1bb3721a6375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553500787 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2553500787
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2245614259
Short name T699
Test name
Test status
Simulation time 513080593 ps
CPU time 1.68 seconds
Started Jun 22 05:51:54 PM PDT 24
Finished Jun 22 05:51:56 PM PDT 24
Peak memory 201920 kb
Host smart-d0e8f0d6-2d76-4b34-9fad-749fc36b8b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245614259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2245614259
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3935391787
Short name T257
Test name
Test status
Simulation time 492016613636 ps
CPU time 226.21 seconds
Started Jun 22 05:51:49 PM PDT 24
Finished Jun 22 05:55:36 PM PDT 24
Peak memory 202112 kb
Host smart-1c09a485-10d1-480f-aa1c-563704686788
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935391787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3935391787
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3099900793
Short name T300
Test name
Test status
Simulation time 560437499431 ps
CPU time 633.82 seconds
Started Jun 22 05:51:54 PM PDT 24
Finished Jun 22 06:02:29 PM PDT 24
Peak memory 202200 kb
Host smart-91a04856-785a-4329-9cb3-ae5831735d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099900793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3099900793
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.318717068
Short name T717
Test name
Test status
Simulation time 164019981376 ps
CPU time 100.47 seconds
Started Jun 22 05:51:46 PM PDT 24
Finished Jun 22 05:53:27 PM PDT 24
Peak memory 202148 kb
Host smart-b2cf087c-2920-466f-ac98-f13705756657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318717068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.318717068
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3133186402
Short name T615
Test name
Test status
Simulation time 162582363962 ps
CPU time 353.2 seconds
Started Jun 22 05:51:47 PM PDT 24
Finished Jun 22 05:57:41 PM PDT 24
Peak memory 202184 kb
Host smart-34ce5abc-2b13-4883-a5e9-9954234f09df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133186402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3133186402
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.735731733
Short name T152
Test name
Test status
Simulation time 488513470798 ps
CPU time 1200.72 seconds
Started Jun 22 05:51:52 PM PDT 24
Finished Jun 22 06:11:53 PM PDT 24
Peak memory 202248 kb
Host smart-4ad842a9-16ab-44eb-bce4-8aa0f1417780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735731733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.735731733
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.4260174781
Short name T26
Test name
Test status
Simulation time 484517336331 ps
CPU time 273.8 seconds
Started Jun 22 05:51:52 PM PDT 24
Finished Jun 22 05:56:26 PM PDT 24
Peak memory 202220 kb
Host smart-86c26d63-39d0-4869-9fa8-7923f3c98859
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260174781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.4260174781
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3003074339
Short name T318
Test name
Test status
Simulation time 186456340427 ps
CPU time 230.83 seconds
Started Jun 22 05:51:52 PM PDT 24
Finished Jun 22 05:55:43 PM PDT 24
Peak memory 202160 kb
Host smart-0fd3da17-d824-4968-beff-450f9b73a546
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003074339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3003074339
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.4244317856
Short name T398
Test name
Test status
Simulation time 406980001788 ps
CPU time 904.44 seconds
Started Jun 22 05:51:48 PM PDT 24
Finished Jun 22 06:06:53 PM PDT 24
Peak memory 202192 kb
Host smart-d50b8b47-290b-4f95-897b-413e151d1111
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244317856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.4244317856
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3749008092
Short name T348
Test name
Test status
Simulation time 113035042047 ps
CPU time 375.19 seconds
Started Jun 22 05:51:55 PM PDT 24
Finished Jun 22 05:58:10 PM PDT 24
Peak memory 202588 kb
Host smart-5167d035-fe1c-426c-a58a-f19be67cc362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749008092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3749008092
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2943857947
Short name T701
Test name
Test status
Simulation time 25110038239 ps
CPU time 16.36 seconds
Started Jun 22 05:51:55 PM PDT 24
Finished Jun 22 05:52:11 PM PDT 24
Peak memory 202028 kb
Host smart-f374ca48-3cd3-4eec-bcf0-6ccb2734e89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943857947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2943857947
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.367545720
Short name T385
Test name
Test status
Simulation time 5411618331 ps
CPU time 3.89 seconds
Started Jun 22 05:51:53 PM PDT 24
Finished Jun 22 05:51:58 PM PDT 24
Peak memory 202056 kb
Host smart-d0bbb856-4073-4f67-9337-7e4c3ed30104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367545720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.367545720
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1377153269
Short name T599
Test name
Test status
Simulation time 5573034303 ps
CPU time 13.22 seconds
Started Jun 22 05:51:42 PM PDT 24
Finished Jun 22 05:51:56 PM PDT 24
Peak memory 202036 kb
Host smart-a8ac5bd7-875a-41ac-a08c-1c2f06b2678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377153269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1377153269
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3990277736
Short name T293
Test name
Test status
Simulation time 253848152679 ps
CPU time 395.37 seconds
Started Jun 22 05:51:55 PM PDT 24
Finished Jun 22 05:58:31 PM PDT 24
Peak memory 202852 kb
Host smart-01ebb49c-8944-43fe-87d5-e4967f32e562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990277736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3990277736
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3675274303
Short name T542
Test name
Test status
Simulation time 27705451727 ps
CPU time 100.62 seconds
Started Jun 22 05:51:54 PM PDT 24
Finished Jun 22 05:53:35 PM PDT 24
Peak memory 210924 kb
Host smart-4420aac4-e106-49b7-919c-8c2f79c91e49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675274303 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3675274303
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3216886649
Short name T396
Test name
Test status
Simulation time 526347961 ps
CPU time 0.89 seconds
Started Jun 22 05:52:16 PM PDT 24
Finished Jun 22 05:52:17 PM PDT 24
Peak memory 201924 kb
Host smart-09a959c9-5202-4423-8722-2e87c83a98d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216886649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3216886649
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.4082415405
Short name T180
Test name
Test status
Simulation time 546340617339 ps
CPU time 227.1 seconds
Started Jun 22 05:52:19 PM PDT 24
Finished Jun 22 05:56:07 PM PDT 24
Peak memory 202220 kb
Host smart-1daf54b1-1d5d-4b83-a752-b21ca7071ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082415405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.4082415405
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2256001834
Short name T719
Test name
Test status
Simulation time 336267600132 ps
CPU time 182.52 seconds
Started Jun 22 05:52:01 PM PDT 24
Finished Jun 22 05:55:04 PM PDT 24
Peak memory 202196 kb
Host smart-a3560e31-2b91-4c00-8ad9-e89491e1ab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256001834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2256001834
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4013621918
Short name T698
Test name
Test status
Simulation time 164964908034 ps
CPU time 93.02 seconds
Started Jun 22 05:52:02 PM PDT 24
Finished Jun 22 05:53:36 PM PDT 24
Peak memory 202188 kb
Host smart-592054b6-9fb0-4f04-aca0-8c35df53c701
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013621918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4013621918
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.436915911
Short name T747
Test name
Test status
Simulation time 504222314661 ps
CPU time 556.99 seconds
Started Jun 22 05:52:02 PM PDT 24
Finished Jun 22 06:01:20 PM PDT 24
Peak memory 202260 kb
Host smart-c3eb1083-4177-44c1-9ba6-4a0c95d537b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436915911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.436915911
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.317091136
Short name T355
Test name
Test status
Simulation time 330862182373 ps
CPU time 742.34 seconds
Started Jun 22 05:52:01 PM PDT 24
Finished Jun 22 06:04:23 PM PDT 24
Peak memory 202260 kb
Host smart-7befe8ea-227b-45dd-b3fc-cffe14fef811
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=317091136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.317091136
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1821544954
Short name T669
Test name
Test status
Simulation time 391315416838 ps
CPU time 876.84 seconds
Started Jun 22 05:52:10 PM PDT 24
Finished Jun 22 06:06:47 PM PDT 24
Peak memory 202172 kb
Host smart-339b8e57-1696-43bb-95b7-94dde3881c6a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821544954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1821544954
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1731810754
Short name T792
Test name
Test status
Simulation time 128244075133 ps
CPU time 422.5 seconds
Started Jun 22 05:52:17 PM PDT 24
Finished Jun 22 05:59:20 PM PDT 24
Peak memory 202444 kb
Host smart-232ec7ad-4ffe-406b-9379-0e886f4ee7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731810754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1731810754
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2866388844
Short name T371
Test name
Test status
Simulation time 26764900358 ps
CPU time 30.27 seconds
Started Jun 22 05:52:15 PM PDT 24
Finished Jun 22 05:52:46 PM PDT 24
Peak memory 202036 kb
Host smart-5daff38f-0c83-49ec-be41-5bdfb4ee462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866388844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2866388844
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1193126968
Short name T583
Test name
Test status
Simulation time 5377535002 ps
CPU time 2.91 seconds
Started Jun 22 05:52:15 PM PDT 24
Finished Jun 22 05:52:18 PM PDT 24
Peak memory 202048 kb
Host smart-7777a33b-faca-479d-b476-81a49c4c7f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193126968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1193126968
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3510782777
Short name T143
Test name
Test status
Simulation time 5577300791 ps
CPU time 13.64 seconds
Started Jun 22 05:51:56 PM PDT 24
Finished Jun 22 05:52:10 PM PDT 24
Peak memory 202000 kb
Host smart-a094f29b-22e3-4633-b080-99dfe365b9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510782777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3510782777
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.146145700
Short name T46
Test name
Test status
Simulation time 83966368072 ps
CPU time 55.25 seconds
Started Jun 22 05:52:16 PM PDT 24
Finished Jun 22 05:53:11 PM PDT 24
Peak memory 210800 kb
Host smart-46617857-eea1-49b2-8456-cb390684c8db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146145700 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.146145700
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1946881503
Short name T13
Test name
Test status
Simulation time 479341632 ps
CPU time 1.69 seconds
Started Jun 22 05:52:34 PM PDT 24
Finished Jun 22 05:52:36 PM PDT 24
Peak memory 201880 kb
Host smart-43288c30-95a9-4af5-a10f-e95fa1f20662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946881503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1946881503
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2681172780
Short name T342
Test name
Test status
Simulation time 539015750635 ps
CPU time 298.41 seconds
Started Jun 22 05:52:25 PM PDT 24
Finished Jun 22 05:57:24 PM PDT 24
Peak memory 202364 kb
Host smart-74efa771-0b26-4682-a09a-74c9b9879d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681172780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2681172780
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3456248677
Short name T272
Test name
Test status
Simulation time 334553157908 ps
CPU time 111 seconds
Started Jun 22 05:52:17 PM PDT 24
Finished Jun 22 05:54:08 PM PDT 24
Peak memory 202300 kb
Host smart-59d9b77d-7fc0-41e1-beac-54768b17afdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456248677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3456248677
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.68980996
Short name T507
Test name
Test status
Simulation time 161489830179 ps
CPU time 96.03 seconds
Started Jun 22 05:52:15 PM PDT 24
Finished Jun 22 05:53:52 PM PDT 24
Peak memory 202176 kb
Host smart-4f33b417-ebbd-4fd1-925e-1cf5db608d15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=68980996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt
_fixed.68980996
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2699110639
Short name T720
Test name
Test status
Simulation time 496808027893 ps
CPU time 1151.38 seconds
Started Jun 22 05:52:16 PM PDT 24
Finished Jun 22 06:11:28 PM PDT 24
Peak memory 202248 kb
Host smart-e22471c5-3509-41d2-97df-b0798ae144b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699110639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2699110639
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.143625052
Short name T600
Test name
Test status
Simulation time 166696652208 ps
CPU time 104.03 seconds
Started Jun 22 05:52:16 PM PDT 24
Finished Jun 22 05:54:00 PM PDT 24
Peak memory 202196 kb
Host smart-b245d9f8-43bb-42c3-ab68-09411147d61a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=143625052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.143625052
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3430737611
Short name T675
Test name
Test status
Simulation time 169045946734 ps
CPU time 392.39 seconds
Started Jun 22 05:52:26 PM PDT 24
Finished Jun 22 05:58:59 PM PDT 24
Peak memory 202284 kb
Host smart-b1e97f99-e847-4eab-8a38-f659bcf6e2b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430737611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3430737611
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3013304372
Short name T545
Test name
Test status
Simulation time 205482734342 ps
CPU time 160.38 seconds
Started Jun 22 05:52:23 PM PDT 24
Finished Jun 22 05:55:04 PM PDT 24
Peak memory 202180 kb
Host smart-b519c5ad-c3ef-4f81-ada1-15fc1118d2bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013304372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3013304372
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.771806192
Short name T530
Test name
Test status
Simulation time 88541266722 ps
CPU time 300.62 seconds
Started Jun 22 05:52:25 PM PDT 24
Finished Jun 22 05:57:26 PM PDT 24
Peak memory 202492 kb
Host smart-daef43d6-c214-4d5b-8f73-8c5bfc560fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771806192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.771806192
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1592179312
Short name T572
Test name
Test status
Simulation time 30828922065 ps
CPU time 10.57 seconds
Started Jun 22 05:52:24 PM PDT 24
Finished Jun 22 05:52:35 PM PDT 24
Peak memory 202032 kb
Host smart-d9731ad5-cb80-49ef-8661-128a7a739d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592179312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1592179312
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.507083361
Short name T434
Test name
Test status
Simulation time 4114676841 ps
CPU time 1.33 seconds
Started Jun 22 05:52:25 PM PDT 24
Finished Jun 22 05:52:27 PM PDT 24
Peak memory 202064 kb
Host smart-2a477631-1009-4fc6-b8fe-e5cc99028d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507083361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.507083361
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.887551319
Short name T573
Test name
Test status
Simulation time 5786425762 ps
CPU time 6.98 seconds
Started Jun 22 05:52:16 PM PDT 24
Finished Jun 22 05:52:24 PM PDT 24
Peak memory 202024 kb
Host smart-f3b6297f-7404-46ea-a08a-66b1dab7cefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887551319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.887551319
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2455665118
Short name T196
Test name
Test status
Simulation time 339259610799 ps
CPU time 216.5 seconds
Started Jun 22 05:52:31 PM PDT 24
Finished Jun 22 05:56:08 PM PDT 24
Peak memory 202148 kb
Host smart-dae3b3a2-6c52-43d7-890d-d750e57a574f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455665118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2455665118
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3921542884
Short name T657
Test name
Test status
Simulation time 50839604321 ps
CPU time 83.67 seconds
Started Jun 22 05:52:27 PM PDT 24
Finished Jun 22 05:53:51 PM PDT 24
Peak memory 218488 kb
Host smart-ac530140-ebce-4feb-8d0a-28229730751b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921542884 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3921542884
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3919345605
Short name T399
Test name
Test status
Simulation time 485962124 ps
CPU time 1.78 seconds
Started Jun 22 05:52:46 PM PDT 24
Finished Jun 22 05:52:48 PM PDT 24
Peak memory 201920 kb
Host smart-a48089c4-4a46-4788-8299-f3857e180717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919345605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3919345605
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3169500690
Short name T239
Test name
Test status
Simulation time 414084976344 ps
CPU time 89.08 seconds
Started Jun 22 05:52:41 PM PDT 24
Finished Jun 22 05:54:10 PM PDT 24
Peak memory 202212 kb
Host smart-4414afde-2402-4e2a-bf29-a5fa763d22c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169500690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3169500690
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2283700312
Short name T296
Test name
Test status
Simulation time 322244082106 ps
CPU time 201.92 seconds
Started Jun 22 05:52:31 PM PDT 24
Finished Jun 22 05:55:54 PM PDT 24
Peak memory 202136 kb
Host smart-8f78a8de-f315-4f24-8105-76b3928f8918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283700312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2283700312
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1316129537
Short name T711
Test name
Test status
Simulation time 166874411157 ps
CPU time 203.55 seconds
Started Jun 22 05:52:40 PM PDT 24
Finished Jun 22 05:56:04 PM PDT 24
Peak memory 202136 kb
Host smart-8330c787-77e9-43f3-a80a-01d7215e47b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316129537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1316129537
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3549984156
Short name T494
Test name
Test status
Simulation time 158153820618 ps
CPU time 86.48 seconds
Started Jun 22 05:52:33 PM PDT 24
Finished Jun 22 05:54:00 PM PDT 24
Peak memory 202284 kb
Host smart-53668957-a934-4b66-a580-8f295ec5f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549984156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3549984156
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2762717103
Short name T649
Test name
Test status
Simulation time 322922916571 ps
CPU time 402.45 seconds
Started Jun 22 05:52:32 PM PDT 24
Finished Jun 22 05:59:15 PM PDT 24
Peak memory 202264 kb
Host smart-8c022e26-dec2-42b2-a438-b1b480d4c935
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762717103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2762717103
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2936561175
Short name T466
Test name
Test status
Simulation time 179497858705 ps
CPU time 95.66 seconds
Started Jun 22 05:52:41 PM PDT 24
Finished Jun 22 05:54:17 PM PDT 24
Peak memory 202184 kb
Host smart-62a283b6-860e-49d2-9c7a-feb54f92d435
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936561175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2936561175
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1540125497
Short name T589
Test name
Test status
Simulation time 397504089686 ps
CPU time 889.61 seconds
Started Jun 22 05:52:39 PM PDT 24
Finished Jun 22 06:07:29 PM PDT 24
Peak memory 202140 kb
Host smart-d2b5a3fe-df19-4e42-b1c3-5c33b0c13068
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540125497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1540125497
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3448782668
Short name T538
Test name
Test status
Simulation time 128963084508 ps
CPU time 439.17 seconds
Started Jun 22 05:52:46 PM PDT 24
Finished Jun 22 06:00:06 PM PDT 24
Peak memory 202604 kb
Host smart-595dd6e1-a34e-4917-947c-72917e998df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448782668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3448782668
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2561369794
Short name T523
Test name
Test status
Simulation time 25000036488 ps
CPU time 13.79 seconds
Started Jun 22 05:52:47 PM PDT 24
Finished Jun 22 05:53:01 PM PDT 24
Peak memory 202004 kb
Host smart-f51372be-e498-42b7-8db3-a29319c5313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561369794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2561369794
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3328875802
Short name T457
Test name
Test status
Simulation time 5079599938 ps
CPU time 3.3 seconds
Started Jun 22 05:52:48 PM PDT 24
Finished Jun 22 05:52:52 PM PDT 24
Peak memory 201916 kb
Host smart-7d3b00d1-f45d-4d68-a5e4-a64010cd692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328875802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3328875802
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.625916676
Short name T401
Test name
Test status
Simulation time 6066791783 ps
CPU time 12.96 seconds
Started Jun 22 05:52:35 PM PDT 24
Finished Jun 22 05:52:49 PM PDT 24
Peak memory 202036 kb
Host smart-ca30e405-ae9f-45e8-ab6a-2b49df62f58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625916676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.625916676
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3149593531
Short name T769
Test name
Test status
Simulation time 335014883379 ps
CPU time 619.63 seconds
Started Jun 22 05:52:46 PM PDT 24
Finished Jun 22 06:03:06 PM PDT 24
Peak memory 210680 kb
Host smart-3f3cd816-8d51-4af4-b8f7-a88cc56d2859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149593531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3149593531
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3553646623
Short name T20
Test name
Test status
Simulation time 23419916330 ps
CPU time 45.93 seconds
Started Jun 22 05:52:50 PM PDT 24
Finished Jun 22 05:53:36 PM PDT 24
Peak memory 210832 kb
Host smart-a36c9abc-b230-4938-be56-bebd7d5ca433
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553646623 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3553646623
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1102890681
Short name T743
Test name
Test status
Simulation time 324559821 ps
CPU time 0.71 seconds
Started Jun 22 05:53:05 PM PDT 24
Finished Jun 22 05:53:06 PM PDT 24
Peak memory 201904 kb
Host smart-fa1233b0-8e5b-4ee3-92fe-cc6f2d9ba69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102890681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1102890681
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2013051152
Short name T266
Test name
Test status
Simulation time 358767242656 ps
CPU time 851.51 seconds
Started Jun 22 05:52:56 PM PDT 24
Finished Jun 22 06:07:08 PM PDT 24
Peak memory 202432 kb
Host smart-2fd32e11-383e-4b43-9e4b-e0456b1bff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013051152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2013051152
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.773651907
Short name T220
Test name
Test status
Simulation time 165269788874 ps
CPU time 393.93 seconds
Started Jun 22 05:52:55 PM PDT 24
Finished Jun 22 05:59:29 PM PDT 24
Peak memory 202300 kb
Host smart-9b2d6870-752b-40d2-9461-2a7109d084ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773651907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.773651907
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2250331917
Short name T753
Test name
Test status
Simulation time 490642134069 ps
CPU time 85.56 seconds
Started Jun 22 05:52:54 PM PDT 24
Finished Jun 22 05:54:20 PM PDT 24
Peak memory 202240 kb
Host smart-d6c18175-4dcc-4219-a187-f5c74724246c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250331917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2250331917
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3995100310
Short name T160
Test name
Test status
Simulation time 318667778275 ps
CPU time 332.23 seconds
Started Jun 22 05:52:46 PM PDT 24
Finished Jun 22 05:58:19 PM PDT 24
Peak memory 202292 kb
Host smart-3b009bc5-9a47-42cb-8209-9b0c29b8cac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995100310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3995100310
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3506596075
Short name T489
Test name
Test status
Simulation time 330905815650 ps
CPU time 744.04 seconds
Started Jun 22 05:52:54 PM PDT 24
Finished Jun 22 06:05:18 PM PDT 24
Peak memory 202276 kb
Host smart-b4624c06-99e6-4dc2-b861-0beff7ffa076
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506596075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3506596075
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3651095704
Short name T788
Test name
Test status
Simulation time 636199417247 ps
CPU time 687.71 seconds
Started Jun 22 05:52:55 PM PDT 24
Finished Jun 22 06:04:23 PM PDT 24
Peak memory 202168 kb
Host smart-91bbb210-133b-4960-8ecf-6cf35ddd3483
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651095704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3651095704
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3481580751
Short name T372
Test name
Test status
Simulation time 395701519738 ps
CPU time 95.79 seconds
Started Jun 22 05:52:55 PM PDT 24
Finished Jun 22 05:54:31 PM PDT 24
Peak memory 202196 kb
Host smart-8ca75076-378e-4ec0-872f-4c78d724b325
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481580751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3481580751
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3976260760
Short name T205
Test name
Test status
Simulation time 131896589799 ps
CPU time 397.61 seconds
Started Jun 22 05:53:03 PM PDT 24
Finished Jun 22 05:59:41 PM PDT 24
Peak memory 202452 kb
Host smart-32b0d295-4689-41cc-83c2-094dba4f8167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976260760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3976260760
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1801295683
Short name T357
Test name
Test status
Simulation time 43883220023 ps
CPU time 51.77 seconds
Started Jun 22 05:53:02 PM PDT 24
Finished Jun 22 05:53:54 PM PDT 24
Peak memory 202024 kb
Host smart-a7588e00-8ad4-42f4-93ce-1d908cb81b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801295683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1801295683
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1733631272
Short name T426
Test name
Test status
Simulation time 3711076248 ps
CPU time 7.71 seconds
Started Jun 22 05:52:53 PM PDT 24
Finished Jun 22 05:53:02 PM PDT 24
Peak memory 202032 kb
Host smart-7709f52d-690e-4863-a90a-51ec87c37469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733631272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1733631272
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1592509503
Short name T665
Test name
Test status
Simulation time 5804018729 ps
CPU time 3.84 seconds
Started Jun 22 05:52:46 PM PDT 24
Finished Jun 22 05:52:50 PM PDT 24
Peak memory 202032 kb
Host smart-c9a816c2-fb36-418c-9047-6aa8cdce5ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592509503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1592509503
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1405467208
Short name T33
Test name
Test status
Simulation time 165583695501 ps
CPU time 201.52 seconds
Started Jun 22 05:53:02 PM PDT 24
Finished Jun 22 05:56:24 PM PDT 24
Peak memory 202212 kb
Host smart-05721360-ffbb-4851-b3c4-5f4b81844972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405467208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1405467208
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2176181637
Short name T433
Test name
Test status
Simulation time 454138985 ps
CPU time 1.13 seconds
Started Jun 22 05:53:10 PM PDT 24
Finished Jun 22 05:53:12 PM PDT 24
Peak memory 201908 kb
Host smart-0d231a06-8f8d-42f3-8c15-57c16038c317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176181637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2176181637
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.984090249
Short name T581
Test name
Test status
Simulation time 422260552371 ps
CPU time 341.18 seconds
Started Jun 22 05:53:10 PM PDT 24
Finished Jun 22 05:58:51 PM PDT 24
Peak memory 202216 kb
Host smart-014aa293-e1b5-4839-a57c-91bccf8c5cef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984090249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.984090249
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.889532520
Short name T256
Test name
Test status
Simulation time 165284774018 ps
CPU time 154.89 seconds
Started Jun 22 05:53:09 PM PDT 24
Finished Jun 22 05:55:45 PM PDT 24
Peak memory 202216 kb
Host smart-e6742826-a384-4f44-89fd-db35525ff9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889532520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.889532520
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.325295185
Short name T330
Test name
Test status
Simulation time 331449082750 ps
CPU time 210.15 seconds
Started Jun 22 05:53:01 PM PDT 24
Finished Jun 22 05:56:32 PM PDT 24
Peak memory 202168 kb
Host smart-604502d5-d923-40c4-8530-497d2b6b1926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325295185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.325295185
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1933223322
Short name T459
Test name
Test status
Simulation time 492053219483 ps
CPU time 138.52 seconds
Started Jun 22 05:53:03 PM PDT 24
Finished Jun 22 05:55:22 PM PDT 24
Peak memory 202188 kb
Host smart-d2603b69-5ef4-4cf2-8771-062085fe7e53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933223322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1933223322
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2206822183
Short name T178
Test name
Test status
Simulation time 492479520465 ps
CPU time 1156.19 seconds
Started Jun 22 05:53:01 PM PDT 24
Finished Jun 22 06:12:17 PM PDT 24
Peak memory 202284 kb
Host smart-cf1b52cb-309d-4150-a8cc-a32aaeedcf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206822183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2206822183
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1261394694
Short name T622
Test name
Test status
Simulation time 492872518948 ps
CPU time 593.66 seconds
Started Jun 22 05:53:03 PM PDT 24
Finished Jun 22 06:02:57 PM PDT 24
Peak memory 202180 kb
Host smart-ae9f9065-1ea5-4030-97db-eb02695eb908
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261394694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1261394694
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3998028292
Short name T249
Test name
Test status
Simulation time 341299291784 ps
CPU time 437.12 seconds
Started Jun 22 05:53:03 PM PDT 24
Finished Jun 22 06:00:21 PM PDT 24
Peak memory 202252 kb
Host smart-c80ec667-0dc7-4d02-81ef-2e479d850102
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998028292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3998028292
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.977932545
Short name T569
Test name
Test status
Simulation time 200340536061 ps
CPU time 96.13 seconds
Started Jun 22 05:53:10 PM PDT 24
Finished Jun 22 05:54:47 PM PDT 24
Peak memory 202184 kb
Host smart-76eb96d0-55cb-4b24-b915-6f50f3dfc7dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977932545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.977932545
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1157338741
Short name T423
Test name
Test status
Simulation time 126523523779 ps
CPU time 483.45 seconds
Started Jun 22 05:53:14 PM PDT 24
Finished Jun 22 06:01:18 PM PDT 24
Peak memory 202568 kb
Host smart-4b46ba4b-f366-4c86-b899-fe09ae5b923e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157338741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1157338741
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1953131744
Short name T630
Test name
Test status
Simulation time 25169611019 ps
CPU time 59.61 seconds
Started Jun 22 05:53:10 PM PDT 24
Finished Jun 22 05:54:10 PM PDT 24
Peak memory 202012 kb
Host smart-215efa70-0ac6-41bf-bdd9-2e048dd64e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953131744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1953131744
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.705902895
Short name T144
Test name
Test status
Simulation time 4622680581 ps
CPU time 3.47 seconds
Started Jun 22 05:53:09 PM PDT 24
Finished Jun 22 05:53:13 PM PDT 24
Peak memory 202020 kb
Host smart-5b586b82-3321-479b-b12a-ba41ec103040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705902895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.705902895
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1482214325
Short name T30
Test name
Test status
Simulation time 5756039709 ps
CPU time 4.1 seconds
Started Jun 22 05:53:01 PM PDT 24
Finished Jun 22 05:53:06 PM PDT 24
Peak memory 202028 kb
Host smart-8367be34-848c-41c4-974f-54a36dfd70f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482214325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1482214325
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3725105627
Short name T761
Test name
Test status
Simulation time 586111218109 ps
CPU time 453.48 seconds
Started Jun 22 05:53:09 PM PDT 24
Finished Jun 22 06:00:43 PM PDT 24
Peak memory 212872 kb
Host smart-b0d9c286-39cf-44da-af85-e0ae61e85404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725105627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3725105627
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3666856203
Short name T692
Test name
Test status
Simulation time 37164502764 ps
CPU time 79.33 seconds
Started Jun 22 05:53:08 PM PDT 24
Finished Jun 22 05:54:28 PM PDT 24
Peak memory 210616 kb
Host smart-0e660e3e-0307-45dd-a1ea-35cc6f78ea2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666856203 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3666856203
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2761848628
Short name T408
Test name
Test status
Simulation time 418131896 ps
CPU time 1.66 seconds
Started Jun 22 05:53:27 PM PDT 24
Finished Jun 22 05:53:29 PM PDT 24
Peak memory 201924 kb
Host smart-75a5dbfe-7793-4b3c-a1f8-631d3ee66b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761848628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2761848628
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.464179432
Short name T244
Test name
Test status
Simulation time 217435296571 ps
CPU time 325.1 seconds
Started Jun 22 05:53:25 PM PDT 24
Finished Jun 22 05:58:50 PM PDT 24
Peak memory 202220 kb
Host smart-abd8bbb3-e1db-4f99-a646-8a23f1dbb280
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464179432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.464179432
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1473207018
Short name T282
Test name
Test status
Simulation time 161289568256 ps
CPU time 176.1 seconds
Started Jun 22 05:53:18 PM PDT 24
Finished Jun 22 05:56:14 PM PDT 24
Peak memory 202288 kb
Host smart-bbbe96d4-1b96-4bdd-89db-3cda36895f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473207018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1473207018
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1385522273
Short name T537
Test name
Test status
Simulation time 163727948046 ps
CPU time 366.88 seconds
Started Jun 22 05:53:17 PM PDT 24
Finished Jun 22 05:59:24 PM PDT 24
Peak memory 202256 kb
Host smart-c7da1b58-08da-4ec7-a91a-e4df813c8a37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385522273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1385522273
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2749420692
Short name T120
Test name
Test status
Simulation time 163518579509 ps
CPU time 94.53 seconds
Started Jun 22 05:53:18 PM PDT 24
Finished Jun 22 05:54:52 PM PDT 24
Peak memory 202208 kb
Host smart-a83dbf7e-b27d-416d-9e99-757b5858a8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749420692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2749420692
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1549993661
Short name T121
Test name
Test status
Simulation time 489867208311 ps
CPU time 1106.17 seconds
Started Jun 22 05:53:19 PM PDT 24
Finished Jun 22 06:11:45 PM PDT 24
Peak memory 202260 kb
Host smart-90076695-6234-4fd3-9cd3-75e0d28f42ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549993661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1549993661
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2932022668
Short name T541
Test name
Test status
Simulation time 383660884281 ps
CPU time 900.61 seconds
Started Jun 22 05:53:17 PM PDT 24
Finished Jun 22 06:08:18 PM PDT 24
Peak memory 202200 kb
Host smart-ef9d9cda-58d3-4f8c-9aac-3dcaf89efdd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932022668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2932022668
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.67610172
Short name T586
Test name
Test status
Simulation time 392571687540 ps
CPU time 246.65 seconds
Started Jun 22 05:53:27 PM PDT 24
Finished Jun 22 05:57:34 PM PDT 24
Peak memory 202184 kb
Host smart-87238323-f9c7-4330-b36f-fbddb1bee82a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67610172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.a
dc_ctrl_filters_wakeup_fixed.67610172
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1512689434
Short name T422
Test name
Test status
Simulation time 99327221151 ps
CPU time 430.88 seconds
Started Jun 22 05:53:30 PM PDT 24
Finished Jun 22 06:00:41 PM PDT 24
Peak memory 202584 kb
Host smart-b9712f0c-da01-43cb-9a94-2a734d5c3899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512689434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1512689434
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.243626483
Short name T52
Test name
Test status
Simulation time 32254778062 ps
CPU time 69.46 seconds
Started Jun 22 05:53:26 PM PDT 24
Finished Jun 22 05:54:35 PM PDT 24
Peak memory 202020 kb
Host smart-d73ff44f-b1b5-48be-bda5-943faa266218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243626483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.243626483
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.4223382767
Short name T118
Test name
Test status
Simulation time 3274586871 ps
CPU time 8.97 seconds
Started Jun 22 05:53:25 PM PDT 24
Finished Jun 22 05:53:34 PM PDT 24
Peak memory 202052 kb
Host smart-2f345242-0f83-45bd-8e9a-0e33cc203b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223382767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.4223382767
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.416217576
Short name T369
Test name
Test status
Simulation time 5623852970 ps
CPU time 3.93 seconds
Started Jun 22 05:53:18 PM PDT 24
Finished Jun 22 05:53:22 PM PDT 24
Peak memory 202000 kb
Host smart-56612b7d-ade9-4284-89a0-90d67071d56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416217576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.416217576
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3925794276
Short name T114
Test name
Test status
Simulation time 253062046498 ps
CPU time 221.67 seconds
Started Jun 22 05:53:24 PM PDT 24
Finished Jun 22 05:57:06 PM PDT 24
Peak memory 202284 kb
Host smart-b74bcc92-1d11-4bf0-860a-5db8ea7d3467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925794276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3925794276
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2503099243
Short name T309
Test name
Test status
Simulation time 76061452985 ps
CPU time 86.72 seconds
Started Jun 22 05:53:24 PM PDT 24
Finished Jun 22 05:54:51 PM PDT 24
Peak memory 210476 kb
Host smart-89d26f99-2bc2-4d5e-9bb5-b2285a9c1c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503099243 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2503099243
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2255188040
Short name T513
Test name
Test status
Simulation time 296771416 ps
CPU time 1.26 seconds
Started Jun 22 05:53:39 PM PDT 24
Finished Jun 22 05:53:41 PM PDT 24
Peak memory 201924 kb
Host smart-225ed395-42eb-490d-98f3-fff513341999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255188040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2255188040
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4103065203
Short name T742
Test name
Test status
Simulation time 194963647868 ps
CPU time 179.18 seconds
Started Jun 22 05:53:36 PM PDT 24
Finished Jun 22 05:56:36 PM PDT 24
Peak memory 202296 kb
Host smart-92c87b78-1ee7-48ba-91ea-c88377104052
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103065203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4103065203
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1258924317
Short name T341
Test name
Test status
Simulation time 162664038760 ps
CPU time 391.71 seconds
Started Jun 22 05:53:33 PM PDT 24
Finished Jun 22 06:00:06 PM PDT 24
Peak memory 202196 kb
Host smart-74d3b272-058d-4093-96f6-08bad3c19db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258924317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1258924317
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1120674249
Short name T611
Test name
Test status
Simulation time 320421619336 ps
CPU time 194.26 seconds
Started Jun 22 05:53:32 PM PDT 24
Finished Jun 22 05:56:47 PM PDT 24
Peak memory 202280 kb
Host smart-39ec2ac8-df70-4618-9b49-abfef54e9367
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120674249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1120674249
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2911466885
Short name T179
Test name
Test status
Simulation time 497747077187 ps
CPU time 133.01 seconds
Started Jun 22 05:53:24 PM PDT 24
Finished Jun 22 05:55:37 PM PDT 24
Peak memory 202300 kb
Host smart-7c3970d3-bcd2-439b-986b-856d5f092ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911466885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2911466885
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1988812102
Short name T430
Test name
Test status
Simulation time 326218080783 ps
CPU time 702.46 seconds
Started Jun 22 05:53:34 PM PDT 24
Finished Jun 22 06:05:17 PM PDT 24
Peak memory 202288 kb
Host smart-cc76d362-5bd5-4425-8b72-95695c05b2d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988812102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1988812102
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.401725349
Short name T147
Test name
Test status
Simulation time 528235686995 ps
CPU time 640.59 seconds
Started Jun 22 05:53:33 PM PDT 24
Finished Jun 22 06:04:14 PM PDT 24
Peak memory 202488 kb
Host smart-5f39bc68-c47d-4b56-ba96-18ee9aadf26d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401725349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.401725349
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3956062702
Short name T522
Test name
Test status
Simulation time 584747909781 ps
CPU time 627.93 seconds
Started Jun 22 05:53:33 PM PDT 24
Finished Jun 22 06:04:02 PM PDT 24
Peak memory 202188 kb
Host smart-26353342-2094-45e1-9e3b-8bb10ea33bf7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956062702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3956062702
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4152947194
Short name T349
Test name
Test status
Simulation time 105411848501 ps
CPU time 381.12 seconds
Started Jun 22 05:53:38 PM PDT 24
Finished Jun 22 06:00:00 PM PDT 24
Peak memory 202500 kb
Host smart-7e0920d5-7bbc-44bd-a620-612888c02acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152947194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4152947194
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.64634325
Short name T478
Test name
Test status
Simulation time 42342310657 ps
CPU time 94.31 seconds
Started Jun 22 05:53:32 PM PDT 24
Finished Jun 22 05:55:06 PM PDT 24
Peak memory 202032 kb
Host smart-a0683358-4d67-4b7d-b839-af88ced47c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64634325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.64634325
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1742708280
Short name T768
Test name
Test status
Simulation time 5123141525 ps
CPU time 2.56 seconds
Started Jun 22 05:53:35 PM PDT 24
Finished Jun 22 05:53:38 PM PDT 24
Peak memory 202036 kb
Host smart-8bdeb685-7c99-4644-b6bf-ae189786599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742708280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1742708280
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1869311625
Short name T445
Test name
Test status
Simulation time 5935184242 ps
CPU time 6.34 seconds
Started Jun 22 05:53:25 PM PDT 24
Finished Jun 22 05:53:32 PM PDT 24
Peak memory 202048 kb
Host smart-7ecb26e1-6461-4466-be1a-63445ead9fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869311625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1869311625
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2444367968
Short name T619
Test name
Test status
Simulation time 348783150193 ps
CPU time 756.5 seconds
Started Jun 22 05:53:42 PM PDT 24
Finished Jun 22 06:06:19 PM PDT 24
Peak memory 202284 kb
Host smart-817d42a8-354e-45aa-ba4c-a97440c5a1ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444367968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2444367968
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.4248131459
Short name T616
Test name
Test status
Simulation time 448144485 ps
CPU time 1.15 seconds
Started Jun 22 05:53:52 PM PDT 24
Finished Jun 22 05:53:53 PM PDT 24
Peak memory 201920 kb
Host smart-1a2b3f26-d751-4596-9ec1-bb780188a78a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248131459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.4248131459
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.739530920
Short name T184
Test name
Test status
Simulation time 553788904830 ps
CPU time 307.78 seconds
Started Jun 22 05:53:45 PM PDT 24
Finished Jun 22 05:58:54 PM PDT 24
Peak memory 202260 kb
Host smart-26f37b9d-c49f-4a8d-b3ef-131e4f9dd417
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739530920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.739530920
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.133648601
Short name T509
Test name
Test status
Simulation time 347458803114 ps
CPU time 197.83 seconds
Started Jun 22 05:53:46 PM PDT 24
Finished Jun 22 05:57:04 PM PDT 24
Peak memory 202288 kb
Host smart-9503a399-26d1-40ee-84b6-676601930b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133648601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.133648601
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3017257306
Short name T199
Test name
Test status
Simulation time 484889350149 ps
CPU time 251.04 seconds
Started Jun 22 05:53:45 PM PDT 24
Finished Jun 22 05:57:57 PM PDT 24
Peak memory 202184 kb
Host smart-07ad8ed2-d9d0-4abd-afc5-61de58918b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017257306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3017257306
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1146998963
Short name T468
Test name
Test status
Simulation time 489991372158 ps
CPU time 1169.74 seconds
Started Jun 22 05:53:50 PM PDT 24
Finished Jun 22 06:13:20 PM PDT 24
Peak memory 202168 kb
Host smart-ee0c0b00-35ca-4a5f-94d9-9c0dafff61bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146998963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1146998963
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1886596757
Short name T662
Test name
Test status
Simulation time 331942028416 ps
CPU time 80.63 seconds
Started Jun 22 05:53:38 PM PDT 24
Finished Jun 22 05:54:59 PM PDT 24
Peak memory 202196 kb
Host smart-b30eef70-a7fa-42e9-a49b-cc5edba9713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886596757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1886596757
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.759964979
Short name T444
Test name
Test status
Simulation time 327223821221 ps
CPU time 126.73 seconds
Started Jun 22 05:53:42 PM PDT 24
Finished Jun 22 05:55:49 PM PDT 24
Peak memory 202188 kb
Host smart-4beaba91-5ec2-4883-9b07-13aa5285fd6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=759964979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.759964979
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.708526880
Short name T255
Test name
Test status
Simulation time 215363716756 ps
CPU time 82.58 seconds
Started Jun 22 05:53:45 PM PDT 24
Finished Jun 22 05:55:08 PM PDT 24
Peak memory 202168 kb
Host smart-b280522f-5ac4-4762-9afd-744afdcd01b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708526880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.708526880
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.423748946
Short name T636
Test name
Test status
Simulation time 580917621370 ps
CPU time 348.12 seconds
Started Jun 22 05:53:45 PM PDT 24
Finished Jun 22 05:59:34 PM PDT 24
Peak memory 202160 kb
Host smart-571b17f7-2f1a-4687-afb9-5336be5f77d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423748946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.423748946
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2136396411
Short name T66
Test name
Test status
Simulation time 126463724660 ps
CPU time 581.79 seconds
Started Jun 22 05:53:45 PM PDT 24
Finished Jun 22 06:03:28 PM PDT 24
Peak memory 202540 kb
Host smart-84b2c155-2ca3-4756-ba65-adecfca6a5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136396411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2136396411
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.818619056
Short name T721
Test name
Test status
Simulation time 37519923874 ps
CPU time 78.43 seconds
Started Jun 22 05:53:45 PM PDT 24
Finished Jun 22 05:55:03 PM PDT 24
Peak memory 202020 kb
Host smart-1e8988d8-ad9f-4106-85bb-1f01ae5efe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818619056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.818619056
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3529854692
Short name T438
Test name
Test status
Simulation time 5095744908 ps
CPU time 6.45 seconds
Started Jun 22 05:53:44 PM PDT 24
Finished Jun 22 05:53:51 PM PDT 24
Peak memory 202036 kb
Host smart-face937a-6931-45e2-9ebc-c291f4b33154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529854692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3529854692
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1501410623
Short name T117
Test name
Test status
Simulation time 5677793427 ps
CPU time 7.59 seconds
Started Jun 22 05:53:42 PM PDT 24
Finished Jun 22 05:53:49 PM PDT 24
Peak memory 202036 kb
Host smart-aa365621-65ac-42bc-8123-4dbf54632881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501410623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1501410623
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3263831948
Short name T115
Test name
Test status
Simulation time 22372565669 ps
CPU time 59.78 seconds
Started Jun 22 05:53:46 PM PDT 24
Finished Jun 22 05:54:46 PM PDT 24
Peak memory 210908 kb
Host smart-d97d361d-9ad2-4857-a8c4-a192666c4e81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263831948 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3263831948
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3584696145
Short name T676
Test name
Test status
Simulation time 461891637 ps
CPU time 1.66 seconds
Started Jun 22 05:54:25 PM PDT 24
Finished Jun 22 05:54:27 PM PDT 24
Peak memory 201920 kb
Host smart-72d0ff1a-15d8-4b19-9291-b6cef6452e82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584696145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3584696145
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1859877519
Short name T325
Test name
Test status
Simulation time 169812005078 ps
CPU time 197.25 seconds
Started Jun 22 05:54:20 PM PDT 24
Finished Jun 22 05:57:38 PM PDT 24
Peak memory 202220 kb
Host smart-7374aa53-2a36-452a-b3db-96757ec75697
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859877519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1859877519
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2452275422
Short name T168
Test name
Test status
Simulation time 492552976218 ps
CPU time 76.96 seconds
Started Jun 22 05:54:22 PM PDT 24
Finished Jun 22 05:55:39 PM PDT 24
Peak memory 202256 kb
Host smart-254d4730-3986-47ae-837a-7023b705b26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452275422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2452275422
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3098568334
Short name T624
Test name
Test status
Simulation time 489067474889 ps
CPU time 295.02 seconds
Started Jun 22 05:54:25 PM PDT 24
Finished Jun 22 05:59:21 PM PDT 24
Peak memory 202188 kb
Host smart-b2b50e74-7ed7-4be8-aa1b-17c15b763987
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098568334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3098568334
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1626301488
Short name T652
Test name
Test status
Simulation time 164927253407 ps
CPU time 102.65 seconds
Started Jun 22 05:53:51 PM PDT 24
Finished Jun 22 05:55:34 PM PDT 24
Peak memory 202228 kb
Host smart-dd20dada-cdfa-4203-8b1e-94e6a8e79b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626301488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1626301488
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1921854652
Short name T402
Test name
Test status
Simulation time 320968568003 ps
CPU time 697.38 seconds
Started Jun 22 05:53:50 PM PDT 24
Finished Jun 22 06:05:28 PM PDT 24
Peak memory 202160 kb
Host smart-460a7df2-0c75-40a7-aac9-5b9eddfbc3e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921854652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1921854652
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2216402800
Short name T500
Test name
Test status
Simulation time 198546392071 ps
CPU time 26.72 seconds
Started Jun 22 05:54:22 PM PDT 24
Finished Jun 22 05:54:49 PM PDT 24
Peak memory 202276 kb
Host smart-bfbfb64b-6da7-4909-9031-cc8141be289a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216402800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2216402800
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.326085897
Short name T534
Test name
Test status
Simulation time 40864548010 ps
CPU time 35.51 seconds
Started Jun 22 05:54:22 PM PDT 24
Finished Jun 22 05:54:58 PM PDT 24
Peak memory 202036 kb
Host smart-0ab4a226-076a-47cf-b749-dd1dfbd1559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326085897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.326085897
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.625025743
Short name T456
Test name
Test status
Simulation time 3277244483 ps
CPU time 2.56 seconds
Started Jun 22 05:54:20 PM PDT 24
Finished Jun 22 05:54:23 PM PDT 24
Peak memory 202064 kb
Host smart-615415dc-9709-4987-8665-e85854acdb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625025743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.625025743
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1630773736
Short name T568
Test name
Test status
Simulation time 5972789355 ps
CPU time 3.13 seconds
Started Jun 22 05:53:52 PM PDT 24
Finished Jun 22 05:53:55 PM PDT 24
Peak memory 202036 kb
Host smart-ca5f5c02-9d58-4615-824c-a3fd056cbf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630773736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1630773736
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2783959515
Short name T70
Test name
Test status
Simulation time 327285761062 ps
CPU time 1102.48 seconds
Started Jun 22 05:54:22 PM PDT 24
Finished Jun 22 06:12:45 PM PDT 24
Peak memory 210720 kb
Host smart-b3eb122e-ff4a-4d41-a08d-a32a7c4e5402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783959515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2783959515
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4256188946
Short name T49
Test name
Test status
Simulation time 14041898237 ps
CPU time 33.1 seconds
Started Jun 22 05:54:23 PM PDT 24
Finished Jun 22 05:54:56 PM PDT 24
Peak memory 202328 kb
Host smart-bff7232d-a119-41c2-b978-f2834bdf2111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256188946 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.4256188946
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2915944038
Short name T412
Test name
Test status
Simulation time 441678431 ps
CPU time 0.88 seconds
Started Jun 22 05:44:18 PM PDT 24
Finished Jun 22 05:44:19 PM PDT 24
Peak memory 201924 kb
Host smart-60b5c162-d9ef-4fee-9d36-625bb3f25a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915944038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2915944038
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.865390229
Short name T299
Test name
Test status
Simulation time 488250466312 ps
CPU time 272.6 seconds
Started Jun 22 05:44:01 PM PDT 24
Finished Jun 22 05:48:34 PM PDT 24
Peak memory 202200 kb
Host smart-5584ea70-d54a-40f0-9fba-fa5a9dc01e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865390229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.865390229
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2332827932
Short name T695
Test name
Test status
Simulation time 164209939887 ps
CPU time 69.37 seconds
Started Jun 22 05:44:04 PM PDT 24
Finished Jun 22 05:45:13 PM PDT 24
Peak memory 202084 kb
Host smart-c673f9be-cd4c-4d1b-815f-ca69f18e98a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332827932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2332827932
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3845868208
Short name T316
Test name
Test status
Simulation time 164389925374 ps
CPU time 290.34 seconds
Started Jun 22 05:44:01 PM PDT 24
Finished Jun 22 05:48:52 PM PDT 24
Peak memory 202284 kb
Host smart-8b8ae5fe-e398-4ca8-a6a9-6e83ea33ae8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845868208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3845868208
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1714637062
Short name T437
Test name
Test status
Simulation time 487973816192 ps
CPU time 539.72 seconds
Started Jun 22 05:44:04 PM PDT 24
Finished Jun 22 05:53:04 PM PDT 24
Peak memory 202188 kb
Host smart-c6bf69ef-0e01-4488-9e10-5122f57ea2a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714637062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1714637062
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3500775054
Short name T265
Test name
Test status
Simulation time 186917672775 ps
CPU time 102.76 seconds
Started Jun 22 05:44:01 PM PDT 24
Finished Jun 22 05:45:44 PM PDT 24
Peak memory 202256 kb
Host smart-f4bbdf3e-843c-4fa3-9093-da7ce813d6b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500775054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3500775054
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2088541398
Short name T587
Test name
Test status
Simulation time 200495169637 ps
CPU time 174.43 seconds
Started Jun 22 05:44:08 PM PDT 24
Finished Jun 22 05:47:03 PM PDT 24
Peak memory 202084 kb
Host smart-7e1704fa-ad06-4eba-a6e8-a5dce50e2b46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088541398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2088541398
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1620104045
Short name T203
Test name
Test status
Simulation time 100249147763 ps
CPU time 512.94 seconds
Started Jun 22 05:44:21 PM PDT 24
Finished Jun 22 05:52:54 PM PDT 24
Peak memory 202592 kb
Host smart-62746ce2-d1ae-4bba-90c4-aacc76770b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620104045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1620104045
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1296985988
Short name T710
Test name
Test status
Simulation time 27886939922 ps
CPU time 14.86 seconds
Started Jun 22 05:44:21 PM PDT 24
Finished Jun 22 05:44:36 PM PDT 24
Peak memory 202040 kb
Host smart-bcc3e584-1064-4540-aee9-8bb577130e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296985988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1296985988
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2456075384
Short name T673
Test name
Test status
Simulation time 4792027072 ps
CPU time 11.98 seconds
Started Jun 22 05:44:19 PM PDT 24
Finished Jun 22 05:44:31 PM PDT 24
Peak memory 202060 kb
Host smart-5f866be7-d2d2-4e98-b7d0-945b2e56dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456075384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2456075384
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1346248119
Short name T102
Test name
Test status
Simulation time 3975659460 ps
CPU time 9.5 seconds
Started Jun 22 05:44:16 PM PDT 24
Finished Jun 22 05:44:26 PM PDT 24
Peak memory 217768 kb
Host smart-c6db00ae-16a6-4ee5-bfc6-bc86b3cd22f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346248119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1346248119
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1152355225
Short name T378
Test name
Test status
Simulation time 6006184519 ps
CPU time 2.8 seconds
Started Jun 22 05:44:00 PM PDT 24
Finished Jun 22 05:44:03 PM PDT 24
Peak memory 202036 kb
Host smart-1a820d4e-5615-4229-88d5-9a4fde368082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152355225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1152355225
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.78174856
Short name T638
Test name
Test status
Simulation time 291200107759 ps
CPU time 717.89 seconds
Started Jun 22 05:44:18 PM PDT 24
Finished Jun 22 05:56:16 PM PDT 24
Peak memory 202560 kb
Host smart-0ca61882-f1f6-435c-8e59-b5e8fc713e16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78174856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.78174856
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.770997610
Short name T762
Test name
Test status
Simulation time 564514825 ps
CPU time 0.79 seconds
Started Jun 22 05:54:25 PM PDT 24
Finished Jun 22 05:54:27 PM PDT 24
Peak memory 201920 kb
Host smart-4ee015b8-2244-42ae-b9c8-8e926f81f362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770997610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.770997610
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3917876558
Short name T777
Test name
Test status
Simulation time 286937427917 ps
CPU time 486.52 seconds
Started Jun 22 05:54:24 PM PDT 24
Finished Jun 22 06:02:31 PM PDT 24
Peak memory 202228 kb
Host smart-a71d3e66-7f37-431b-89ec-7fd443575d4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917876558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3917876558
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2272105391
Short name T237
Test name
Test status
Simulation time 349577994695 ps
CPU time 218.94 seconds
Started Jun 22 05:54:25 PM PDT 24
Finished Jun 22 05:58:05 PM PDT 24
Peak memory 202188 kb
Host smart-bc0d54f4-e281-4b57-b29e-f57b89ff2b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272105391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2272105391
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1353094303
Short name T284
Test name
Test status
Simulation time 490519488493 ps
CPU time 1096.11 seconds
Started Jun 22 05:54:24 PM PDT 24
Finished Jun 22 06:12:41 PM PDT 24
Peak memory 202184 kb
Host smart-72820429-52ce-41ad-85f1-3b0a31fe5e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353094303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1353094303
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1732248464
Short name T524
Test name
Test status
Simulation time 332421821879 ps
CPU time 179.32 seconds
Started Jun 22 05:54:27 PM PDT 24
Finished Jun 22 05:57:26 PM PDT 24
Peak memory 202196 kb
Host smart-085d58b4-c5cd-493e-9b46-1f4cbfdd9436
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732248464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1732248464
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1653201192
Short name T221
Test name
Test status
Simulation time 324940300192 ps
CPU time 275.79 seconds
Started Jun 22 05:54:25 PM PDT 24
Finished Jun 22 05:59:01 PM PDT 24
Peak memory 202240 kb
Host smart-cd54813b-c97a-4ec6-9276-9d869ddc694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653201192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1653201192
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.759439659
Short name T688
Test name
Test status
Simulation time 166213281787 ps
CPU time 192.99 seconds
Started Jun 22 05:54:25 PM PDT 24
Finished Jun 22 05:57:38 PM PDT 24
Peak memory 202184 kb
Host smart-85e36d50-fc23-41c9-a4ae-c027a3b28c66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=759439659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.759439659
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2470337593
Short name T643
Test name
Test status
Simulation time 185243518984 ps
CPU time 417.24 seconds
Started Jun 22 05:54:24 PM PDT 24
Finished Jun 22 06:01:22 PM PDT 24
Peak memory 202192 kb
Host smart-e63ca9a0-b456-4bda-b4b9-a18c373bc877
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470337593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2470337593
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1559976366
Short name T387
Test name
Test status
Simulation time 208460700207 ps
CPU time 296.35 seconds
Started Jun 22 05:54:26 PM PDT 24
Finished Jun 22 05:59:23 PM PDT 24
Peak memory 202204 kb
Host smart-78773e3d-16b3-4913-9478-9404218855ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559976366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1559976366
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4006907886
Short name T213
Test name
Test status
Simulation time 98429938674 ps
CPU time 384.2 seconds
Started Jun 22 05:54:25 PM PDT 24
Finished Jun 22 06:00:50 PM PDT 24
Peak memory 202604 kb
Host smart-0e2a781d-d0b8-4099-ae9e-66d5143ef80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006907886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4006907886
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4208358421
Short name T672
Test name
Test status
Simulation time 44024365607 ps
CPU time 93.25 seconds
Started Jun 22 05:54:29 PM PDT 24
Finished Jun 22 05:56:03 PM PDT 24
Peak memory 202024 kb
Host smart-8b6b945b-a1ba-417c-bd7e-3b9bd70b4374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208358421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4208358421
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1716740262
Short name T490
Test name
Test status
Simulation time 2979780839 ps
CPU time 7.1 seconds
Started Jun 22 05:54:27 PM PDT 24
Finished Jun 22 05:54:34 PM PDT 24
Peak memory 202012 kb
Host smart-b53f4ac5-b3a6-4366-9894-8e9196216132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716740262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1716740262
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3737617436
Short name T435
Test name
Test status
Simulation time 5590542616 ps
CPU time 13.94 seconds
Started Jun 22 05:54:25 PM PDT 24
Finished Jun 22 05:54:39 PM PDT 24
Peak memory 202028 kb
Host smart-cb16a8f6-209e-4fb1-80a8-20113c96e10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737617436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3737617436
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3069796257
Short name T556
Test name
Test status
Simulation time 314123850866 ps
CPU time 129.39 seconds
Started Jun 22 05:54:28 PM PDT 24
Finished Jun 22 05:56:38 PM PDT 24
Peak memory 211556 kb
Host smart-4f16b462-6f28-426e-9770-04300c87bdc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069796257 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3069796257
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.4193595162
Short name T526
Test name
Test status
Simulation time 297800535 ps
CPU time 1.33 seconds
Started Jun 22 05:54:34 PM PDT 24
Finished Jun 22 05:54:36 PM PDT 24
Peak memory 201884 kb
Host smart-050f1f24-d484-4f6d-a3cd-82054ddac742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193595162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.4193595162
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2657546266
Short name T331
Test name
Test status
Simulation time 543712011909 ps
CPU time 720.81 seconds
Started Jun 22 05:54:29 PM PDT 24
Finished Jun 22 06:06:30 PM PDT 24
Peak memory 202296 kb
Host smart-3bde3703-4115-44a2-920e-b9158ba4e6ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657546266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2657546266
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.4287486774
Short name T241
Test name
Test status
Simulation time 168624070958 ps
CPU time 418.7 seconds
Started Jun 22 05:54:28 PM PDT 24
Finished Jun 22 06:01:28 PM PDT 24
Peak memory 202220 kb
Host smart-2d90efe9-790b-4f66-a299-cdd107b3b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287486774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.4287486774
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.746461417
Short name T525
Test name
Test status
Simulation time 158112085840 ps
CPU time 361.14 seconds
Started Jun 22 05:54:27 PM PDT 24
Finished Jun 22 06:00:28 PM PDT 24
Peak memory 202220 kb
Host smart-beb38f01-ea9c-4db0-b49e-064ae9f202e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746461417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.746461417
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2942754393
Short name T592
Test name
Test status
Simulation time 167889419890 ps
CPU time 176.19 seconds
Started Jun 22 05:54:28 PM PDT 24
Finished Jun 22 05:57:25 PM PDT 24
Peak memory 202184 kb
Host smart-b0e36b84-7a0d-45e1-9a3c-ddd80ca003c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942754393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2942754393
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3938210985
Short name T217
Test name
Test status
Simulation time 326832227609 ps
CPU time 379.5 seconds
Started Jun 22 05:54:30 PM PDT 24
Finished Jun 22 06:00:50 PM PDT 24
Peak memory 202224 kb
Host smart-28f4f7bf-200d-4f9a-8faa-6278aab6392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938210985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3938210985
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2075709122
Short name T472
Test name
Test status
Simulation time 509732567810 ps
CPU time 1043.74 seconds
Started Jun 22 05:54:26 PM PDT 24
Finished Jun 22 06:11:50 PM PDT 24
Peak memory 202196 kb
Host smart-85bca298-d705-4524-8b13-4b6b5856b478
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075709122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2075709122
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.226343752
Short name T697
Test name
Test status
Simulation time 388271696224 ps
CPU time 875.18 seconds
Started Jun 22 05:54:26 PM PDT 24
Finished Jun 22 06:09:02 PM PDT 24
Peak memory 202172 kb
Host smart-15278b3c-9553-4448-a892-7d076fd6fa27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226343752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.226343752
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2681087424
Short name T476
Test name
Test status
Simulation time 619833110336 ps
CPU time 1466.96 seconds
Started Jun 22 05:54:28 PM PDT 24
Finished Jun 22 06:18:55 PM PDT 24
Peak memory 202272 kb
Host smart-479ee6d5-8c90-4011-be35-1de110a29ad6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681087424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2681087424
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3586811824
Short name T363
Test name
Test status
Simulation time 114865877357 ps
CPU time 604.76 seconds
Started Jun 22 05:54:32 PM PDT 24
Finished Jun 22 06:04:38 PM PDT 24
Peak memory 202520 kb
Host smart-e3957c36-2464-4aad-b4c6-9b2d3207524e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586811824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3586811824
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1654834486
Short name T712
Test name
Test status
Simulation time 40623188482 ps
CPU time 90.33 seconds
Started Jun 22 05:54:33 PM PDT 24
Finished Jun 22 05:56:03 PM PDT 24
Peak memory 202040 kb
Host smart-236bf675-43c3-458c-9419-46f2d81a06c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654834486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1654834486
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3131469507
Short name T386
Test name
Test status
Simulation time 3862032878 ps
CPU time 10.2 seconds
Started Jun 22 05:54:30 PM PDT 24
Finished Jun 22 05:54:41 PM PDT 24
Peak memory 202016 kb
Host smart-61d21733-d1e3-448c-a105-7ac5fbd8d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131469507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3131469507
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.676818264
Short name T623
Test name
Test status
Simulation time 5706126265 ps
CPU time 12.52 seconds
Started Jun 22 05:54:30 PM PDT 24
Finished Jun 22 05:54:43 PM PDT 24
Peak memory 202012 kb
Host smart-ea7ff42a-d72c-4db0-a258-627aad0a3124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676818264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.676818264
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3040484357
Short name T15
Test name
Test status
Simulation time 44784790876 ps
CPU time 48.04 seconds
Started Jun 22 05:54:32 PM PDT 24
Finished Jun 22 05:55:20 PM PDT 24
Peak memory 202816 kb
Host smart-e05948cf-cfbe-4d7a-af60-bf8ccfff840f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040484357 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3040484357
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3597237370
Short name T594
Test name
Test status
Simulation time 500652069 ps
CPU time 0.86 seconds
Started Jun 22 05:54:46 PM PDT 24
Finished Jun 22 05:54:48 PM PDT 24
Peak memory 201892 kb
Host smart-6b5a7045-7153-4090-9f98-d9419a9ba19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597237370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3597237370
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3234599040
Short name T634
Test name
Test status
Simulation time 500186390188 ps
CPU time 1205.96 seconds
Started Jun 22 05:54:36 PM PDT 24
Finished Jun 22 06:14:42 PM PDT 24
Peak memory 202184 kb
Host smart-55ffdc38-4a3b-46d9-97f2-5b199025f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234599040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3234599040
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2727788385
Short name T734
Test name
Test status
Simulation time 326146095247 ps
CPU time 754.5 seconds
Started Jun 22 05:54:35 PM PDT 24
Finished Jun 22 06:07:10 PM PDT 24
Peak memory 202192 kb
Host smart-781173fc-9e5a-412c-b502-a5959d9ea808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727788385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2727788385
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1287920562
Short name T684
Test name
Test status
Simulation time 330797128554 ps
CPU time 789.63 seconds
Started Jun 22 05:54:34 PM PDT 24
Finished Jun 22 06:07:44 PM PDT 24
Peak memory 202500 kb
Host smart-904e4585-6029-4510-b26c-4c4cd32d7e35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287920562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1287920562
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3873137029
Short name T732
Test name
Test status
Simulation time 323402615015 ps
CPU time 725.42 seconds
Started Jun 22 05:54:29 PM PDT 24
Finished Jun 22 06:06:35 PM PDT 24
Peak memory 202304 kb
Host smart-dd4f6e31-0331-46cc-9c64-061b146c9b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873137029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3873137029
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3299500442
Short name T406
Test name
Test status
Simulation time 159527087811 ps
CPU time 83.69 seconds
Started Jun 22 05:54:32 PM PDT 24
Finished Jun 22 05:55:55 PM PDT 24
Peak memory 202156 kb
Host smart-31ba5c11-9aea-4809-8bd3-d78fd36b16c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299500442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3299500442
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1790134734
Short name T462
Test name
Test status
Simulation time 544374287585 ps
CPU time 613.15 seconds
Started Jun 22 05:54:36 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 202204 kb
Host smart-72bfaf3d-314a-47c7-9cc1-f2bab5f87db2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790134734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1790134734
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3441013171
Short name T728
Test name
Test status
Simulation time 187257319649 ps
CPU time 33.74 seconds
Started Jun 22 05:54:35 PM PDT 24
Finished Jun 22 05:55:09 PM PDT 24
Peak memory 202276 kb
Host smart-dd3f45c8-9c47-48d3-aed5-dee3efd6e433
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441013171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3441013171
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1444363529
Short name T559
Test name
Test status
Simulation time 129082294599 ps
CPU time 553.71 seconds
Started Jun 22 05:54:42 PM PDT 24
Finished Jun 22 06:03:56 PM PDT 24
Peak memory 202520 kb
Host smart-7f9cf0fd-10cb-4378-bca4-468aadc9265d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444363529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1444363529
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3494953902
Short name T736
Test name
Test status
Simulation time 39648069573 ps
CPU time 44.69 seconds
Started Jun 22 05:54:33 PM PDT 24
Finished Jun 22 05:55:18 PM PDT 24
Peak memory 201984 kb
Host smart-7b2e54fd-51a0-4772-ba3f-7a2ddf0fed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494953902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3494953902
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1706754280
Short name T532
Test name
Test status
Simulation time 4415029536 ps
CPU time 3.39 seconds
Started Jun 22 05:54:34 PM PDT 24
Finished Jun 22 05:54:38 PM PDT 24
Peak memory 202036 kb
Host smart-202ff6cf-14bb-47b5-98ba-602895c81821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706754280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1706754280
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2753100208
Short name T591
Test name
Test status
Simulation time 5582432871 ps
CPU time 4.36 seconds
Started Jun 22 05:54:32 PM PDT 24
Finished Jun 22 05:54:37 PM PDT 24
Peak memory 202016 kb
Host smart-bde4db88-c325-4d97-bc4a-7237ec55bf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753100208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2753100208
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2349375236
Short name T201
Test name
Test status
Simulation time 350665383260 ps
CPU time 208.66 seconds
Started Jun 22 05:54:40 PM PDT 24
Finished Jun 22 05:58:09 PM PDT 24
Peak memory 202204 kb
Host smart-627fea16-4103-457d-b5c8-d83463b0ad27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349375236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2349375236
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1736289340
Short name T696
Test name
Test status
Simulation time 24667796744 ps
CPU time 57.19 seconds
Started Jun 22 05:54:39 PM PDT 24
Finished Jun 22 05:55:37 PM PDT 24
Peak memory 210612 kb
Host smart-f463e7b2-a213-4738-8252-87d56f766870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736289340 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1736289340
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3636339278
Short name T510
Test name
Test status
Simulation time 373865780 ps
CPU time 0.72 seconds
Started Jun 22 05:54:53 PM PDT 24
Finished Jun 22 05:54:54 PM PDT 24
Peak memory 201904 kb
Host smart-51c9ae76-6414-43b7-b933-4badc15a9571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636339278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3636339278
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1940691811
Short name T260
Test name
Test status
Simulation time 160692459580 ps
CPU time 135.67 seconds
Started Jun 22 05:54:56 PM PDT 24
Finished Jun 22 05:57:12 PM PDT 24
Peak memory 202296 kb
Host smart-6f9caad1-bd2e-43a8-8ae1-a7553867a5e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940691811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1940691811
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3117906749
Short name T227
Test name
Test status
Simulation time 346475577530 ps
CPU time 441.6 seconds
Started Jun 22 05:54:53 PM PDT 24
Finished Jun 22 06:02:15 PM PDT 24
Peak memory 202220 kb
Host smart-195d6f75-d7c9-478f-aa9c-817b6c720e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117906749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3117906749
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.725204271
Short name T122
Test name
Test status
Simulation time 164524357931 ps
CPU time 347.18 seconds
Started Jun 22 05:54:47 PM PDT 24
Finished Jun 22 06:00:35 PM PDT 24
Peak memory 202224 kb
Host smart-2bb3674e-57a7-4f78-b6f2-ee0c7ef6725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725204271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.725204271
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3560465954
Short name T450
Test name
Test status
Simulation time 331140116426 ps
CPU time 760.89 seconds
Started Jun 22 05:54:46 PM PDT 24
Finished Jun 22 06:07:28 PM PDT 24
Peak memory 202156 kb
Host smart-f198f412-92f1-481e-85be-7f153e040b70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560465954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3560465954
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1593034846
Short name T766
Test name
Test status
Simulation time 320222394265 ps
CPU time 357.78 seconds
Started Jun 22 05:54:48 PM PDT 24
Finished Jun 22 06:00:46 PM PDT 24
Peak memory 202184 kb
Host smart-59c8b1d4-da8e-411e-94bd-66b06136920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593034846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1593034846
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.4275333839
Short name T404
Test name
Test status
Simulation time 318375334294 ps
CPU time 87.7 seconds
Started Jun 22 05:54:46 PM PDT 24
Finished Jun 22 05:56:14 PM PDT 24
Peak memory 202196 kb
Host smart-2daddabf-a855-4ac8-8d06-a1b83abd993e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275333839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.4275333839
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2453353320
Short name T60
Test name
Test status
Simulation time 410386501638 ps
CPU time 62.65 seconds
Started Jun 22 05:54:46 PM PDT 24
Finished Jun 22 05:55:50 PM PDT 24
Peak memory 202136 kb
Host smart-387699ec-ded3-4836-8391-cd3e1d2c8674
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453353320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2453353320
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2822990523
Short name T384
Test name
Test status
Simulation time 26278501977 ps
CPU time 16.46 seconds
Started Jun 22 05:54:55 PM PDT 24
Finished Jun 22 05:55:11 PM PDT 24
Peak memory 202024 kb
Host smart-0ba8153f-6646-4780-9d02-17658c863305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822990523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2822990523
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2909657468
Short name T682
Test name
Test status
Simulation time 3994198869 ps
CPU time 4.39 seconds
Started Jun 22 05:54:54 PM PDT 24
Finished Jun 22 05:54:58 PM PDT 24
Peak memory 202016 kb
Host smart-5e506d77-570e-43f4-a1cf-4ce96eb76f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909657468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2909657468
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2302664351
Short name T577
Test name
Test status
Simulation time 5574935624 ps
CPU time 14.16 seconds
Started Jun 22 05:54:48 PM PDT 24
Finished Jun 22 05:55:02 PM PDT 24
Peak memory 202000 kb
Host smart-b4ad292b-f316-4d6a-a813-655772c02d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302664351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2302664351
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2987935837
Short name T738
Test name
Test status
Simulation time 350357622725 ps
CPU time 220.92 seconds
Started Jun 22 05:54:55 PM PDT 24
Finished Jun 22 05:58:37 PM PDT 24
Peak memory 202188 kb
Host smart-14798d07-a679-47a0-b8a5-27716da704dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987935837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2987935837
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2261659185
Short name T442
Test name
Test status
Simulation time 141233049387 ps
CPU time 208.7 seconds
Started Jun 22 05:54:55 PM PDT 24
Finished Jun 22 05:58:25 PM PDT 24
Peak memory 210860 kb
Host smart-9cc6b3dd-e021-49c7-848c-6899d589036e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261659185 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2261659185
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.361870584
Short name T361
Test name
Test status
Simulation time 505114045 ps
CPU time 0.87 seconds
Started Jun 22 05:55:10 PM PDT 24
Finished Jun 22 05:55:11 PM PDT 24
Peak memory 201892 kb
Host smart-ca39a097-fe2e-40a1-a05f-4c2109b23a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361870584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.361870584
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2583662563
Short name T286
Test name
Test status
Simulation time 165785898621 ps
CPU time 98.51 seconds
Started Jun 22 05:55:02 PM PDT 24
Finished Jun 22 05:56:41 PM PDT 24
Peak memory 202196 kb
Host smart-0944c686-46c3-453e-b3fb-87001c63133e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583662563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2583662563
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2898890462
Short name T740
Test name
Test status
Simulation time 504067386975 ps
CPU time 312.05 seconds
Started Jun 22 05:55:05 PM PDT 24
Finished Jun 22 06:00:18 PM PDT 24
Peak memory 202436 kb
Host smart-5e0985b2-30f3-4a01-9efb-4c2ecb9dfa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898890462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2898890462
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2092704487
Short name T236
Test name
Test status
Simulation time 491207386933 ps
CPU time 1223.54 seconds
Started Jun 22 05:55:00 PM PDT 24
Finished Jun 22 06:15:24 PM PDT 24
Peak memory 202224 kb
Host smart-77c80b76-28a6-4910-84bb-ec7e315691e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092704487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2092704487
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.470882295
Short name T549
Test name
Test status
Simulation time 160902569999 ps
CPU time 388.63 seconds
Started Jun 22 05:55:03 PM PDT 24
Finished Jun 22 06:01:32 PM PDT 24
Peak memory 202172 kb
Host smart-69f2f9ac-9c81-499c-9cad-4af53e631c48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=470882295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.470882295
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2455066552
Short name T12
Test name
Test status
Simulation time 331127162311 ps
CPU time 822.94 seconds
Started Jun 22 05:54:55 PM PDT 24
Finished Jun 22 06:08:39 PM PDT 24
Peak memory 202304 kb
Host smart-13b4c29f-23df-4792-b6c1-491c75fd809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455066552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2455066552
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.820975869
Short name T11
Test name
Test status
Simulation time 321265868812 ps
CPU time 761.46 seconds
Started Jun 22 05:55:05 PM PDT 24
Finished Jun 22 06:07:47 PM PDT 24
Peak memory 202324 kb
Host smart-892036aa-9e76-4c34-9687-b17ce967e6a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=820975869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.820975869
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2458693429
Short name T322
Test name
Test status
Simulation time 670451304392 ps
CPU time 663.06 seconds
Started Jun 22 05:55:01 PM PDT 24
Finished Jun 22 06:06:05 PM PDT 24
Peak memory 202204 kb
Host smart-39eb80b2-6cdc-4897-bb78-829ca4e2ca45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458693429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2458693429
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1451392254
Short name T454
Test name
Test status
Simulation time 200421567288 ps
CPU time 109.86 seconds
Started Jun 22 05:55:06 PM PDT 24
Finished Jun 22 05:56:57 PM PDT 24
Peak memory 202184 kb
Host smart-8a80bf40-d2e3-4ecd-ae23-b1f351f5a20b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451392254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1451392254
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4244306979
Short name T67
Test name
Test status
Simulation time 57524039342 ps
CPU time 336.63 seconds
Started Jun 22 05:55:09 PM PDT 24
Finished Jun 22 06:00:46 PM PDT 24
Peak memory 202488 kb
Host smart-f31549f5-f7dc-4dca-959f-af5acd01be88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244306979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4244306979
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.391425216
Short name T533
Test name
Test status
Simulation time 35028172877 ps
CPU time 71.92 seconds
Started Jun 22 05:55:10 PM PDT 24
Finished Jun 22 05:56:23 PM PDT 24
Peak memory 202020 kb
Host smart-556f3c76-f05a-431e-af7d-d72e2bbe8638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391425216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.391425216
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2723611596
Short name T501
Test name
Test status
Simulation time 3154250978 ps
CPU time 8.08 seconds
Started Jun 22 05:55:02 PM PDT 24
Finished Jun 22 05:55:10 PM PDT 24
Peak memory 202032 kb
Host smart-c0d548b5-2732-4286-9585-0157c743dafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723611596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2723611596
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3973633536
Short name T744
Test name
Test status
Simulation time 5993652029 ps
CPU time 7.15 seconds
Started Jun 22 05:54:54 PM PDT 24
Finished Jun 22 05:55:02 PM PDT 24
Peak memory 202036 kb
Host smart-2ed17de3-07ad-4e6d-b093-0aa96ab94a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973633536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3973633536
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2816300712
Short name T207
Test name
Test status
Simulation time 529553066189 ps
CPU time 1656.9 seconds
Started Jun 22 05:55:11 PM PDT 24
Finished Jun 22 06:22:48 PM PDT 24
Peak memory 202520 kb
Host smart-11307675-bba2-4367-b7c2-42d68630d99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816300712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2816300712
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.581411944
Short name T105
Test name
Test status
Simulation time 60344660357 ps
CPU time 35.84 seconds
Started Jun 22 05:55:12 PM PDT 24
Finished Jun 22 05:55:48 PM PDT 24
Peak memory 210540 kb
Host smart-9c419e22-80f5-47e8-bcff-1f6c4d99e5c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581411944 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.581411944
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2639963815
Short name T43
Test name
Test status
Simulation time 327742869 ps
CPU time 1.34 seconds
Started Jun 22 05:55:28 PM PDT 24
Finished Jun 22 05:55:30 PM PDT 24
Peak memory 201920 kb
Host smart-4e3783bc-9b33-4dcd-ad09-071a47dc50e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639963815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2639963815
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1366666933
Short name T722
Test name
Test status
Simulation time 167152118701 ps
CPU time 145.92 seconds
Started Jun 22 05:55:24 PM PDT 24
Finished Jun 22 05:57:50 PM PDT 24
Peak memory 202260 kb
Host smart-0f33d343-9fa5-4280-857b-f681e39d8070
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366666933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1366666933
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.628397110
Short name T224
Test name
Test status
Simulation time 334553854413 ps
CPU time 818.28 seconds
Started Jun 22 05:55:10 PM PDT 24
Finished Jun 22 06:08:49 PM PDT 24
Peak memory 202204 kb
Host smart-d2892e66-326e-4f7b-a488-d89396a0f2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628397110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.628397110
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2051753973
Short name T515
Test name
Test status
Simulation time 325033748201 ps
CPU time 769.91 seconds
Started Jun 22 05:55:12 PM PDT 24
Finished Jun 22 06:08:02 PM PDT 24
Peak memory 202252 kb
Host smart-d7c50cd4-4307-4ad5-9a5e-44773b3baef4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051753973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2051753973
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1183415705
Short name T544
Test name
Test status
Simulation time 329676844856 ps
CPU time 738.07 seconds
Started Jun 22 05:55:14 PM PDT 24
Finished Jun 22 06:07:32 PM PDT 24
Peak memory 202420 kb
Host smart-d7493c0f-cd71-43ff-96e0-10bc31349f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183415705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1183415705
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2655584158
Short name T467
Test name
Test status
Simulation time 499505001018 ps
CPU time 546.09 seconds
Started Jun 22 05:55:14 PM PDT 24
Finished Jun 22 06:04:20 PM PDT 24
Peak memory 202396 kb
Host smart-fe103111-52e2-4880-ba32-ed35009349d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655584158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2655584158
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3088940720
Short name T519
Test name
Test status
Simulation time 590956116780 ps
CPU time 599.66 seconds
Started Jun 22 05:55:20 PM PDT 24
Finished Jun 22 06:05:20 PM PDT 24
Peak memory 202264 kb
Host smart-c9ed6516-0aab-4fc7-923e-c45d966a618a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088940720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3088940720
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3215047668
Short name T71
Test name
Test status
Simulation time 77657078853 ps
CPU time 320.28 seconds
Started Jun 22 05:55:19 PM PDT 24
Finished Jun 22 06:00:40 PM PDT 24
Peak memory 202524 kb
Host smart-744d0df7-9b6d-4e2e-aba8-7170ab06032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215047668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3215047668
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.741738925
Short name T56
Test name
Test status
Simulation time 28681274081 ps
CPU time 62.82 seconds
Started Jun 22 05:55:20 PM PDT 24
Finished Jun 22 05:56:23 PM PDT 24
Peak memory 201936 kb
Host smart-d83e77a0-1f42-498f-922b-66756f701a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741738925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.741738925
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2526406278
Short name T645
Test name
Test status
Simulation time 4757190943 ps
CPU time 11.33 seconds
Started Jun 22 05:55:18 PM PDT 24
Finished Jun 22 05:55:29 PM PDT 24
Peak memory 202036 kb
Host smart-54ef8517-e06e-48b0-944c-815853e32263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526406278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2526406278
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3195449746
Short name T612
Test name
Test status
Simulation time 5895790396 ps
CPU time 4.32 seconds
Started Jun 22 05:55:11 PM PDT 24
Finished Jun 22 05:55:15 PM PDT 24
Peak memory 202036 kb
Host smart-5e67dab0-3ae8-4239-9985-2665824a54d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195449746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3195449746
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.786923812
Short name T72
Test name
Test status
Simulation time 334659050192 ps
CPU time 517.23 seconds
Started Jun 22 05:55:19 PM PDT 24
Finished Jun 22 06:03:56 PM PDT 24
Peak memory 202196 kb
Host smart-3c684ad7-21d2-4fcd-91c2-fe415277b658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786923812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
786923812
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1908681973
Short name T418
Test name
Test status
Simulation time 459529531 ps
CPU time 0.86 seconds
Started Jun 22 05:55:35 PM PDT 24
Finished Jun 22 05:55:36 PM PDT 24
Peak memory 201920 kb
Host smart-2657a61b-30c7-4970-ba72-1f68b96e550f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908681973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1908681973
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3502963530
Short name T261
Test name
Test status
Simulation time 201269663004 ps
CPU time 490.81 seconds
Started Jun 22 05:55:27 PM PDT 24
Finished Jun 22 06:03:39 PM PDT 24
Peak memory 202216 kb
Host smart-24862b86-d2c8-4d79-a18f-38612865cbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502963530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3502963530
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2902905085
Short name T245
Test name
Test status
Simulation time 164252317295 ps
CPU time 97.76 seconds
Started Jun 22 05:55:28 PM PDT 24
Finished Jun 22 05:57:06 PM PDT 24
Peak memory 202224 kb
Host smart-427cae5b-9c85-4062-b318-b06b8110ab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902905085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2902905085
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3331553841
Short name T448
Test name
Test status
Simulation time 168687971494 ps
CPU time 389.08 seconds
Started Jun 22 05:55:30 PM PDT 24
Finished Jun 22 06:02:00 PM PDT 24
Peak memory 202168 kb
Host smart-fa29bc83-9fde-4b48-9cb9-497c413e5aea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331553841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3331553841
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3350494065
Short name T585
Test name
Test status
Simulation time 329985779400 ps
CPU time 188.77 seconds
Started Jun 22 05:55:26 PM PDT 24
Finished Jun 22 05:58:35 PM PDT 24
Peak memory 202304 kb
Host smart-757cb00b-6369-42b9-b14b-e5890774a440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350494065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3350494065
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.59344387
Short name T503
Test name
Test status
Simulation time 499757773672 ps
CPU time 318.58 seconds
Started Jun 22 05:55:27 PM PDT 24
Finished Jun 22 06:00:46 PM PDT 24
Peak memory 202176 kb
Host smart-ec478001-f5a4-45af-a4ba-e874d64d804d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=59344387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed
.59344387
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2945032727
Short name T162
Test name
Test status
Simulation time 519545152171 ps
CPU time 301.1 seconds
Started Jun 22 05:55:31 PM PDT 24
Finished Jun 22 06:00:32 PM PDT 24
Peak memory 202272 kb
Host smart-18f1c3d0-b521-47f8-9cdf-a680e1944dad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945032727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2945032727
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2902010765
Short name T113
Test name
Test status
Simulation time 405498522237 ps
CPU time 458.26 seconds
Started Jun 22 05:55:30 PM PDT 24
Finished Jun 22 06:03:09 PM PDT 24
Peak memory 202184 kb
Host smart-ef011757-1389-438b-8aa6-b88e4eec7d51
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902010765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2902010765
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.278810295
Short name T208
Test name
Test status
Simulation time 82598226721 ps
CPU time 306.74 seconds
Started Jun 22 05:55:37 PM PDT 24
Finished Jun 22 06:00:44 PM PDT 24
Peak memory 202592 kb
Host smart-98aa8cae-73f5-4b97-a076-d97614373b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278810295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.278810295
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3551455320
Short name T780
Test name
Test status
Simulation time 41560422656 ps
CPU time 19.86 seconds
Started Jun 22 05:55:27 PM PDT 24
Finished Jun 22 05:55:47 PM PDT 24
Peak memory 202024 kb
Host smart-18ded85c-9161-49f7-a90f-91911bb851e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551455320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3551455320
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3401107004
Short name T512
Test name
Test status
Simulation time 3704245848 ps
CPU time 4.88 seconds
Started Jun 22 05:55:27 PM PDT 24
Finished Jun 22 05:55:33 PM PDT 24
Peak memory 202024 kb
Host smart-4a9ec418-a21e-4e2f-80ab-4892470831a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401107004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3401107004
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1609656571
Short name T748
Test name
Test status
Simulation time 5826114423 ps
CPU time 13.49 seconds
Started Jun 22 05:55:28 PM PDT 24
Finished Jun 22 05:55:42 PM PDT 24
Peak memory 201980 kb
Host smart-50a3f46e-3ec1-429d-851d-fa9a020fba4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609656571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1609656571
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1140623440
Short name T339
Test name
Test status
Simulation time 326383566804 ps
CPU time 778.27 seconds
Started Jun 22 05:55:34 PM PDT 24
Finished Jun 22 06:08:33 PM PDT 24
Peak memory 202136 kb
Host smart-7cdaac2c-b35e-4e51-bd74-54f9c07e6523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140623440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1140623440
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1922156496
Short name T529
Test name
Test status
Simulation time 177082409551 ps
CPU time 262.69 seconds
Started Jun 22 05:55:38 PM PDT 24
Finished Jun 22 06:00:01 PM PDT 24
Peak memory 210856 kb
Host smart-5ae4b25f-9f0f-42ca-840b-cea41b9f1268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922156496 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1922156496
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3509171184
Short name T427
Test name
Test status
Simulation time 324315069 ps
CPU time 1.39 seconds
Started Jun 22 05:55:39 PM PDT 24
Finished Jun 22 05:55:41 PM PDT 24
Peak memory 201904 kb
Host smart-3ca77b35-a418-4835-9712-8591a30720d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509171184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3509171184
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3430327728
Short name T277
Test name
Test status
Simulation time 499479291203 ps
CPU time 287.38 seconds
Started Jun 22 05:55:35 PM PDT 24
Finished Jun 22 06:00:23 PM PDT 24
Peak memory 202200 kb
Host smart-0537dbf5-f3be-433c-8586-0ecdbb84e37a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430327728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3430327728
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2703149709
Short name T764
Test name
Test status
Simulation time 490094730860 ps
CPU time 556.16 seconds
Started Jun 22 05:55:42 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 202192 kb
Host smart-968d68ef-97a9-48fb-93cc-af0f9e984e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703149709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2703149709
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2349817408
Short name T631
Test name
Test status
Simulation time 498190609861 ps
CPU time 1180.87 seconds
Started Jun 22 05:55:37 PM PDT 24
Finished Jun 22 06:15:18 PM PDT 24
Peak memory 202268 kb
Host smart-fc8cdd3e-f8c3-4208-ba48-dd2b21e27cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349817408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2349817408
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2708624160
Short name T183
Test name
Test status
Simulation time 484019181548 ps
CPU time 309.8 seconds
Started Jun 22 05:55:36 PM PDT 24
Finished Jun 22 06:00:46 PM PDT 24
Peak memory 202252 kb
Host smart-c4ae3aef-c1cb-4425-93a1-aae646e7f71a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708624160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2708624160
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1017705853
Short name T187
Test name
Test status
Simulation time 327509078266 ps
CPU time 149.58 seconds
Started Jun 22 05:55:38 PM PDT 24
Finished Jun 22 05:58:08 PM PDT 24
Peak memory 202208 kb
Host smart-7d68cb06-191f-4b48-b231-e2fe3f2b9cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017705853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1017705853
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.778992161
Short name T752
Test name
Test status
Simulation time 504622132482 ps
CPU time 1069.2 seconds
Started Jun 22 05:55:36 PM PDT 24
Finished Jun 22 06:13:26 PM PDT 24
Peak memory 202240 kb
Host smart-10af6688-6c0d-47e9-909e-39138fd1fbd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=778992161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.778992161
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.4212463413
Short name T35
Test name
Test status
Simulation time 186173059975 ps
CPU time 291.32 seconds
Started Jun 22 05:55:36 PM PDT 24
Finished Jun 22 06:00:28 PM PDT 24
Peak memory 202188 kb
Host smart-702e34a6-0e89-4734-9b3e-b92941d07b59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212463413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.4212463413
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.4132833340
Short name T629
Test name
Test status
Simulation time 192009782777 ps
CPU time 123.51 seconds
Started Jun 22 05:55:34 PM PDT 24
Finished Jun 22 05:57:38 PM PDT 24
Peak memory 202196 kb
Host smart-6b89d2d3-e0c6-4821-a622-f99d1ea06552
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132833340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.4132833340
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3308637404
Short name T50
Test name
Test status
Simulation time 90583572146 ps
CPU time 379.06 seconds
Started Jun 22 05:55:41 PM PDT 24
Finished Jun 22 06:02:01 PM PDT 24
Peak memory 202516 kb
Host smart-5d268bab-59d1-4ec0-8382-58f7ce793eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308637404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3308637404
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2804067774
Short name T358
Test name
Test status
Simulation time 32288205190 ps
CPU time 17.99 seconds
Started Jun 22 05:55:42 PM PDT 24
Finished Jun 22 05:56:01 PM PDT 24
Peak memory 202020 kb
Host smart-cad7a49f-0c17-46cc-96e3-9c3d9e583464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804067774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2804067774
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3578751753
Short name T471
Test name
Test status
Simulation time 3746181863 ps
CPU time 5.13 seconds
Started Jun 22 05:55:41 PM PDT 24
Finished Jun 22 05:55:46 PM PDT 24
Peak memory 202036 kb
Host smart-85007ec3-5c8d-4512-9edb-fe458ba9a50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578751753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3578751753
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1970705005
Short name T680
Test name
Test status
Simulation time 5744144853 ps
CPU time 12.2 seconds
Started Jun 22 05:55:35 PM PDT 24
Finished Jun 22 05:55:48 PM PDT 24
Peak memory 202036 kb
Host smart-c9b2bfc3-ccfd-481f-aa81-ef97365fadd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970705005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1970705005
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3405690706
Short name T165
Test name
Test status
Simulation time 203529762992 ps
CPU time 109.55 seconds
Started Jun 22 05:55:41 PM PDT 24
Finished Jun 22 05:57:31 PM PDT 24
Peak memory 202204 kb
Host smart-31aa0734-c25d-41a2-90cd-b97ec5f7370b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405690706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3405690706
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3106884092
Short name T333
Test name
Test status
Simulation time 17458715676 ps
CPU time 40.6 seconds
Started Jun 22 05:55:40 PM PDT 24
Finished Jun 22 05:56:21 PM PDT 24
Peak memory 202396 kb
Host smart-caa49aef-4c7b-4fb4-8ec6-335c24683efc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106884092 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3106884092
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1140291528
Short name T723
Test name
Test status
Simulation time 391642033 ps
CPU time 0.69 seconds
Started Jun 22 05:55:48 PM PDT 24
Finished Jun 22 05:55:49 PM PDT 24
Peak memory 201920 kb
Host smart-052983b2-1c79-4e26-a211-83dce60f7bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140291528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1140291528
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2996054088
Short name T543
Test name
Test status
Simulation time 166167186565 ps
CPU time 76.98 seconds
Started Jun 22 05:55:47 PM PDT 24
Finished Jun 22 05:57:05 PM PDT 24
Peak memory 202220 kb
Host smart-9878cb70-26a0-4973-8b89-b7364bc7061e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996054088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2996054088
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1818391942
Short name T111
Test name
Test status
Simulation time 328869553248 ps
CPU time 198.18 seconds
Started Jun 22 05:55:41 PM PDT 24
Finished Jun 22 05:59:00 PM PDT 24
Peak memory 202212 kb
Host smart-3b608956-80fd-4a5b-8b07-8d3bf4b7f597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818391942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1818391942
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.71896561
Short name T421
Test name
Test status
Simulation time 482903743316 ps
CPU time 574.36 seconds
Started Jun 22 05:55:47 PM PDT 24
Finished Jun 22 06:05:22 PM PDT 24
Peak memory 202184 kb
Host smart-53b5f225-0740-4cf1-97c9-7435b2927f46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=71896561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt
_fixed.71896561
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2984615009
Short name T602
Test name
Test status
Simulation time 497903522819 ps
CPU time 1027.84 seconds
Started Jun 22 05:55:41 PM PDT 24
Finished Jun 22 06:12:49 PM PDT 24
Peak memory 202168 kb
Host smart-9c8ffa77-77c8-4060-9f82-101690a2b111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984615009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2984615009
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.952014870
Short name T718
Test name
Test status
Simulation time 165551921262 ps
CPU time 352.7 seconds
Started Jun 22 05:55:39 PM PDT 24
Finished Jun 22 06:01:33 PM PDT 24
Peak memory 202232 kb
Host smart-92123789-ce6e-4319-aa08-99a954691990
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=952014870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.952014870
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3340070305
Short name T499
Test name
Test status
Simulation time 399571657912 ps
CPU time 707.81 seconds
Started Jun 22 05:55:54 PM PDT 24
Finished Jun 22 06:07:42 PM PDT 24
Peak memory 202196 kb
Host smart-3a111ea5-6f18-4913-828d-2387596189ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340070305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3340070305
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2410315956
Short name T535
Test name
Test status
Simulation time 78074333196 ps
CPU time 393.65 seconds
Started Jun 22 05:55:47 PM PDT 24
Finished Jun 22 06:02:21 PM PDT 24
Peak memory 202520 kb
Host smart-121fbbac-a2c1-4851-b3fe-21053f1382d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410315956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2410315956
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3099807143
Short name T570
Test name
Test status
Simulation time 33936140981 ps
CPU time 73.24 seconds
Started Jun 22 05:55:47 PM PDT 24
Finished Jun 22 05:57:00 PM PDT 24
Peak memory 202272 kb
Host smart-07c99264-bd32-4362-b1b1-49ccbc79ada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099807143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3099807143
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2709817214
Short name T687
Test name
Test status
Simulation time 3858533042 ps
CPU time 9.68 seconds
Started Jun 22 05:55:47 PM PDT 24
Finished Jun 22 05:55:57 PM PDT 24
Peak memory 202000 kb
Host smart-511e20ab-ce4c-4979-b57f-209b24aea77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709817214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2709817214
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.882669703
Short name T381
Test name
Test status
Simulation time 5848459786 ps
CPU time 6.44 seconds
Started Jun 22 05:55:40 PM PDT 24
Finished Jun 22 05:55:47 PM PDT 24
Peak memory 202020 kb
Host smart-52a317b1-7b23-4202-b223-ebb71b4712fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882669703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.882669703
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3525159513
Short name T746
Test name
Test status
Simulation time 25081922351 ps
CPU time 58.46 seconds
Started Jun 22 05:55:47 PM PDT 24
Finished Jun 22 05:56:45 PM PDT 24
Peak memory 202040 kb
Host smart-e320b789-87aa-487a-8d74-b9d0bebf7b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525159513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3525159513
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1699170064
Short name T276
Test name
Test status
Simulation time 246150964548 ps
CPU time 157.62 seconds
Started Jun 22 05:55:49 PM PDT 24
Finished Jun 22 05:58:27 PM PDT 24
Peak memory 202376 kb
Host smart-49adc7ad-e9ac-4e4d-8a66-5fd10bd9e468
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699170064 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1699170064
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.318508510
Short name T145
Test name
Test status
Simulation time 378179575 ps
CPU time 0.81 seconds
Started Jun 22 05:56:01 PM PDT 24
Finished Jun 22 05:56:02 PM PDT 24
Peak memory 201920 kb
Host smart-304f00e7-b2b4-4921-abff-2e46ba9e1c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318508510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.318508510
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3252464859
Short name T783
Test name
Test status
Simulation time 375748798748 ps
CPU time 932.3 seconds
Started Jun 22 05:55:57 PM PDT 24
Finished Jun 22 06:11:30 PM PDT 24
Peak memory 202428 kb
Host smart-fef4ec8c-63a3-4a88-a2b6-37ed76de0854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252464859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3252464859
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3721495563
Short name T146
Test name
Test status
Simulation time 500475715485 ps
CPU time 593 seconds
Started Jun 22 05:55:49 PM PDT 24
Finished Jun 22 06:05:42 PM PDT 24
Peak memory 202260 kb
Host smart-39c70de1-215a-4063-bc93-2e0fba5cfb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721495563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3721495563
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2213875765
Short name T739
Test name
Test status
Simulation time 496332692398 ps
CPU time 214.51 seconds
Started Jun 22 05:55:49 PM PDT 24
Finished Jun 22 05:59:23 PM PDT 24
Peak memory 202192 kb
Host smart-cd33b52a-f2de-4399-bdd3-e38bcf553707
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213875765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2213875765
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.4156422937
Short name T487
Test name
Test status
Simulation time 158877350689 ps
CPU time 87.71 seconds
Started Jun 22 05:55:48 PM PDT 24
Finished Jun 22 05:57:16 PM PDT 24
Peak memory 202208 kb
Host smart-1e84b6c1-bd37-4ad8-a9bd-42cf9bd9ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156422937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.4156422937
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.883999087
Short name T431
Test name
Test status
Simulation time 169345590090 ps
CPU time 390.45 seconds
Started Jun 22 05:55:49 PM PDT 24
Finished Jun 22 06:02:20 PM PDT 24
Peak memory 202156 kb
Host smart-002126fa-6c5a-4f72-abef-88f6223548a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=883999087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.883999087
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2830125572
Short name T546
Test name
Test status
Simulation time 342215110830 ps
CPU time 752.85 seconds
Started Jun 22 05:55:54 PM PDT 24
Finished Jun 22 06:08:27 PM PDT 24
Peak memory 202164 kb
Host smart-132de147-bf2b-4e33-8639-8f773b2a6b06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830125572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2830125572
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1287377540
Short name T112
Test name
Test status
Simulation time 405920509892 ps
CPU time 992.48 seconds
Started Jun 22 05:55:54 PM PDT 24
Finished Jun 22 06:12:27 PM PDT 24
Peak memory 202196 kb
Host smart-481c8943-2f53-4cee-9e84-e7fc42531898
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287377540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1287377540
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3029779265
Short name T703
Test name
Test status
Simulation time 23958692316 ps
CPU time 11.45 seconds
Started Jun 22 05:55:53 PM PDT 24
Finished Jun 22 05:56:05 PM PDT 24
Peak memory 202024 kb
Host smart-58a403a8-f6a9-4229-94e6-e17f39117424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029779265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3029779265
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1081482872
Short name T609
Test name
Test status
Simulation time 3817702364 ps
CPU time 10.38 seconds
Started Jun 22 05:55:53 PM PDT 24
Finished Jun 22 05:56:04 PM PDT 24
Peak memory 202020 kb
Host smart-d15c939e-4364-4cc7-91aa-a46ae14f7894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081482872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1081482872
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3591855249
Short name T660
Test name
Test status
Simulation time 5968700233 ps
CPU time 2.03 seconds
Started Jun 22 05:55:53 PM PDT 24
Finished Jun 22 05:55:56 PM PDT 24
Peak memory 202008 kb
Host smart-ce687087-a379-42e4-a2e8-a2558379163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591855249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3591855249
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.190198300
Short name T321
Test name
Test status
Simulation time 109010553718 ps
CPU time 144.93 seconds
Started Jun 22 05:55:54 PM PDT 24
Finished Jun 22 05:58:20 PM PDT 24
Peak memory 218660 kb
Host smart-af132a03-713f-4425-9f55-d6cc9db85bb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190198300 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.190198300
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1100677418
Short name T491
Test name
Test status
Simulation time 410994419 ps
CPU time 1.57 seconds
Started Jun 22 05:44:51 PM PDT 24
Finished Jun 22 05:44:53 PM PDT 24
Peak memory 202068 kb
Host smart-7879fa74-48e7-43f6-8383-2f4bde25c65e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100677418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1100677418
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1952405145
Short name T603
Test name
Test status
Simulation time 211263033868 ps
CPU time 491.1 seconds
Started Jun 22 05:44:33 PM PDT 24
Finished Jun 22 05:52:45 PM PDT 24
Peak memory 202216 kb
Host smart-a57a4e0a-62ee-4332-b743-88787e6a1045
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952405145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1952405145
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1835292314
Short name T332
Test name
Test status
Simulation time 332381477425 ps
CPU time 788.96 seconds
Started Jun 22 05:44:36 PM PDT 24
Finished Jun 22 05:57:46 PM PDT 24
Peak memory 202208 kb
Host smart-ff6aded0-c159-4cce-af47-a16b655a9d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835292314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1835292314
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2346745783
Short name T658
Test name
Test status
Simulation time 168782776955 ps
CPU time 63.4 seconds
Started Jun 22 05:44:27 PM PDT 24
Finished Jun 22 05:45:31 PM PDT 24
Peak memory 202196 kb
Host smart-e9597498-8574-47bb-98cf-ce8398f4c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346745783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2346745783
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2174484850
Short name T482
Test name
Test status
Simulation time 324935471269 ps
CPU time 199.6 seconds
Started Jun 22 05:44:26 PM PDT 24
Finished Jun 22 05:47:46 PM PDT 24
Peak memory 202112 kb
Host smart-b1ee7d47-2925-4bf8-89f5-586e9dcdddb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174484850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2174484850
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1118394467
Short name T151
Test name
Test status
Simulation time 322804666828 ps
CPU time 198.42 seconds
Started Jun 22 05:44:26 PM PDT 24
Finished Jun 22 05:47:45 PM PDT 24
Peak memory 202280 kb
Host smart-4c24a513-b1f3-45b7-861a-5fc3742a1a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118394467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1118394467
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1594495443
Short name T715
Test name
Test status
Simulation time 330005013382 ps
CPU time 166.93 seconds
Started Jun 22 05:44:25 PM PDT 24
Finished Jun 22 05:47:12 PM PDT 24
Peak memory 202168 kb
Host smart-364ecab1-7c60-48b0-81be-3df4bfb9bdaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594495443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1594495443
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2509967275
Short name T189
Test name
Test status
Simulation time 624280581120 ps
CPU time 355.03 seconds
Started Jun 22 05:44:25 PM PDT 24
Finished Jun 22 05:50:21 PM PDT 24
Peak memory 202208 kb
Host smart-5164b225-f737-440c-b491-8a434935883c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509967275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2509967275
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1910896565
Short name T514
Test name
Test status
Simulation time 598717814375 ps
CPU time 860.27 seconds
Started Jun 22 05:44:35 PM PDT 24
Finished Jun 22 05:58:55 PM PDT 24
Peak memory 202268 kb
Host smart-e037023d-116b-4a3a-ab7f-f14680635d2c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910896565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1910896565
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1664495968
Short name T770
Test name
Test status
Simulation time 105409861015 ps
CPU time 459.42 seconds
Started Jun 22 05:44:35 PM PDT 24
Finished Jun 22 05:52:15 PM PDT 24
Peak memory 202576 kb
Host smart-e0576528-4bc3-4ffc-be25-00fe6779508f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664495968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1664495968
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1482032578
Short name T364
Test name
Test status
Simulation time 28644102909 ps
CPU time 15.11 seconds
Started Jun 22 05:44:36 PM PDT 24
Finished Jun 22 05:44:51 PM PDT 24
Peak memory 202040 kb
Host smart-6060ac9a-a5db-4ac5-8077-496a13c5645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482032578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1482032578
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1145494822
Short name T626
Test name
Test status
Simulation time 3325193588 ps
CPU time 2.87 seconds
Started Jun 22 05:44:33 PM PDT 24
Finished Jun 22 05:44:36 PM PDT 24
Peak memory 202048 kb
Host smart-9f080de7-227a-465c-a900-15d84a498c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145494822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1145494822
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1914542277
Short name T578
Test name
Test status
Simulation time 5625297322 ps
CPU time 7.26 seconds
Started Jun 22 05:44:17 PM PDT 24
Finished Jun 22 05:44:25 PM PDT 24
Peak memory 202036 kb
Host smart-36542e65-cb33-431e-838b-049b4efd380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914542277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1914542277
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1194574135
Short name T335
Test name
Test status
Simulation time 202354179277 ps
CPU time 471.1 seconds
Started Jun 22 05:44:45 PM PDT 24
Finished Jun 22 05:52:37 PM PDT 24
Peak memory 202200 kb
Host smart-ff94621b-aa60-44b6-847a-cf23cd1cb363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194574135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1194574135
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3928249048
Short name T370
Test name
Test status
Simulation time 487712037 ps
CPU time 1.7 seconds
Started Jun 22 05:45:15 PM PDT 24
Finished Jun 22 05:45:18 PM PDT 24
Peak memory 201924 kb
Host smart-95a6216c-de0d-4727-a9a0-ae02efc89e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928249048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3928249048
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2803500878
Short name T223
Test name
Test status
Simulation time 324910395001 ps
CPU time 691.9 seconds
Started Jun 22 05:45:01 PM PDT 24
Finished Jun 22 05:56:33 PM PDT 24
Peak memory 202216 kb
Host smart-e248984d-17ea-48ca-a4c9-1f34ff66854c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803500878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2803500878
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2787819801
Short name T304
Test name
Test status
Simulation time 169027799526 ps
CPU time 202 seconds
Started Jun 22 05:44:53 PM PDT 24
Finished Jun 22 05:48:15 PM PDT 24
Peak memory 202292 kb
Host smart-4fd5ddb1-4d66-402b-9525-cbe219885b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787819801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2787819801
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1815488394
Short name T579
Test name
Test status
Simulation time 331120176320 ps
CPU time 195.45 seconds
Started Jun 22 05:44:59 PM PDT 24
Finished Jun 22 05:48:15 PM PDT 24
Peak memory 202184 kb
Host smart-6ec61c2c-d0d8-42b0-8d43-fddbe7573bde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815488394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1815488394
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3313972972
Short name T632
Test name
Test status
Simulation time 489471743087 ps
CPU time 1190.88 seconds
Started Jun 22 05:44:54 PM PDT 24
Finished Jun 22 06:04:46 PM PDT 24
Peak memory 202220 kb
Host smart-26da9929-e523-4226-9140-c124afb70056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313972972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3313972972
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3320096483
Short name T440
Test name
Test status
Simulation time 171784309535 ps
CPU time 186.15 seconds
Started Jun 22 05:44:53 PM PDT 24
Finished Jun 22 05:47:59 PM PDT 24
Peak memory 202212 kb
Host smart-fc0fabe1-c09a-4e19-9828-b9eb5ef150a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320096483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3320096483
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2274284555
Short name T731
Test name
Test status
Simulation time 223577183267 ps
CPU time 160.24 seconds
Started Jun 22 05:45:02 PM PDT 24
Finished Jun 22 05:47:42 PM PDT 24
Peak memory 202296 kb
Host smart-4034705e-8503-4b70-81ff-f90a922dc27c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274284555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2274284555
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1553704215
Short name T765
Test name
Test status
Simulation time 208933635053 ps
CPU time 515.64 seconds
Started Jun 22 05:45:00 PM PDT 24
Finished Jun 22 05:53:36 PM PDT 24
Peak memory 202180 kb
Host smart-cfa192b5-e976-4d66-af8f-cb5a74f41737
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553704215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1553704215
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3770056478
Short name T212
Test name
Test status
Simulation time 87430855895 ps
CPU time 491.84 seconds
Started Jun 22 05:45:07 PM PDT 24
Finished Jun 22 05:53:19 PM PDT 24
Peak memory 202508 kb
Host smart-14ddcc6f-e7f7-4fd5-9997-442062f5ebc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770056478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3770056478
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1705436801
Short name T767
Test name
Test status
Simulation time 42163524134 ps
CPU time 100.4 seconds
Started Jun 22 05:45:08 PM PDT 24
Finished Jun 22 05:46:49 PM PDT 24
Peak memory 202040 kb
Host smart-36bd2f4a-8837-40b9-b8ad-aebc161abf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705436801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1705436801
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3023249478
Short name T405
Test name
Test status
Simulation time 2989143876 ps
CPU time 7.52 seconds
Started Jun 22 05:45:03 PM PDT 24
Finished Jun 22 05:45:11 PM PDT 24
Peak memory 202060 kb
Host smart-0b0e1c8a-3025-4d1f-abdc-96d048956c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023249478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3023249478
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.859613439
Short name T576
Test name
Test status
Simulation time 5884668918 ps
CPU time 7.22 seconds
Started Jun 22 05:44:55 PM PDT 24
Finished Jun 22 05:45:02 PM PDT 24
Peak memory 202056 kb
Host smart-c37083a6-7997-4489-8aca-8e5b451a37d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859613439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.859613439
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3419608259
Short name T694
Test name
Test status
Simulation time 217223872933 ps
CPU time 153.52 seconds
Started Jun 22 05:45:08 PM PDT 24
Finished Jun 22 05:47:41 PM PDT 24
Peak memory 210852 kb
Host smart-d25ac46a-dafb-4679-b740-d908a62ebf42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419608259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3419608259
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.384872778
Short name T366
Test name
Test status
Simulation time 432557921 ps
CPU time 0.8 seconds
Started Jun 22 05:45:28 PM PDT 24
Finished Jun 22 05:45:29 PM PDT 24
Peak memory 201888 kb
Host smart-ea6e86b1-352a-42b5-b8f2-585babeb16ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384872778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.384872778
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.944109306
Short name T254
Test name
Test status
Simulation time 177593391174 ps
CPU time 419.26 seconds
Started Jun 22 05:45:21 PM PDT 24
Finished Jun 22 05:52:20 PM PDT 24
Peak memory 202280 kb
Host smart-ff51d32a-c8a7-4cc2-8e05-17cad8e54bf4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944109306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.944109306
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.787175929
Short name T531
Test name
Test status
Simulation time 514244326213 ps
CPU time 301.4 seconds
Started Jun 22 05:45:21 PM PDT 24
Finished Jun 22 05:50:23 PM PDT 24
Peak memory 202208 kb
Host smart-cd60d753-786e-4504-84dd-5d88feaa2c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787175929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.787175929
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2721165464
Short name T294
Test name
Test status
Simulation time 160902813261 ps
CPU time 369.55 seconds
Started Jun 22 05:45:16 PM PDT 24
Finished Jun 22 05:51:26 PM PDT 24
Peak memory 202184 kb
Host smart-3d8809ac-7874-440a-a36c-2572093f4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721165464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2721165464
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.485771577
Short name T741
Test name
Test status
Simulation time 165118139004 ps
CPU time 116.56 seconds
Started Jun 22 05:45:16 PM PDT 24
Finished Jun 22 05:47:13 PM PDT 24
Peak memory 202184 kb
Host smart-2970d092-ec83-4e19-b60a-ef16c20b4186
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=485771577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.485771577
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3884739101
Short name T713
Test name
Test status
Simulation time 160830009973 ps
CPU time 89.87 seconds
Started Jun 22 05:45:16 PM PDT 24
Finished Jun 22 05:46:46 PM PDT 24
Peak memory 202264 kb
Host smart-ca1fbee7-cdf3-402d-acf8-c76d591cf47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884739101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3884739101
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.512862558
Short name T567
Test name
Test status
Simulation time 324554664275 ps
CPU time 750.41 seconds
Started Jun 22 05:45:15 PM PDT 24
Finished Jun 22 05:57:46 PM PDT 24
Peak memory 202188 kb
Host smart-62b9807e-5e70-4069-b99b-c824cf4b15fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=512862558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.512862558
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3551349107
Short name T536
Test name
Test status
Simulation time 172088691519 ps
CPU time 411.59 seconds
Started Jun 22 05:45:17 PM PDT 24
Finished Jun 22 05:52:09 PM PDT 24
Peak memory 202208 kb
Host smart-889a2b7d-fa23-4712-89e8-d83f98909939
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551349107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3551349107
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.233667253
Short name T455
Test name
Test status
Simulation time 410006320658 ps
CPU time 971.93 seconds
Started Jun 22 05:45:15 PM PDT 24
Finished Jun 22 06:01:28 PM PDT 24
Peak memory 202192 kb
Host smart-4d814d94-0e5f-42e5-af85-bf7f8e795411
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233667253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.233667253
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1163684351
Short name T552
Test name
Test status
Simulation time 72428406077 ps
CPU time 285.38 seconds
Started Jun 22 05:45:21 PM PDT 24
Finished Jun 22 05:50:07 PM PDT 24
Peak memory 202552 kb
Host smart-e9aae9d9-11cd-4c82-9572-2a898ce97286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163684351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1163684351
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1151629483
Short name T68
Test name
Test status
Simulation time 25353322218 ps
CPU time 14.89 seconds
Started Jun 22 05:45:22 PM PDT 24
Finished Jun 22 05:45:37 PM PDT 24
Peak memory 202040 kb
Host smart-8112abf0-7a14-45a4-9eb9-1e66e96e5d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151629483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1151629483
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3749010037
Short name T413
Test name
Test status
Simulation time 4843592832 ps
CPU time 8.64 seconds
Started Jun 22 05:45:21 PM PDT 24
Finished Jun 22 05:45:30 PM PDT 24
Peak memory 202048 kb
Host smart-5d74bb81-b7db-4c88-afcb-ac593d8f713d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749010037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3749010037
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2992213055
Short name T647
Test name
Test status
Simulation time 6048373044 ps
CPU time 2.77 seconds
Started Jun 22 05:45:16 PM PDT 24
Finished Jun 22 05:45:19 PM PDT 24
Peak memory 201988 kb
Host smart-b4930227-a2da-4f68-aae7-b1234a31932c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992213055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2992213055
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1228193958
Short name T671
Test name
Test status
Simulation time 395585840201 ps
CPU time 237.67 seconds
Started Jun 22 05:45:21 PM PDT 24
Finished Jun 22 05:49:18 PM PDT 24
Peak memory 202228 kb
Host smart-97d3f502-fe9f-4277-a3d2-c98454fc55ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228193958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1228193958
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1665830838
Short name T799
Test name
Test status
Simulation time 523792755 ps
CPU time 0.9 seconds
Started Jun 22 05:45:43 PM PDT 24
Finished Jun 22 05:45:45 PM PDT 24
Peak memory 201924 kb
Host smart-76fa6339-8ef0-4dfa-9571-d3430d2ca3d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665830838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1665830838
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3910422694
Short name T340
Test name
Test status
Simulation time 529242547027 ps
CPU time 624.19 seconds
Started Jun 22 05:45:29 PM PDT 24
Finished Jun 22 05:55:53 PM PDT 24
Peak memory 202296 kb
Host smart-8fa558c6-b818-43a1-8db1-30f707b73b49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910422694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3910422694
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.4067258722
Short name T305
Test name
Test status
Simulation time 221275315109 ps
CPU time 127.78 seconds
Started Jun 22 05:45:41 PM PDT 24
Finished Jun 22 05:47:49 PM PDT 24
Peak memory 202196 kb
Host smart-2c65009a-2b8c-45e4-bd43-316ceb9e55bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067258722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4067258722
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3357149329
Short name T504
Test name
Test status
Simulation time 165050428592 ps
CPU time 342.48 seconds
Started Jun 22 05:45:26 PM PDT 24
Finished Jun 22 05:51:09 PM PDT 24
Peak memory 202288 kb
Host smart-7b4ebfdf-b1c3-425b-9086-9319b2e70f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357149329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3357149329
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1320142254
Short name T580
Test name
Test status
Simulation time 165842129209 ps
CPU time 366.37 seconds
Started Jun 22 05:45:37 PM PDT 24
Finished Jun 22 05:51:44 PM PDT 24
Peak memory 202324 kb
Host smart-85057c34-d815-4d99-9130-3cdf7da40ed1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320142254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1320142254
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.474918742
Short name T219
Test name
Test status
Simulation time 492620266052 ps
CPU time 552.78 seconds
Started Jun 22 05:45:42 PM PDT 24
Finished Jun 22 05:54:55 PM PDT 24
Peak memory 202264 kb
Host smart-2201de29-2362-47c3-aa03-01748bffea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474918742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.474918742
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3431059413
Short name T484
Test name
Test status
Simulation time 329633812647 ps
CPU time 739.21 seconds
Started Jun 22 05:45:28 PM PDT 24
Finished Jun 22 05:57:48 PM PDT 24
Peak memory 202240 kb
Host smart-0bd91765-9812-4217-9e89-76476b04c05e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431059413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3431059413
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.18032380
Short name T784
Test name
Test status
Simulation time 364269074770 ps
CPU time 327.52 seconds
Started Jun 22 05:45:29 PM PDT 24
Finished Jun 22 05:50:57 PM PDT 24
Peak memory 202240 kb
Host smart-3dce6ed3-e98d-4534-b31a-26eb05824bf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18032380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wa
keup.18032380
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.4200647923
Short name T464
Test name
Test status
Simulation time 203960846432 ps
CPU time 73.55 seconds
Started Jun 22 05:45:29 PM PDT 24
Finished Jun 22 05:46:43 PM PDT 24
Peak memory 202176 kb
Host smart-6dfab925-5b49-4f92-9068-0fddd9b165ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200647923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.4200647923
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2025521542
Short name T353
Test name
Test status
Simulation time 133374771590 ps
CPU time 704.3 seconds
Started Jun 22 05:45:37 PM PDT 24
Finished Jun 22 05:57:22 PM PDT 24
Peak memory 202736 kb
Host smart-6ebdc13a-2856-4680-9dcd-f20c18a65614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025521542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2025521542
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2376755091
Short name T374
Test name
Test status
Simulation time 30728992191 ps
CPU time 18.44 seconds
Started Jun 22 05:45:38 PM PDT 24
Finished Jun 22 05:45:57 PM PDT 24
Peak memory 202028 kb
Host smart-f7067427-92d2-4a27-944c-08ab599ee70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376755091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2376755091
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3159215321
Short name T627
Test name
Test status
Simulation time 3388555264 ps
CPU time 3.01 seconds
Started Jun 22 05:45:40 PM PDT 24
Finished Jun 22 05:45:43 PM PDT 24
Peak memory 202052 kb
Host smart-553eea3b-479a-4456-9109-ebf3483cdc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159215321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3159215321
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3089500097
Short name T755
Test name
Test status
Simulation time 5878712748 ps
CPU time 15.06 seconds
Started Jun 22 05:45:32 PM PDT 24
Finished Jun 22 05:45:47 PM PDT 24
Peak memory 201936 kb
Host smart-1035f2b5-1477-49ee-832a-0145ac1ec956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089500097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3089500097
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1179734762
Short name T709
Test name
Test status
Simulation time 194401337976 ps
CPU time 109.23 seconds
Started Jun 22 05:45:43 PM PDT 24
Finished Jun 22 05:47:32 PM PDT 24
Peak memory 202224 kb
Host smart-1ec063c1-6424-4437-a562-bf92ba6026ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179734762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1179734762
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1530661222
Short name T19
Test name
Test status
Simulation time 136168955659 ps
CPU time 161.89 seconds
Started Jun 22 05:45:48 PM PDT 24
Finished Jun 22 05:48:31 PM PDT 24
Peak memory 210904 kb
Host smart-461e18fe-623d-4b6a-ab78-90eb6e48c870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530661222 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1530661222
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3566119460
Short name T693
Test name
Test status
Simulation time 520081227 ps
CPU time 1.72 seconds
Started Jun 22 05:46:23 PM PDT 24
Finished Jun 22 05:46:25 PM PDT 24
Peak memory 201924 kb
Host smart-18ed9e21-0510-4a75-8c9a-1ff62fe58715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566119460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3566119460
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3440201592
Short name T247
Test name
Test status
Simulation time 331543432465 ps
CPU time 186.78 seconds
Started Jun 22 05:45:53 PM PDT 24
Finished Jun 22 05:49:00 PM PDT 24
Peak memory 202424 kb
Host smart-f911d81b-0b79-44d0-977b-488141cdbfdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440201592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3440201592
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.930660670
Short name T714
Test name
Test status
Simulation time 161981451476 ps
CPU time 177.74 seconds
Started Jun 22 05:45:52 PM PDT 24
Finished Jun 22 05:48:50 PM PDT 24
Peak memory 202192 kb
Host smart-445e625d-92ce-40a6-abb5-9fc1216b12e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=930660670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.930660670
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1937982490
Short name T601
Test name
Test status
Simulation time 328900922009 ps
CPU time 119.6 seconds
Started Jun 22 05:45:52 PM PDT 24
Finished Jun 22 05:47:52 PM PDT 24
Peak memory 202284 kb
Host smart-041f1140-9098-452f-a7cf-b0363608247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937982490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1937982490
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.920653750
Short name T651
Test name
Test status
Simulation time 331225137802 ps
CPU time 358.61 seconds
Started Jun 22 05:45:52 PM PDT 24
Finished Jun 22 05:51:51 PM PDT 24
Peak memory 202196 kb
Host smart-12bf42f6-65a5-4ea2-8389-9673a7aba4a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=920653750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.920653750
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.256108803
Short name T745
Test name
Test status
Simulation time 171344314037 ps
CPU time 96.44 seconds
Started Jun 22 05:45:52 PM PDT 24
Finished Jun 22 05:47:29 PM PDT 24
Peak memory 202248 kb
Host smart-67fc838d-7da9-417b-8eb4-5bbb2df6c6b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256108803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.256108803
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1757937790
Short name T55
Test name
Test status
Simulation time 207374365452 ps
CPU time 401 seconds
Started Jun 22 05:45:51 PM PDT 24
Finished Jun 22 05:52:32 PM PDT 24
Peak memory 202276 kb
Host smart-409c1bb9-6bc6-48c9-967e-fa768e043fe8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757937790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1757937790
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2808396421
Short name T347
Test name
Test status
Simulation time 80232398078 ps
CPU time 410.88 seconds
Started Jun 22 05:45:59 PM PDT 24
Finished Jun 22 05:52:50 PM PDT 24
Peak memory 202444 kb
Host smart-99d20206-3df9-4cf4-b958-dec87a3756e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808396421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2808396421
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4043939459
Short name T414
Test name
Test status
Simulation time 29511194197 ps
CPU time 35.41 seconds
Started Jun 22 05:45:59 PM PDT 24
Finished Jun 22 05:46:34 PM PDT 24
Peak memory 202040 kb
Host smart-68a1369e-f3f6-4829-85ba-0ebb31a86ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043939459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4043939459
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2780362363
Short name T362
Test name
Test status
Simulation time 3804567646 ps
CPU time 8.91 seconds
Started Jun 22 05:45:59 PM PDT 24
Finished Jun 22 05:46:09 PM PDT 24
Peak memory 202060 kb
Host smart-4d4a85b4-54c7-41ec-bc15-943421cdfa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780362363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2780362363
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.418163297
Short name T564
Test name
Test status
Simulation time 5761198621 ps
CPU time 4.39 seconds
Started Jun 22 05:45:44 PM PDT 24
Finished Jun 22 05:45:49 PM PDT 24
Peak memory 202060 kb
Host smart-8320f41c-2c98-40a4-b12d-b74b4c2a28f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418163297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.418163297
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3494067272
Short name T210
Test name
Test status
Simulation time 109894071532 ps
CPU time 354.58 seconds
Started Jun 22 05:46:03 PM PDT 24
Finished Jun 22 05:51:58 PM PDT 24
Peak memory 202588 kb
Host smart-6df34cc4-eab2-44bf-a828-c3f33ddf3daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494067272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3494067272
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3310501353
Short name T22
Test name
Test status
Simulation time 384478357119 ps
CPU time 340.22 seconds
Started Jun 22 05:46:01 PM PDT 24
Finished Jun 22 05:51:42 PM PDT 24
Peak memory 210860 kb
Host smart-d8b07a6c-1502-4196-999e-cf36d88507d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310501353 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3310501353
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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