Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7158	1			T1	26		T4	13		T5	8
testmodes[AdcCtrlTestmodeNormal]	5911	1			T1	9		T2	2		T3	2
testmodes[AdcCtrlTestmodeLowpower]	6182	1			T1	11		T5	1		T6	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3684	1			T1	21		T4	10		T5	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1940	1			T1	4		T4	2		T5	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1431	1			T1	1		T6	1		T8	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1916	1			T1	5		T4	2		T5	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2102	1			T1	3		T2	1		T3	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1548	1			T8	5		T9	22		T24	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1432	1			T6	1		T8	6		T9	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1531	1			T1	1		T5	1		T6	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2969	1			T1	10		T8	36		T9	27