Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21557

1

T1

44

T3

1

T4

17

auto[ADC_CTRL_FILTER_COND_OUT]

5657

1

T1

31

T2

20

T3

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21464

1

T1

75

T3

4

T4

17

auto[1]

5750

1

T2

20

T5

27

T6

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T197	14		T198	1		-	-
values[0]	58	1			T73	4		T138	12		T199	29
values[1]	829	1			T8	6		T11	1		T76	1
values[2]	640	1			T23	5		T24	7		T125	2
values[3]	732	1			T9	17		T127	15		T129	2
values[4]	715	1			T3	3		T9	3		T76	1
values[5]	556	1			T5	12		T6	5		T8	5
values[6]	671	1			T1	20		T5	27		T125	19
values[7]	653	1			T125	2		T143	2		T89	15
values[8]	565	1			T11	1		T76	1		T124	27
values[9]	3444	1			T1	11		T2	20		T3	1
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	963	1			T8	6		T11	1		T123	21
values[1]	3008	1			T2	20		T7	29		T10	3
values[2]	638	1			T9	20		T23	5		T102	14
values[3]	721	1			T3	3		T5	12		T76	1
values[4]	596	1			T6	5		T8	5		T9	1
values[5]	595	1			T1	20		T5	27		T125	19
values[6]	606	1			T11	1		T40	1		T125	2
values[7]	691	1			T9	10		T23	3		T76	1
values[8]	927	1			T1	11		T3	1		T32	23
values[9]	129	1			T34	9		T132	3		T18	5
minimum	18340	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T8	5		T11	1		T123	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T123	8		T28	1		T94	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T125	1		T129	1		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1550	1			T2	2		T7	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	13		T102	1		T94	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	2		T23	5		T88	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	1		T76	1		T89	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T88	18		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	3		T9	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	4		T33	2		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	15		T143	1		T130	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	11		T125	10		T28	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T125	1		T89	1		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	1		T40	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	10		T23	3		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T76	1		T40	1		T133	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	1		T127	17		T135	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	11		T32	12		T33	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T200	1		T201	3		T202	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T34	5		T132	1		T18	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18198	1			T1	44		T4	17		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	1		T130	3		T131	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T94	8		T136	4		T73	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T125	1		T146	9		T203	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1109	1			T2	18		T7	26		T24	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T9	4		T102	13		T94	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	1		T88	11		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	11		T89	14		T128	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	2		T88	12		T128	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T148	1		T204	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T6	1		T33	1		T102	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T5	12		T130	5		T13	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	9		T125	9		T29	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T125	1		T89	1		T68	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T89	5		T129	13		T72	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T98	9		T124	13		T135	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	13		T68	7		T146	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T135	17		T73	2		T205	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T32	11		T33	15		T40	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T200	17		T201	2		T202	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T34	4		T132	2		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T197	2		T198	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T138	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T73	1		T199	16		T206	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	5		T11	1		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T76	1		T123	8		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T125	1		T130	15		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T23	5		T24	4		T88	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	13		T129	1		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T127	15		T129	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T76	1		T102	1		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T9	2		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	1		T8	3		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	4		T33	2		T94	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	15		T13	8		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	11		T125	10		T28	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T125	1		T143	1		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T143	1		T89	8		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T124	14		T136	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	1		T76	1		T40	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T3	1		T9	10		T23	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1625	1			T1	11		T2	2		T7	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T197	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T73	3		T199	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	1		T131	9		T209	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T94	8		T136	19		T15	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T125	1		T130	3		T210	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T24	3		T88	11		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	4		T146	9		T211	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T126	8		T140	12		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T102	13		T89	14		T94	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	2		T9	1		T102	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	11		T8	2		T128	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T6	1		T33	1		T94	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	12		T13	7		T212	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	9		T125	9		T126	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T125	1		T89	1		T130	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T89	5		T129	13		T72	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T124	13		T136	11		T213	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T40	13		T130	13		T146	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T98	9		T135	19		T73	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1142	1			T2	18		T7	26		T32	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T8	3		T11	1		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T123	1		T28	1		T94	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T125	2		T129	1		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1442	1			T2	20		T7	29		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	8		T102	14		T94	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	2		T23	1		T88	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T5	12		T76	1		T89	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	3		T88	13		T128	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	5		T9	1		T148	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	4		T33	2		T102	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	13		T143	1		T130	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	10		T125	10		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T125	2		T89	2		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	1		T40	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	1		T23	1		T98	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T76	1		T40	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T3	1		T127	1		T135	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	1		T32	12		T33	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T200	18		T201	3		T202	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T34	5		T132	3		T18	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18337	1			T1	44		T4	17		T5	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	3		T123	12		T93	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T123	7		T94	10		T141	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T146	9		T179	18		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1217	1			T24	2		T168	23		T214	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	9		T94	7		T30	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T23	4		T88	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T89	4		T128	4		T70	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T88	17		T16	23		T215	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T212	3		T216	16		T217	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T6	1		T33	1		T94	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	14		T130	13		T13	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T1	10		T125	9		T28	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T134	11		T218	5		T219	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T89	7		T220	10		T72	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	9		T23	2		T124	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T133	6		T130	12		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T127	16		T135	13		T221	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	10		T32	11		T33	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T201	2		T202	13		T222	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T34	4		T18	1		T223	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T224	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T197	13		T198	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T138	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T73	4		T199	14		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T8	3		T11	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T76	1		T123	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T125	2		T130	4		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T23	1		T24	5		T88	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	8		T129	1		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T127	1		T129	1		T126	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T76	1		T102	14		T89	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	3		T9	2		T102	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	12		T8	5		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	4		T33	2		T94	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	13		T13	11		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	10		T125	10		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T125	2		T143	1		T89	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T143	1		T89	6		T129	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T124	14		T136	12		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	1		T76	1		T40	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T3	1		T9	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1499	1			T1	1		T2	20		T7	29
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T197	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T138	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T199	15		T206	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	3		T123	12		T93	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T123	7		T94	10		T141	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T130	14		T179	18		T210	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T23	4		T24	2		T88	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	9		T146	9		T145	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T127	14		T148	11		T225	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T89	4		T94	7		T70	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	1		T88	17		T16	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T128	4		T226	2		T212	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T6	1		T33	1		T94	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	14		T13	4		T212	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	10		T125	9		T28	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T134	11		T130	13		T218	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T89	7		T72	14		T14	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T124	13		T213	15		T227	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T40	7		T220	10		T133	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T9	9		T23	2		T127	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1268	1			T1	10		T32	11		T33	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23692

1

T1

44

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3522

1

T1

31

T3

1

T5

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21328

1

T1

44

T3

3

T4

17

auto[1]

5886

1

T1

31

T2

20

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T228	2		-	-		-	-
values[0]	65	1			T229	1		T230	8		T175	5
values[1]	687	1			T1	20		T8	6		T9	1
values[2]	561	1			T40	1		T127	17		T29	14
values[3]	774	1			T32	23		T76	1		T98	10
values[4]	896	1			T9	10		T11	1		T23	5
values[5]	2669	1			T2	20		T3	1		T7	29
values[6]	757	1			T5	12		T9	17		T88	24
values[7]	642	1			T1	11		T3	3		T11	1
values[8]	719	1			T8	5		T125	21		T91	1
values[9]	1106	1			T5	27		T6	5		T9	3
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	822	1			T8	6		T9	1		T24	7
values[1]	715	1			T76	1		T40	1		T127	17
values[2]	784	1			T32	23		T98	10		T143	1
values[3]	2915	1			T2	20		T7	29		T9	10
values[4]	617	1			T3	1		T5	12		T33	27
values[5]	580	1			T9	17		T123	8		T91	1
values[6]	745	1			T1	11		T3	3		T11	1
values[7]	776	1			T8	5		T76	1		T34	9
values[8]	756	1			T5	27		T6	5		T9	3
values[9]	148	1			T231	12		T211	5		T20	1
minimum	18356	1			T1	64		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	5		T24	4		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	1		T33	2		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T76	1		T40	1		T29	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T127	17		T232	1		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T32	12		T89	5		T220	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T98	1		T143	1		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T2	2		T7	3		T9	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T23	5		T89	8		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T33	12		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	1		T88	13		T134	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T133	7		T30	7		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	13		T123	8		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T11	1		T124	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	11		T88	18		T93	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T76	1		T34	5		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T8	3		T125	11		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	2		T123	13		T28	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	15		T6	4		T23	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T231	12		T211	1		T233	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T20	1		T234	18		T216	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T1	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	1		T24	3		T136	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T33	1		T102	13		T72	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T29	8		T75	7		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T135	2		T73	2		T131	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T32	11		T89	14		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T98	9		T89	1		T68	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1079	1			T2	18		T7	26		T178	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T89	5		T144	5		T218	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	11		T33	15		T40	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T88	11		T126	8		T13	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T30	2		T146	9		T235	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	4		T94	5		T73	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	2		T124	13		T130	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T88	12		T130	3		T131	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T34	4		T136	4		T145	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	2		T125	10		T128	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T136	11		T68	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	12		T6	1		T102	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T211	4		T233	8		T236	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T237	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T1	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T228	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T229	1		T175	1		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T230	8		T239	1		T240	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	5		T24	4		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	11		T9	1		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T40	1		T29	6		T75	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T127	17		T73	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T32	12		T76	1		T89	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T98	1		T143	1		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	10		T11	1		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T23	5		T89	8		T127	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T2	2		T7	3		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	1		T91	1		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T133	7		T30	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	13		T88	13		T94	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T11	1		T124	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	11		T123	8		T88	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T130	14		T136	1		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	3		T125	11		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T9	2		T76	1		T34	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T5	15		T6	4		T23	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T175	4		T238	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T240	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	1		T24	3		T136	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	9		T33	1		T102	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T29	8		T75	7		T204	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T73	2		T131	9		T173	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	11		T89	14		T128	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T98	9		T89	1		T135	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T40	13		T94	8		T135	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T89	5		T144	5		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T2	18		T7	26		T33	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T126	8		T13	7		T218	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	11		T30	2		T146	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	4		T88	11		T94	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	2		T124	13		T243	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T88	12		T130	3		T131	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T130	5		T136	4		T145	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	2		T125	10		T128	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T9	1		T34	4		T136	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	12		T6	1		T102	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3