Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23840

1

T1

44

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3374

1

T1

31

T3

1

T5

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21651

1

T1

64

T3

4

T4

17

auto[1]

5563

1

T1

11

T2

20

T5

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	192	1			T9	3		T102	12		T123	13
values[0]	51	1			T204	13		T238	7		T239	1
values[1]	639	1			T1	20		T8	6		T24	7
values[2]	627	1			T9	1		T127	17		T29	14
values[3]	808	1			T32	23		T76	1		T98	10
values[4]	855	1			T9	10		T11	1		T23	5
values[5]	2691	1			T2	20		T3	1		T7	29
values[6]	735	1			T5	12		T9	17		T88	24
values[7]	654	1			T1	11		T3	3		T11	1
values[8]	659	1			T8	5		T76	1		T125	21
values[9]	967	1			T5	27		T6	5		T23	3
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	652	1			T1	20		T9	1		T102	14
values[1]	763	1			T76	1		T40	1		T127	17
values[2]	803	1			T23	5		T32	23		T98	10
values[3]	2904	1			T2	20		T7	29		T9	10
values[4]	571	1			T3	1		T5	12		T33	27
values[5]	633	1			T9	17		T123	8		T91	1
values[6]	743	1			T1	11		T3	3		T11	1
values[7]	749	1			T8	5		T76	1		T34	9
values[8]	828	1			T5	27		T6	5		T9	3
values[9]	77	1			T231	12		T211	5		T20	1
minimum	18491	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	1		T70	13		T72	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	11		T9	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T76	1		T40	1		T135	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T127	17		T232	1		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T23	5		T32	12		T89	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T98	1		T143	1		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1472	1			T2	2		T7	3		T9	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T76	1		T89	8		T127	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T125	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T33	12		T88	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T73	1		T146	10		T315	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	13		T123	8		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T11	1		T124	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	11		T88	18		T93	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T34	5		T125	10		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	3		T76	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T6	4		T9	2		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	15		T23	3		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T231	12		T211	1		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T20	1		T234	18		T216	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18210	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T72	15		T26	1		T204	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	15		T70	11		T72	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	9		T102	13		T209	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T135	2		T29	8		T75	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T73	2		T146	10		T173	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T32	11		T89	14		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T98	9		T89	1		T68	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T2	18		T7	26		T40	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T89	5		T126	8		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	11		T125	1		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T33	15		T88	11		T13	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T73	13		T146	9		T132	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	4		T94	5		T130	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	2		T124	13		T247	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T88	12		T130	5		T131	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	4		T125	9		T136	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	2		T125	1		T128	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	1		T9	1		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	12		T102	11		T94	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T211	4		T236	6		T317	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T8	4		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T72	12		T204	12		T318	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T9	2		T123	13		T28	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T102	1		T225	17		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T238	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T204	1		T239	1		T240	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	5		T24	4		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	11		T102	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T29	6		T75	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	1		T127	17		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T32	12		T76	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T98	1		T143	1		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	10		T11	1		T23	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T76	1		T89	8		T127	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T2	2		T7	3		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	1		T33	12		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	1		T73	1		T146	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	13		T88	13		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T11	1		T124	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	11		T123	8		T88	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T125	10		T136	1		T69	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	3		T76	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T6	4		T34	5		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	15		T23	3		T40	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T9	1		T148	1		T211	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T102	11		T225	12		T237	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T238	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T204	12		T240	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	1		T24	3		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	9		T102	13		T72	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	8		T75	7		T131	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T73	2		T173	2		T204	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T32	11		T89	14		T128	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T98	9		T89	1		T68	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T40	13		T94	8		T135	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T89	5		T144	5		T319	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T2	18		T7	26		T178	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T33	15		T126	8		T13	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	11		T73	13		T146	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	4		T88	11		T94	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	2		T124	13		T247	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T88	12		T130	8		T131	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T125	9		T136	4		T145	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	2		T125	1		T128	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	1		T34	4		T136	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	12		T94	8		T135	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T136	16		T70	12		T72	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	10		T9	1		T102	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T76	1		T40	1		T135	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T127	1		T232	1		T73	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T23	1		T32	12		T89	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T98	10		T143	1		T89	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T2	20		T7	29		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T76	1		T89	6		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	12		T125	2		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T33	16		T88	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T73	14		T146	10		T315	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	8		T123	1		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	3		T11	1		T124	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T88	13		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	5		T125	10		T136	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	5		T76	1		T125	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	4		T9	2		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	13		T23	1		T102	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T231	1		T211	5		T236	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T20	1		T234	1		T216	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T72	13		T26	1		T204	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T70	12		T226	2		T213	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	10		T209	22		T187	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T135	10		T29	1		T179	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T127	16		T146	11		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T23	4		T32	11		T89	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T242	3		T244	1		T19	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1136	1			T9	9		T40	7		T94	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T89	7		T127	12		T69	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T30	4		T146	9		T147	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T33	11		T88	12		T134	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T146	9		T246	3		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	9		T123	7		T94	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T124	13		T247	4		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	10		T88	17		T93	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	4		T125	9		T69	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	12		T213	12		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T6	1		T9	1		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	14		T23	2		T94	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T231	11		T317	2		T165	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T234	17		T287	2		T206	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T8	3		T24	2		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T72	14		T80	12		T230	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T9	2		T123	1		T28	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T102	12		T225	13		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T238	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T204	13		T239	1		T240	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	3		T24	5		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	10		T102	14		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T29	13		T75	8		T131	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	1		T127	1		T73	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T32	12		T76	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T98	10		T143	1		T89	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T9	1		T11	1		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T76	1		T89	6		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T2	20		T7	29		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	1		T33	16		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	12		T73	14		T146	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	8		T88	12		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	3		T11	1		T124	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T123	1		T88	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T125	10		T136	5		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	5		T76	1		T125	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T6	4		T34	5		T136	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	13		T23	1		T40	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T9	1		T123	12		T28	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T225	16		T287	2		T228	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T240	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	3		T24	2		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	10		T72	14		T209	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T29	1		T179	18		T145	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T127	16		T173	10		T20	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T32	11		T89	4		T220	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T146	11		T210	2		T244	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	9		T23	4		T40	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T89	7		T127	12		T69	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1128	1			T168	23		T214	6		T320	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T33	11		T134	11		T13	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T146	9		T147	4		T142	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	9		T88	12		T94	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T124	13		T247	4		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	10		T123	7		T88	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T125	9		T69	16		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T93	18		T14	7		T213	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	1		T34	4		T173	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	14		T23	2		T94	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1