Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23932

1

T1

64

T2

20

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3282

1

T1

11

T5

39

T9

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21261

1

T1

64

T3

1

T4

17

auto[1]

5953

1

T1

11

T2

20

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	233	1			T9	1		T125	2		T89	13
values[0]	42	1			T3	1		T207	1		T25	10
values[1]	699	1			T76	1		T125	19		T88	30
values[2]	2971	1			T2	20		T7	29		T8	6
values[3]	542	1			T6	5		T76	1		T40	1
values[4]	646	1			T1	20		T5	12		T11	1
values[5]	484	1			T1	11		T34	9		T123	8
values[6]	638	1			T9	10		T76	1		T33	27
values[7]	645	1			T3	3		T9	20		T11	1
values[8]	825	1			T5	27		T24	7		T102	14
values[9]	1153	1			T8	5		T23	5		T32	23
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	838	1			T3	1		T8	6		T76	1
values[1]	2889	1			T2	20		T6	5		T7	29
values[2]	513	1			T40	21		T220	11		T135	31
values[3]	594	1			T1	20		T5	12		T11	1
values[4]	559	1			T1	11		T129	1		T126	11
values[5]	594	1			T9	10		T76	1		T33	27
values[6]	730	1			T3	3		T5	27		T9	20
values[7]	848	1			T24	7		T102	14		T125	2
values[8]	969	1			T8	5		T9	1		T23	5
values[9]	181	1			T242	11		T244	4		T199	29
minimum	18499	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	1		T8	5		T125	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T76	1		T143	1		T128	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T2	2		T6	4		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T23	3		T76	1		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T40	8		T75	1		T139	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T220	11		T135	14		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	11		T11	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T128	1		T145	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T129	1		T70	13		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	11		T126	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	12		T124	14		T133	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	10		T76	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T9	2		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	15		T9	13		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T24	4		T91	1		T94	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T102	1		T125	1		T127	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T8	3		T23	5		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T9	1		T33	2		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T244	2		T199	16		T271	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T242	4		T321	1		T268	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18247	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T322	1		T156	1		T152	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	1		T125	9		T88	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T128	3		T213	13		T233	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T2	18		T6	1		T7	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T102	11		T130	3		T126	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T40	13		T75	7		T205	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T135	17		T144	2		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	9		T98	9		T34	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T5	11		T128	7		T215	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T70	11		T131	9		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T126	10		T270	5		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	15		T124	13		T136	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T131	12		T26	12		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	2		T9	1		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	12		T9	4		T88	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T24	3		T94	8		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T102	13		T125	1		T136	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	2		T32	11		T89	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T33	1		T125	1		T89	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T244	2		T199	13		T271	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T242	7		T321	2		T268	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	1		T8	3		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T152	9		T304	5		T222	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T89	8		T144	6		T147	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T9	1		T125	1		T14	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T3	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T207	1		T25	5		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T125	10		T88	18		T89	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T76	1		T128	5		T255	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T2	2		T7	3		T8	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T23	3		T102	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T6	4		T40	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T76	1		T220	11		T135	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	11		T11	1		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	1		T145	7		T246	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T34	5		T123	8		T134	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	11		T128	1		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T33	12		T133	7		T69	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	10		T76	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	1		T9	2		T124	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	13		T11	1		T88	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T24	4		T135	13		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	15		T102	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T8	3		T23	5		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T33	2		T89	1		T94	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T89	5		T144	5		T244	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T125	1		T14	10		T242	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T25	5		T268	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T125	9		T88	12		T89	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T128	3		T213	13		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T2	18		T7	26		T8	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T102	11		T130	3		T126	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T6	1		T136	11		T205	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T135	17		T72	13		T144	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	9		T98	9		T40	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T5	11		T221	5		T152	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T34	4		T70	11		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T128	7		T270	5		T276	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T33	15		T131	9		T146	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T126	10		T131	12		T26	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	2		T9	1		T124	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	4		T88	11		T73	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T24	3		T135	10		T129	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	12		T102	13		T125	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	2		T32	11		T94	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T33	1		T89	1		T94	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	1		T8	3		T125	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T76	1		T143	1		T128	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T2	20		T6	4		T7	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T23	1		T76	1		T102	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T40	14		T75	8		T139	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T220	1		T135	18		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	10		T11	1		T98	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T5	12		T128	8		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T129	1		T70	12		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T126	11		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T33	16		T124	14		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T76	1		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	3		T9	2		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	13		T9	8		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T24	5		T91	1		T94	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T102	14		T125	2		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	5		T23	1		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T9	1		T33	2		T125	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T244	4		T199	14		T271	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T242	8		T321	3		T268	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18372	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T322	1		T156	1		T152	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	3		T125	9		T88	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T128	4		T213	12		T142	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T6	1		T168	23		T214	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T23	2		T130	14		T213	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T40	7		T147	9		T278	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T220	10		T135	13		T144	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	10		T34	4		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T145	6		T246	3		T256	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T70	12		T146	9		T148	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T1	10		T270	4		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T33	11		T124	13		T133	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	9		T216	16		T223	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T9	1		T141	19		T203	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	14		T9	9		T88	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T24	2		T94	10		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T127	16		T30	4		T209	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T23	4		T32	11		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T33	1		T94	7		T72	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T199	15		T271	11		T324	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T242	3		T268	11		T190	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T93	18		T325	11		T326	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T152	3		T304	8		T222	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T89	6		T144	6		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T9	1		T125	2		T14	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T3	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T207	1		T25	6		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T125	10		T88	13		T89	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T76	1		T128	4		T255	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T2	20		T7	29		T8	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T23	1		T102	12		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	4		T40	1		T136	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T76	1		T220	1		T135	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	10		T11	1		T98	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T5	12		T145	1		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T34	5		T123	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T128	8		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T33	16		T133	1		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	1		T76	1		T126	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	3		T9	2		T124	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	8		T11	1		T88	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T24	5		T135	11		T129	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	13		T102	14		T125	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T8	5		T23	1		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T33	2		T89	2		T94	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T89	7		T144	5		T147	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T14	7		T242	3		T190	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T25	4		T268	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T125	9		T88	17		T89	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T128	4		T213	12		T227	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T8	3		T168	23		T214	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T23	2		T130	14		T213	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T6	1		T212	2		T278	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T220	10		T135	13		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	10		T40	7		T127	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T145	6		T246	3		T221	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	4		T123	7		T134	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T1	10		T270	4		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T33	11		T133	6		T69	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T9	9		T18	1		T216	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	1		T124	13		T141	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T9	9		T88	12		T127	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T24	2		T135	12		T130	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	14		T127	16		T30	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T23	4		T32	11		T123	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T33	1		T94	7		T72	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1