Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23811

1

T1

44

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3403

1

T1

31

T3

1

T5

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21475

1

T1

75

T3

1

T4

17

auto[1]

5739

1

T2

20

T3

3

T5

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	66	1			T98	10		T82	24		T327	32
values[0]	91	1			T148	37		T187	10		T250	1
values[1]	573	1			T1	11		T5	27		T9	17
values[2]	605	1			T23	3		T124	27		T143	1
values[3]	694	1			T32	23		T40	1		T91	1
values[4]	839	1			T3	1		T9	10		T76	1
values[5]	671	1			T76	1		T34	9		T102	12
values[6]	712	1			T1	20		T24	7		T76	1
values[7]	584	1			T3	3		T102	14		T123	8
values[8]	517	1			T6	5		T8	5		T11	1
values[9]	3526	1			T2	20		T5	12		T7	29
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	838	1			T1	11		T5	27		T9	17
values[1]	652	1			T23	3		T94	39		T220	11
values[2]	783	1			T32	23		T123	13		T125	2
values[3]	686	1			T3	1		T9	10		T76	2
values[4]	824	1			T1	20		T76	1		T88	24
values[5]	625	1			T24	7		T123	8		T40	21
values[6]	2700	1			T2	20		T3	3		T7	29
values[7]	520	1			T6	5		T9	3		T11	1
values[8]	1041	1			T8	6		T9	1		T11	1
values[9]	201	1			T5	12		T23	5		T98	10
minimum	18344	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	15		T124	14		T128	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	11		T9	13		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T126	1		T68	1		T179	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T23	3		T94	26		T220	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T32	12		T125	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T123	13		T88	18		T127	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T34	5		T40	1		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	1		T9	10		T76	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T76	1		T126	1		T14	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	11		T88	13		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T123	8		T40	8		T125	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T24	4		T28	4		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T2	2		T3	1		T7	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T8	3		T102	1		T127	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T89	1		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	4		T11	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T8	5		T11	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	1		T93	19		T30	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T73	1		T204	1		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T5	1		T23	5		T98	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T273	1		T328	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	12		T124	13		T128	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	4		T89	14		T29	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T126	8		T68	7		T144	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T94	13		T136	4		T131	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T32	11		T125	1		T129	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T88	12		T130	13		T72	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T34	4		T130	3		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T33	16		T102	11		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T126	10		T14	10		T209	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	9		T88	11		T131	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T40	13		T125	9		T135	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T24	3		T135	17		T68	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T2	18		T3	2		T7	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T8	2		T102	13		T212	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	1		T89	1		T94	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	1		T128	7		T267	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	1		T125	1		T72	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T30	2		T146	10		T205	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T73	2		T204	12		T251	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T5	11		T98	9		T89	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T328	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T327	18		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T98	1		T82	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T329	1		T330	1		T331	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T148	22		T187	6		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	15		T128	5		T135	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	11		T9	13		T29	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T124	14		T126	1		T68	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T23	3		T143	1		T89	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T32	12		T40	1		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T94	26		T127	15		T220	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T125	1		T127	13		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	1		T9	10		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T34	5		T126	1		T14	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T76	1		T102	1		T141	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T76	1		T40	8		T125	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T1	11		T24	4		T28	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T123	8		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T102	1		T134	12		T68	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T89	1		T93	1		T94	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	4		T8	3		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1650	1			T2	2		T7	3		T8	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T5	1		T9	1		T23	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T327	14		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T98	9		T82	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T330	1		T331	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T148	15		T187	4		T84	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	12		T128	3		T135	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	4		T29	8		T144	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T124	13		T126	8		T68	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T89	14		T136	4		T73	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T32	11		T130	5		T213	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T94	13		T146	9		T211	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T125	1		T129	13		T130	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T33	16		T88	12		T130	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	4		T126	10		T14	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T102	11		T173	9		T319	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T40	13		T125	9		T135	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	9		T24	3		T88	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	2		T70	11		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T102	13		T68	7		T212	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T89	1		T94	8		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	1		T8	2		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T2	18		T7	26		T8	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T5	11		T89	5		T128	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T5	13		T124	14		T128	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T9	8		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T126	9		T68	8		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T23	1		T94	15		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T32	12		T125	2		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T123	1		T88	13		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	5		T40	1		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	1		T9	1		T76	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T76	1		T126	11		T14	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	10		T88	12		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T123	1		T40	14		T125	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T24	5		T28	2		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T2	20		T3	3		T7	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T8	5		T102	14		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	2		T89	2		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	4		T11	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T8	3		T11	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T9	1		T93	1		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T73	3		T204	13		T251	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T5	12		T23	1		T98	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T273	1		T328	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	14		T124	13		T128	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	10		T9	9		T89	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T179	18		T144	9		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T23	2		T94	24		T220	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T32	11		T130	13		T213	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T123	12		T88	17		T127	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T34	4		T127	12		T130	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	9		T33	12		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	7		T209	22		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	10		T88	12		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T123	7		T40	7		T125	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T24	2		T28	2		T134	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T168	23		T214	6		T320	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T127	16		T212	3		T152	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	1		T94	7		T13	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T6	1		T25	2		T215	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	3		T69	6		T72	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T93	18		T30	4		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T233	8		T223	10		T332	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T23	4		T89	7		T133	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T327	15		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T98	10		T82	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T329	1		T330	2		T331	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T148	16		T187	6		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	13		T128	4		T135	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T9	8		T29	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T124	14		T126	9		T68	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T23	1		T143	1		T89	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T32	12		T40	1		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T94	15		T127	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T125	2		T127	1		T129	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	1		T9	1		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	5		T126	11		T14	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T76	1		T102	12		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T76	1		T40	14		T125	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	10		T24	5		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	3		T123	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T102	14		T134	1		T68	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T89	2		T93	1		T94	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	4		T8	5		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T2	20		T7	29		T8	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T5	12		T9	1		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T327	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T82	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T331	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T148	21		T187	4		T84	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	14		T128	4		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T1	10		T9	9		T29	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T124	13		T144	9		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T23	2		T89	4		T333	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T32	11		T130	13		T179	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T94	24		T127	14		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T127	12		T130	14		T173	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	9		T33	12		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	4		T14	7		T209	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T141	7		T142	14		T173	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T40	7		T125	9		T135	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	10		T24	2		T28	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T123	7		T70	12		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T134	11		T213	2		T212	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T94	7		T13	4		T141	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T6	1		T127	16		T30	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T8	3		T9	1		T168	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T23	4		T89	7		T93	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1