Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23926

1

T1

44

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3288

1

T1

31

T3

3

T5

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20766

1

T1

44

T3

4

T4

17

auto[1]

6448

1

T1

31

T2

20

T5

39

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	778	1			T6	3		T8	19		T9	6
values[0]	70	1			T289	29		T296	1		T334	23
values[1]	712	1			T1	31		T9	17		T23	5
values[2]	2727	1			T2	20		T3	1		T7	29
values[3]	908	1			T24	7		T33	3		T40	21
values[4]	508	1			T98	10		T88	24		T14	22
values[5]	660	1			T6	5		T11	1		T40	1
values[6]	755	1			T9	4		T32	23		T28	1
values[7]	713	1			T5	27		T9	10		T125	2
values[8]	637	1			T3	3		T8	5		T11	1
values[9]	868	1			T5	12		T8	6		T76	1
minimum	17878	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	660	1			T1	20		T9	17		T23	5
values[1]	2850	1			T2	20		T3	1		T7	29
values[2]	827	1			T24	7		T98	10		T33	3
values[3]	543	1			T28	4		T130	18		T131	18
values[4]	616	1			T6	5		T9	1		T40	1
values[5]	733	1			T9	3		T11	1		T32	23
values[6]	752	1			T5	27		T8	5		T9	10
values[7]	582	1			T3	3		T5	12		T11	1
values[8]	895	1			T8	6		T23	3		T76	1
values[9]	190	1			T125	2		T143	1		T135	23
minimum	18566	1			T1	55		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	13		T23	5		T128	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	11		T102	1		T130	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1514	1			T2	2		T3	1		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T33	12		T133	7		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T24	4		T33	2		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T98	1		T88	13		T68	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T28	4		T130	15		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T208	1		T297	1		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	1		T40	1		T93	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	4		T89	5		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T143	1		T89	1		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	2		T11	1		T32	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T5	15		T8	3		T124	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	10		T135	11		T29	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T91	1		T128	1		T134	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	1		T5	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	5		T23	3		T102	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T76	1		T88	18		T89	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T125	1		T143	1		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T149	1		T292	8		T159	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18215	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	11		T76	1		T123	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	4		T128	3		T140	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	9		T102	13		T130	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T2	18		T7	26		T34	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T33	15		T73	3		T132	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T24	3		T33	1		T40	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T98	9		T88	11		T68	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T130	3		T131	17		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T319	8		T250	2		T25	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T126	8		T15	9		T152	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	1		T89	14		T205	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T89	1		T136	15		T72	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	1		T32	11		T129	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	12		T8	2		T124	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T135	2		T29	8		T213	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T128	7		T247	2		T278	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	2		T5	11		T94	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	1		T102	11		T94	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T88	12		T89	5		T209	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T125	1		T135	10		T233	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T292	3		T335	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T8	3		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T75	7		T244	2		T289	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	552	1			T6	3		T8	19		T9	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T127	15		T149	1		T301	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T336	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T289	17		T296	1		T334	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	13		T23	5		T128	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	22		T76	1		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T2	2		T3	1		T7	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T33	12		T133	7		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T24	4		T33	2		T40	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T68	1		T69	17		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	12		T297	1		T187	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T98	1		T88	13		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T40	1		T28	4		T93	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	4		T11	1		T89	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T89	1		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	2		T32	12		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	15		T125	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	10		T135	11		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	3		T124	14		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	1		T11	1		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T8	5		T102	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	1		T76	1		T88	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17736	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T125	1		T135	10		T243	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T277	11		T236	11		T337	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T336	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T289	12		T334	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	4		T128	3		T140	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	9		T102	13		T130	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T2	18		T7	26		T34	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T33	15		T73	3		T132	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T24	3		T33	1		T40	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T68	7		T13	7		T148	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	10		T187	4		T203	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T98	9		T88	11		T212	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T130	3		T126	8		T131	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	1		T89	14		T319	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T89	1		T72	13		T211	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	1		T32	11		T129	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	12		T125	1		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T135	2		T126	10		T29	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T124	13		T128	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	2		T94	5		T135	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	1		T102	11		T94	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	11		T88	12		T89	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	8		T23	1		T128	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	10		T102	14		T130	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T2	20		T3	1		T7	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T33	16		T133	1		T73	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T24	5		T33	2		T40	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T98	10		T88	12		T68	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T28	2		T130	4		T131	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T208	1		T297	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T40	1		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	4		T89	15		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T143	1		T89	2		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	2		T11	1		T32	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	13		T8	5		T124	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T135	3		T29	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T91	1		T128	8		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	3		T5	12		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	3		T23	1		T102	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T76	1		T88	13		T89	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T125	2		T143	1		T135	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T149	1		T292	9		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18385	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T1	1		T76	1		T123	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	9		T23	4		T128	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	10		T130	13		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T34	4		T127	12		T168	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T33	11		T133	6		T258	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T24	2		T33	1		T40	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T88	12		T69	16		T13	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T28	2		T130	14		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T147	9		T141	19		T223	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T93	18		T220	10		T69	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T6	1		T89	4		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T242	3		T210	2		T212	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T9	1		T32	11		T127	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	14		T124	13		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	9		T135	10		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T134	11		T247	4		T150	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T94	14		T135	13		T141	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	3		T23	2		T123	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T88	17		T89	7		T127	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T135	12		T179	18		T234	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T292	2		T159	9		T335	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T283	4		T197	1		T262	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T1	10		T123	12		T147	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	551	1			T6	3		T8	19		T9	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T127	1		T149	1		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T336	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T289	13		T296	1		T334	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	8		T23	1		T128	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	11		T76	1		T102	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T2	20		T3	1		T7	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T33	16		T133	1		T73	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T24	5		T33	2		T40	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T68	8		T69	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	15		T297	1		T187	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T98	10		T88	12		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	1		T28	2		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	4		T11	1		T89	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	1		T89	2		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	2		T32	12		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	13		T125	2		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	1		T135	3		T126	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	5		T124	14		T128	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	3		T11	1		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T8	3		T102	12		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	12		T76	1		T88	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17878	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T23	2		T123	7		T135	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T127	14		T301	6		T277	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T289	16		T334	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	9		T23	4		T128	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	20		T123	12		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1123	1			T34	4		T168	23		T214	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T33	11		T133	6		T225	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T24	2		T33	1		T40	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T69	16		T13	4		T148	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T14	7		T187	4		T203	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T88	12		T141	19		T212	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T28	2		T93	18		T220	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	1		T89	4		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T300	5		T333	10		T290	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	1		T32	11		T127	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	14		T130	12		T226	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	9		T135	10		T29	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T124	13		T134	11		T144	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T94	14		T135	13		T141	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	3		T94	17		T141	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T88	17		T89	7		T209	22

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1