Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23753

1

T1

44

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3461

1

T1

31

T3

1

T6

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21442

1

T1

75

T3

1

T4

17

auto[1]

5772

1

T2

20

T3

3

T5

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	370	1			T5	12		T8	6		T98	10
values[0]	9	1			T250	1		T84	4		T329	1
values[1]	652	1			T1	11		T5	27		T9	17
values[2]	662	1			T23	3		T124	27		T143	1
values[3]	650	1			T32	23		T40	1		T94	39
values[4]	821	1			T3	1		T9	10		T76	1
values[5]	730	1			T76	2		T34	9		T102	12
values[6]	699	1			T1	20		T24	7		T40	21
values[7]	539	1			T3	3		T102	14		T123	8
values[8]	469	1			T6	5		T8	5		T11	1
values[9]	3277	1			T2	20		T7	29		T9	4
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	536	1			T124	27		T143	1		T89	19
values[1]	710	1			T23	3		T94	39		T220	11
values[2]	827	1			T32	23		T123	13		T40	1
values[3]	670	1			T3	1		T9	10		T76	2
values[4]	789	1			T1	20		T76	1		T88	24
values[5]	617	1			T24	7		T123	8		T40	21
values[6]	2680	1			T2	20		T3	3		T7	29
values[7]	511	1			T6	5		T11	1		T40	1
values[8]	1133	1			T8	6		T9	4		T11	1
values[9]	150	1			T5	12		T23	5		T98	10
minimum	18591	1			T1	55		T4	17		T5	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T124	14		T135	13		T26	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T143	1		T89	5		T29	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T126	1		T68	1		T179	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T23	3		T94	26		T220	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T32	12		T40	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T123	13		T88	18		T127	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	5		T91	1		T127	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	1		T9	10		T76	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T76	1		T88	13		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	11		T129	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T123	8		T40	8		T125	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T24	4		T28	4		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1443	1			T2	2		T3	1		T7	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T8	3		T102	1		T127	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T40	1		T89	1		T94	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	4		T11	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T11	1		T125	1		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T8	5		T9	3		T93	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T5	1		T73	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T23	5		T98	1		T89	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18242	1			T1	44		T4	17		T5	35
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T1	11		T9	13		T148	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T124	13		T135	10		T213	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T89	14		T29	8		T187	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T126	8		T68	7		T259	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T94	13		T136	4		T73	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T32	11		T125	1		T129	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T88	12		T130	13		T72	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T34	4		T130	3		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T33	16		T102	11		T140	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T88	11		T126	10		T14	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	9		T131	9		T146	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T40	13		T125	9		T135	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T24	3		T135	17		T68	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T2	18		T3	2		T7	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T8	2		T102	13		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T89	1		T94	8		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	1		T128	7		T75	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T125	1		T72	12		T73	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T8	1		T9	1		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T5	11		T73	2		T204	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T98	9		T89	5		T18	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	13		T8	3		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T9	4		T148	15		T242	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T5	1		T69	7		T212	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	5		T98	1		T89	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T329	1		T330	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T250	1		T84	3		T338	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	15		T128	5		T135	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	11		T9	13		T29	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T124	14		T126	1		T68	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T23	3		T143	1		T89	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T32	12		T40	1		T130	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T94	26		T220	11		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T125	1		T91	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T9	10		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T76	1		T34	5		T88	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T76	1		T102	1		T146	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T40	8		T125	10		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	11		T24	4		T28	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T123	8		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T102	1		T134	12		T68	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T89	1		T93	1		T94	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	4		T8	3		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T2	2		T7	3		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T9	3		T23	5		T93	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T5	11		T251	6		T256	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	1		T98	9		T89	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T330	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T84	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	12		T128	3		T135	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	4		T29	8		T148	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T124	13		T126	8		T68	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T89	14		T136	4		T73	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T32	11		T130	5		T213	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T94	13		T131	12		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T125	1		T129	13		T130	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T33	16		T88	12		T130	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T34	4		T88	11		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T102	11		T146	7		T173	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T40	13		T125	9		T135	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	9		T24	3		T135	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	2		T70	11		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T102	13		T68	7		T140	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T89	1		T94	8		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T6	1		T8	2		T310	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T2	18		T7	26		T178	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T128	7		T75	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T124	14		T135	11		T26	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T143	1		T89	15		T29	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T126	9		T68	8		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T23	1		T94	15		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T32	12		T40	1		T125	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T123	1		T88	13		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T34	5		T91	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	1		T9	1		T76	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T76	1		T88	12		T126	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	10		T129	1		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T123	1		T40	14		T125	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	5		T28	2		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T2	20		T3	3		T7	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	5		T102	14		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T40	1		T89	2		T94	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	4		T11	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T11	1		T125	2		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T8	3		T9	3		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T5	12		T73	3		T204	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T23	1		T98	10		T89	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18409	1			T1	44		T4	17		T5	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T1	1		T9	8		T148	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T124	13		T135	12		T213	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T89	4		T29	1		T187	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T179	18		T231	11		T259	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T23	2		T94	24		T220	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T32	11		T130	13		T213	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T123	12		T88	17		T127	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T34	4		T127	12		T130	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	9		T33	12		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T88	12		T14	7		T209	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	10		T146	9		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T123	7		T40	7		T125	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T24	2		T28	2		T134	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1122	1			T168	23		T214	6		T320	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T127	16		T212	5		T152	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T94	7		T13	4		T141	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T6	1		T142	5		T216	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T69	6		T72	14		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T8	3		T9	1		T93	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T332	7		T339	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T23	4		T89	7		T138	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T5	14		T128	4		T230	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T1	10		T9	9		T148	21

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T5	12		T69	1		T212	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	3		T98	10		T89	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T329	1		T330	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T250	1		T84	3		T338	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	13		T128	4		T135	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	1		T9	8		T29	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T124	14		T126	9		T68	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T23	1		T143	1		T89	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T32	12		T40	1		T130	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T94	15		T220	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T125	2		T91	1		T129	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	1		T9	1		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T76	1		T34	5		T88	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T76	1		T102	12		T146	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	14		T125	10		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	10		T24	5		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	3		T123	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T102	14		T134	1		T68	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T89	2		T93	1		T94	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	4		T8	5		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T2	20		T7	29		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T9	3		T23	1		T93	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T69	6		T256	2		T227	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T8	3		T89	7		T138	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T84	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	14		T128	4		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	10		T9	9		T29	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T124	13		T144	5		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T23	2		T89	4		T144	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	11		T130	13		T179	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T94	24		T220	10		T69	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T130	14		T141	8		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	9		T33	12		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	4		T88	12		T127	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T146	9		T141	7		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T40	7		T125	9		T135	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	10		T24	2		T28	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T123	7		T70	12		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T134	11		T213	2		T212	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T94	7		T141	19		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T6	1		T127	16		T216	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T168	23		T214	6		T320	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	1		T23	4		T93	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1