Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23593

1

T1

55

T2

20

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3621

1

T1

20

T5

12

T6

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21359

1

T1

75

T3

1

T4

17

auto[1]

5855

1

T2

20

T3

3

T5

39

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	230	1			T28	1		T136	12		T241	1
values[0]	47	1			T11	1		T24	7		T287	7
values[1]	522	1			T3	3		T23	3		T76	1
values[2]	576	1			T3	1		T5	27		T34	9
values[3]	695	1			T9	3		T32	23		T102	12
values[4]	2954	1			T1	20		T2	20		T7	29
values[5]	760	1			T6	5		T9	1		T143	1
values[6]	781	1			T5	12		T28	4		T91	2
values[7]	613	1			T9	10		T23	5		T76	1
values[8]	736	1			T9	17		T123	13		T135	13
values[9]	964	1			T1	11		T98	10		T33	30
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	419	1			T3	4		T11	1		T23	3
values[1]	701	1			T5	27		T34	9		T102	12
values[2]	676	1			T1	20		T8	6		T9	3
values[3]	2928	1			T2	20		T7	29		T8	5
values[4]	693	1			T6	5		T9	1		T143	1
values[5]	874	1			T5	12		T28	4		T91	1
values[6]	571	1			T9	10		T23	5		T76	1
values[7]	809	1			T9	17		T98	10		T33	27
values[8]	871	1			T33	3		T102	14		T124	27
values[9]	97	1			T1	11		T136	12		T246	4
minimum	18575	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	2		T23	3		T24	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T11	1		T88	13		T89	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	15		T34	5		T94	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T102	1		T130	15		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	5		T125	1		T127	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	11		T9	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T2	2		T7	3		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T123	8		T89	8		T220	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T88	18		T91	1		T72	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	4		T9	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T28	4		T129	1		T69	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	1		T91	1		T135	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T23	5		T76	1		T135	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	10		T89	5		T93	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	13		T40	8		T73	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T98	1		T33	12		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T124	14		T143	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T33	2		T102	1		T123	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T1	11		T246	4		T321	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T136	1		T302	12		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18262	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T76	1		T297	1		T216	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	2		T24	3		T125	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T88	11		T89	1		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	12		T34	4		T94	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T102	11		T130	3		T15	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T8	1		T125	1		T26	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	9		T9	1		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T2	18		T7	26		T8	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T89	5		T128	3		T135	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T88	12		T72	13		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	1		T68	7		T29	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T129	13		T30	2		T14	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	11		T135	10		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T135	2		T68	7		T146	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T89	14		T131	21		T259	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	4		T40	13		T73	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T98	9		T33	15		T94	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T124	13		T94	5		T136	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T33	1		T102	13		T72	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T321	2		T77	14		T342	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T136	11		T257	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T8	3		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T237	13		T285	2		T77	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T28	1		T241	1		T140	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T136	1		T301	7		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T24	4		T287	7		T343	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T11	1		T308	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T23	3		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T76	1		T88	13		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T5	15		T34	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T89	1		T130	15		T31	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T125	1		T127	13		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	2		T32	12		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T2	2		T7	3		T8	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	11		T11	1		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T88	18		T72	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	4		T9	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T28	4		T91	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	1		T91	1		T135	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T23	5		T76	1		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	10		T89	5		T93	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	13		T135	11		T68	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T123	13		T131	2		T213	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	11		T124	14		T40	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T98	1		T33	14		T102	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T20	4		T216	14		T318	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T136	11		T251	14		T217	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T24	3		T309	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T308	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	2		T125	1		T148	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T88	11		T18	1		T236	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	12		T34	4		T125	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T89	1		T130	3		T252	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T125	1		T128	7		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	1		T32	11		T102	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T2	18		T7	26		T8	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	9		T135	17		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T88	12		T72	13		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	1		T89	5		T128	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T129	13		T30	2		T14	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	11		T135	10		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T146	10		T132	2		T211	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T89	14		T260	2		T271	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	4		T135	2		T68	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T131	21		T213	13		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T124	13		T40	13		T94	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T98	9		T33	16		T102	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	4		T23	1		T24	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	1		T88	12		T89	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	13		T34	5		T94	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T102	12		T130	4		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	3		T125	2		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	10		T9	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T2	20		T7	29		T8	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T123	1		T89	6		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T88	13		T91	1		T72	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	4		T9	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T28	2		T129	14		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	12		T91	1		T135	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T23	1		T76	1		T135	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	1		T89	15		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	8		T40	14		T73	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T98	10		T33	16		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T124	14		T143	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T33	2		T102	14		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T1	1		T246	1		T321	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T136	12		T302	1		T257	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18406	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T76	1		T297	1		T216	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T23	2		T24	2		T125	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T88	12		T141	7		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	14		T34	4		T94	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T130	14		T141	8		T15	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T127	12		T134	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	10		T9	1		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1108	1			T127	16		T168	23		T214	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T123	7		T89	7		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T88	17		T146	9		T231	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	1		T29	1		T13	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T28	2		T69	6		T30	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T135	12		T130	12		T213	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T23	4		T135	10		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T9	9		T89	4		T93	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	9		T40	7		T213	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T33	11		T94	7		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T124	13		T94	14		T133	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T33	1		T123	12		T69	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T1	10		T246	3		T77	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T302	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T152	7		T344	2		T345	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T285	10		T80	12		T230	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T28	1		T241	1		T140	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T136	12		T301	1		T251	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T24	5		T287	1		T343	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T11	1		T308	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	3		T23	1		T125	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T76	1		T88	12		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T5	13		T34	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T89	2		T130	4		T31	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T125	2		T127	1		T128	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	2		T32	12		T102	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T2	20		T7	29		T8	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	10		T11	1		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T88	13		T72	14		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	4		T9	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T28	2		T91	1		T129	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	12		T91	1		T135	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T23	1		T76	1		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	1		T89	15		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	8		T135	3		T68	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T123	1		T131	23		T213	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T124	14		T40	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T98	10		T33	18		T102	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T20	2		T216	16		T318	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T301	6		T302	11		T217	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T24	2		T287	6		T309	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T308	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T23	2		T148	21		T218	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T88	12		T141	7		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	14		T34	4		T125	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T130	14		T141	8		T252	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T127	12		T134	11		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	1		T32	11		T70	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T8	3		T127	16		T168	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	10		T123	7		T127	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T88	17		T146	9		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T89	7		T128	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T28	2		T69	6		T30	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T135	12		T130	12		T209	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T23	4		T146	11		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	9		T89	4		T93	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	9		T135	10		T213	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T123	12		T213	12		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	10		T124	13		T40	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T33	12		T94	7		T130	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1