Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	3		T24	5		T136	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T9	1		T33	2		T102	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T76	1		T40	1		T29	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T127	1		T232	1		T135	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T32	12		T89	15		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T98	10		T143	1		T89	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T2	20		T7	29		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T23	1		T89	6		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	12		T33	16		T40	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T88	12		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T133	1		T30	5		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	8		T123	1		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	3		T11	1		T124	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	1		T88	13		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T76	1		T34	5		T136	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	5		T125	12		T128	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	2		T123	1		T28	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	13		T6	4		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T231	1		T211	5		T233	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T20	1		T234	1		T216	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T1	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T24	2		T70	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	1		T72	14		T209	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	1		T146	11		T179	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T127	16		T135	10		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T32	11		T89	4		T220	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T242	3		T244	1		T221	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T9	9		T94	10		T168	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T23	4		T89	7		T127	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T33	11		T40	7		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T88	12		T134	11		T13	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T133	6		T30	4		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	9		T123	7		T94	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T124	13		T127	14		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	10		T88	17		T93	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	4		T142	14		T173	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T125	9		T135	12		T69	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T123	12		T28	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	14		T6	1		T23	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T231	11		T233	8		T227	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T234	17		T206	7		T245	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T1	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T228	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T229	1		T175	5		T238	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T230	1		T239	1		T240	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	3		T24	5		T136	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	10		T9	1		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	1		T29	13		T75	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	1		T73	3		T131	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T32	12		T76	1		T89	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T98	10		T143	1		T89	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T9	1		T11	1		T40	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T23	1		T89	6		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T2	20		T7	29		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	1		T91	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	12		T133	1		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	8		T88	12		T94	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	3		T11	1		T124	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	1		T123	1		T88	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T130	6		T136	5		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	5		T125	12		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T9	2		T76	1		T34	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	13		T6	4		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T228	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T230	7		T240	15		T159	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	3		T24	2		T70	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	10		T33	1		T72	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T29	1		T213	2		T145	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	16		T173	10		T244	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T32	11		T89	4		T220	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T135	10		T210	2		T221	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	9		T40	7		T94	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T23	4		T89	7		T127	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1129	1			T33	11		T168	23		T214	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T134	11		T69	6		T13	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T133	6		T30	4		T146	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	9		T88	12		T94	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T124	13		T127	14		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	10		T123	7		T88	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T130	13		T142	14		T247	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T125	9		T69	16		T14	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T9	1		T34	4		T123	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T5	14		T6	1		T23	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1