Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24021

1

T1

75

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3193

1

T3

3

T8

6

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T1

55

T3

3

T4

17

auto[1]

5617

1

T1

20

T2

20

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	295	1			T8	5		T40	1		T143	1
values[0]	1	1			T248	1		-	-		-	-
values[1]	750	1			T8	6		T34	9		T40	21
values[2]	791	1			T76	1		T98	10		T102	12
values[3]	612	1			T9	1		T23	3		T76	1
values[4]	762	1			T24	7		T76	1		T33	3
values[5]	2773	1			T2	20		T5	39		T7	29
values[6]	612	1			T3	3		T9	10		T11	1
values[7]	832	1			T1	20		T3	1		T9	17
values[8]	569	1			T6	5		T9	3		T23	5
values[9]	881	1			T1	11		T40	1		T28	4
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	807	1			T8	6		T98	10		T34	9
values[1]	756	1			T23	3		T76	1		T125	2
values[2]	680	1			T9	1		T76	1		T33	27
values[3]	2835	1			T2	20		T7	29		T10	3
values[4]	682	1			T5	39		T11	1		T136	5
values[5]	676	1			T1	20		T3	3		T9	10
values[6]	653	1			T3	1		T9	17		T23	5
values[7]	662	1			T6	5		T9	3		T32	23
values[8]	803	1			T1	11		T8	5		T40	1
values[9]	177	1			T40	1		T143	1		T131	13
minimum	18483	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T98	1		T102	1		T40	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	5		T34	5		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T76	1		T125	1		T89	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T23	3		T135	11		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T91	1		T127	13		T128	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T9	1		T76	1		T33	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T2	2		T7	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T33	2		T123	13		T142	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	16		T11	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T136	1		T69	17		T70	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	11		T9	10		T127	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	1		T11	1		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	1		T9	13		T125	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T23	5		T102	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	4		T9	2		T94	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T32	12		T123	8		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	11		T8	3		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T28	4		T130	14		T146	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T40	1		T143	1		T148	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T131	1		T249	1		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18246	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T89	8		T210	8		T217	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T98	9		T102	11		T40	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	1		T34	4		T213	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T125	1		T89	15		T135	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T135	2		T204	18		T251	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T128	3		T68	7		T16	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T33	15		T125	1		T88	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1075	1			T2	18		T7	26		T24	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T33	1		T212	3		T252	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	23		T126	10		T72	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T136	4		T70	11		T148	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	9		T73	13		T144	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	2		T68	7		T73	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	4		T125	9		T146	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T102	13		T136	15		T26	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T6	1		T9	1		T94	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	11		T128	7		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	2		T29	8		T73	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T130	5		T146	9		T173	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T148	15		T253	10		T254	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T131	12		T219	4		T199	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T8	3		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T89	5		T210	3		T217	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T8	3		T40	1		T143	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T255	1		T141	20		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T248	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T40	8		T143	1		T88	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	5		T34	5		T89	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T76	1		T98	1		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T135	11		T255	1		T204	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T127	13		T128	5		T68	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	1		T23	3		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T24	4		T76	1		T124	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T33	2		T123	13		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T2	2		T5	16		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T136	1		T69	17		T70	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	10		T69	7		T72	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	1		T11	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	11		T3	1		T9	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T133	7		T129	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	4		T9	2		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T23	5		T32	12		T123	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	11		T40	1		T134	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T28	4		T128	1		T130	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T8	2		T29	8		T148	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T218	5		T199	13		T20	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T40	13		T88	11		T135	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T8	1		T34	4		T89	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T98	9		T102	11		T125	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T135	2		T204	18		T251	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T128	3		T68	7		T233	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T33	15		T88	12		T130	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T24	3		T124	13		T94	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	1		T125	1		T252	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T2	18		T5	23		T7	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T136	4		T70	11		T148	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T72	13		T131	9		T13	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	2		T102	13		T68	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	9		T9	4		T125	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T136	15		T211	11		T242	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	1		T9	1		T94	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T32	11		T30	2		T26	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T73	3		T205	6		T213	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T128	7		T130	5		T136	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T98	10		T102	12		T40	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	3		T34	5		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T76	1		T125	2		T89	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T23	1		T135	3		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T91	1		T127	1		T128	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T9	1		T76	1		T33	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T2	20		T7	29		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T33	2		T123	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T5	25		T11	1		T126	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T136	5		T69	1		T70	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	10		T9	1		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	3		T11	1		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T9	8		T125	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T23	1		T102	14		T136	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	4		T9	2		T94	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T32	12		T123	1		T128	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T8	5		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T28	2		T130	6		T146	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T40	1		T143	1		T148	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T131	13		T249	1		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18402	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T89	6		T210	9		T217	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T40	7		T88	12		T220	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T8	3		T34	4		T213	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T89	4		T93	18		T135	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T23	2		T135	10		T150	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T127	12		T128	4		T16	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T33	11		T88	17		T130	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T24	2		T124	13		T94	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T33	1		T123	12		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	14		T72	14		T13	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T69	16		T70	12		T141	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	10		T9	9		T127	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T133	6		T231	11		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	9		T125	9		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T23	4		T145	6		T212	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	1		T9	1		T94	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T32	11		T123	7		T30	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	10		T29	1		T213	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T28	2		T130	13		T146	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T148	21		T256	12		T253	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T219	7		T199	15		T25	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T148	11		T187	4		T257	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T89	7		T210	2		T217	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T8	5		T40	1		T143	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T255	1		T141	1		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T248	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T40	14		T143	1		T88	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	3		T34	5		T89	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T76	1		T98	10		T102	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T135	3		T255	1		T204	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T127	1		T128	4		T68	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T9	1		T23	1		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T24	5		T76	1		T124	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T33	2		T123	1		T125	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T2	20		T5	25		T7	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T136	5		T69	1		T70	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	1		T69	1		T72	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	3		T11	1		T102	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	10		T3	1		T9	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T133	1		T129	1		T136	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	4		T9	2		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T23	1		T32	12		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T40	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T28	2		T128	8		T130	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T29	1		T148	21		T15	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T141	19		T218	5		T199	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T40	7		T88	12		T220	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T8	3		T34	4		T89	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T89	4		T93	18		T135	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T135	10		T150	8		T258	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T127	12		T128	4		T246	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T23	2		T33	11		T88	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T24	2		T124	13		T94	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T33	1		T123	12		T252	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T5	14		T168	23		T214	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T69	16		T70	12		T141	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	9		T69	6		T13	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T246	2		T259	10		T260	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	10		T9	9		T125	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T133	6		T145	6		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	1		T9	1		T94	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T23	4		T32	11		T123	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	10		T134	11		T213	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T28	2		T130	13		T146	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1