Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23904

1

T1

64

T2

20

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3310

1

T1

11

T5

39

T9

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21249

1

T1

64

T3

1

T4

17

auto[1]

5965

1

T1

11

T2

20

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	125	1			T9	1		T16	48		T268	24
values[0]	51	1			T3	1		T76	1		T207	1
values[1]	670	1			T125	19		T88	30		T89	19
values[2]	2931	1			T2	20		T7	29		T8	6
values[3]	558	1			T6	5		T76	1		T40	1
values[4]	678	1			T1	20		T5	12		T98	10
values[5]	504	1			T1	11		T11	1		T34	9
values[6]	565	1			T3	3		T9	10		T76	1
values[7]	759	1			T5	27		T9	20		T124	27
values[8]	826	1			T11	1		T24	7		T102	14
values[9]	1211	1			T8	5		T23	5		T32	23
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	988	1			T3	1		T8	6		T76	1
values[1]	2859	1			T2	20		T6	5		T7	29
values[2]	526	1			T40	21		T220	11		T135	31
values[3]	603	1			T1	20		T5	12		T11	1
values[4]	541	1			T129	1		T126	11		T70	24
values[5]	605	1			T1	11		T9	10		T76	1
values[6]	752	1			T3	3		T5	27		T9	20
values[7]	767	1			T24	7		T102	14		T125	2
values[8]	910	1			T8	5		T9	1		T23	5
values[9]	297	1			T89	13		T72	27		T14	22
minimum	18366	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	1		T8	5		T125	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T76	1		T128	5		T130	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T2	2		T6	4		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T23	3		T76	1		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T40	8		T139	2		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T220	11		T135	14		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	11		T11	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T145	7		T246	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T129	1		T70	13		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T126	1		T241	1		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T33	12		T124	14		T133	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	11		T9	10		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	1		T9	2		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T5	15		T9	13		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T24	4		T28	4		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T102	1		T125	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T8	3		T23	5		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	1		T33	2		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T89	8		T244	2		T234	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T72	15		T14	12		T242	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18212	1			T1	44		T4	17		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	1		T125	9		T89	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T128	3		T130	3		T213	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T2	18		T6	1		T7	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T102	11		T126	8		T72	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T40	13		T205	6		T251	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T135	17		T144	2		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	9		T98	9		T34	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T5	11		T215	12		T269	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T70	11		T131	9		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T126	10		T270	5		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T33	15		T124	13		T146	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T136	15		T131	12		T26	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	2		T9	1		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	12		T9	4		T88	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T24	3		T135	10		T129	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T102	13		T125	1		T136	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	2		T32	11		T94	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T33	1		T125	1		T89	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T89	5		T244	2		T271	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T72	12		T14	10		T242	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	1		T8	3		T9	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T272	11		T240	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T9	1		T16	27		T268	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T3	1		T273	1		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T76	1		T207	1		T25	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T125	10		T88	18		T89	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T128	5		T255	1		T213	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T2	2		T7	3		T8	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T23	3		T102	1		T130	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	4		T40	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T76	1		T220	11		T135	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	11		T98	1		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	1		T145	7		T246	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	1		T34	5		T123	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	11		T241	1		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T33	12		T133	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	10		T76	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	2		T124	14		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	15		T9	13		T88	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T24	4		T123	13		T135	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	1		T102	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T8	3		T23	5		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T33	2		T125	1		T89	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T272	9		T240	13		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T16	21		T268	12		T275	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T274	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T25	5		T268	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T125	9		T88	12		T89	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T128	3		T213	13		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T2	18		T7	26		T8	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T102	11		T130	3		T126	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T136	11		T212	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T135	17		T72	13		T144	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	9		T98	9		T40	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T5	11		T221	5		T152	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T34	4		T128	7		T70	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T270	5		T18	1		T276	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	2		T33	15		T131	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T126	10		T131	12		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T124	13		T13	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	12		T9	4		T88	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	3		T135	10		T129	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T102	13		T125	1		T136	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T8	2		T32	11		T89	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T33	1		T125	1		T89	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	1		T8	3		T125	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T76	1		T128	4		T130	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T2	20		T6	4		T7	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T23	1		T76	1		T102	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T40	14		T139	2		T205	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T220	1		T135	18		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	10		T11	1		T98	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T5	12		T145	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T129	1		T70	12		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T126	11		T241	1		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T33	16		T124	14		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T9	1		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	3		T9	2		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	13		T9	8		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T24	5		T28	2		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T102	14		T125	2		T136	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T8	5		T23	1		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T9	1		T33	2		T125	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T89	6		T244	4		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T72	13		T14	15		T242	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18349	1			T1	44		T4	17		T5	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	3		T125	9		T89	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T128	4		T130	14		T213	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1178	1			T6	1		T168	23		T214	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T23	2		T213	13		T277	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T40	7		T147	9		T278	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T220	10		T135	13		T144	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	10		T34	4		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T145	6		T246	3		T256	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T70	12		T146	9		T148	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T270	4		T18	1		T152	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T33	11		T124	13		T133	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T1	10		T9	9		T216	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T9	1		T141	19		T203	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	14		T9	9		T88	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T24	2		T28	2		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T30	4		T209	22		T225	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T23	4		T32	11		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	1		T94	7		T213	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T89	7		T234	17		T271	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T72	14		T14	7		T242	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T88	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T272	10		T240	14		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T9	1		T16	25		T268	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T3	1		T273	1		T274	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T76	1		T207	1		T25	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T125	10		T88	13		T89	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T128	4		T255	1		T213	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T2	20		T7	29		T8	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T23	1		T102	12		T130	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	4		T40	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T76	1		T220	1		T135	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T1	10		T98	10		T40	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	12		T145	1		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	1		T34	5		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T241	1		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	3		T33	16		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	1		T76	1		T126	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	2		T124	14		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	13		T9	8		T88	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T24	5		T123	1		T135	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	1		T102	14		T125	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T8	5		T23	1		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T33	2		T125	2		T89	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T272	10		T240	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T16	23		T268	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T25	4		T268	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T125	9		T88	17		T89	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T128	4		T213	12		T227	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T8	3		T168	23		T214	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T23	2		T130	14		T213	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T6	1		T179	18		T212	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T220	10		T135	13		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	10		T40	7		T127	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T145	6		T246	3		T221	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T34	4		T123	7		T134	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	10		T270	4		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T33	11		T133	6		T69	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T9	9		T216	16		T279	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	1		T124	13		T13	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	14		T9	9		T88	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T24	2		T123	12		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	16		T30	4		T209	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T23	4		T32	11		T28	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T33	1		T94	7		T72	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1