Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21580

1

T1

44

T3

1

T4

17

auto[ADC_CTRL_FILTER_COND_OUT]

5634

1

T1

31

T2

20

T3

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21476

1

T1

75

T3

4

T4

17

auto[1]

5738

1

T2

20

T5

27

T6

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	203	1			T34	9		T140	1		T31	2
values[0]	48	1			T94	19		T199	29		-	-
values[1]	810	1			T8	6		T11	1		T76	1
values[2]	680	1			T24	7		T125	2		T88	24
values[3]	710	1			T9	17		T23	5		T127	15
values[4]	726	1			T3	3		T9	3		T76	1
values[5]	506	1			T5	12		T6	5		T8	5
values[6]	738	1			T1	20		T5	27		T125	19
values[7]	638	1			T124	27		T40	1		T125	2
values[8]	543	1			T11	1		T76	1		T40	21
values[9]	3276	1			T1	11		T2	20		T3	1
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	670	1			T8	6		T11	1		T123	13
values[1]	2985	1			T2	20		T7	29		T10	3
values[2]	619	1			T9	20		T102	14		T93	1
values[3]	730	1			T3	3		T5	12		T76	1
values[4]	592	1			T6	5		T8	5		T9	1
values[5]	620	1			T1	20		T5	27		T125	19
values[6]	598	1			T11	1		T124	27		T40	1
values[7]	668	1			T9	10		T23	3		T76	1
values[8]	983	1			T1	11		T3	1		T32	23
values[9]	86	1			T34	9		T231	12		T235	8
minimum	18663	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	5		T11	1		T123	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T28	1		T136	2		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T125	1		T129	1		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1582	1			T2	2		T7	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	13		T102	1		T94	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	2		T93	1		T127	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	1		T76	1		T89	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T88	18		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	3		T9	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	4		T33	2		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	15		T28	4		T130	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	11		T125	10		T29	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T124	14		T125	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T40	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	10		T23	3		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T76	1		T40	1		T220	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T3	1		T127	17		T135	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	11		T32	12		T33	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T235	1		T201	3		T262	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T34	5		T231	12		T223	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18255	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T123	8		T94	11		T73	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	1		T130	3		T131	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T136	19		T173	2		T252	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T125	1		T146	9		T203	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1097	1			T2	18		T7	26		T24	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	4		T102	13		T94	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T140	12		T148	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	11		T89	14		T128	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	2		T88	12		T128	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	2		T148	1		T204	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	1		T33	1		T102	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	12		T130	5		T13	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	9		T125	9		T29	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T124	13		T125	1		T89	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T89	5		T129	13		T72	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T98	9		T135	2		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T130	13		T68	7		T146	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T135	17		T73	2		T205	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T32	11		T33	15		T40	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T235	7		T201	2		T262	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T34	4		T280	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T8	3		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T94	8		T73	3		T15	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T140	1		T281	1		T235	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T34	5		T31	2		T282	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T94	11		T199	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	5		T11	1		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T76	1		T123	8		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T125	1		T207	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	4		T88	13		T135	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	13		T129	1		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T23	5		T127	15		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T76	1		T102	1		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T9	2		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	1		T8	3		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T6	4		T33	2		T94	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	15		T28	4		T13	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	11		T125	10		T29	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T124	14		T125	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	1		T143	1		T89	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T136	1		T139	1		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T76	1		T40	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T3	1		T9	10		T23	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1571	1			T1	11		T2	2		T7	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T235	7		T283	10		T197	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T34	4		T282	9		T284	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T94	8		T199	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T130	3		T131	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T136	19		T73	3		T15	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T125	1		T210	3		T218	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T24	3		T88	11		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	4		T146	9		T203	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T126	8		T140	12		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T102	13		T89	14		T94	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	2		T9	1		T102	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	11		T8	2		T226	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T6	1		T33	1		T94	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	12		T13	7		T212	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	9		T125	9		T29	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T124	13		T125	1		T89	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T89	5		T129	13		T72	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T136	11		T213	13		T285	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	13		T130	13		T146	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T98	9		T135	19		T73	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1098	1			T2	18		T7	26		T32	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	3		T11	1		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T28	1		T136	21		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T125	2		T129	1		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1431	1			T2	20		T7	29		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	8		T102	14		T94	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	2		T93	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T5	12		T76	1		T89	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	3		T88	13		T128	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	5		T9	1		T148	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	4		T33	2		T102	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	13		T28	2		T130	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	10		T125	10		T29	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T124	14		T125	2		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	1		T40	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	1		T23	1		T98	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T76	1		T40	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T3	1		T127	1		T135	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	1		T32	12		T33	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T235	8		T201	3		T262	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T34	5		T231	1		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18409	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T123	1		T94	9		T73	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	3		T123	12		T93	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T173	4		T252	11		T199	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	9		T150	12		T203	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1248	1			T23	4		T24	2		T88	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T9	9		T94	7		T30	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	1		T127	14		T148	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T89	4		T128	4		T70	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T88	17		T16	23		T215	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T212	3		T216	16		T217	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T6	1		T33	1		T94	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	14		T28	2		T130	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T1	10		T125	9		T29	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T124	13		T134	11		T218	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T89	7		T72	14		T14	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	9		T23	2		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T220	10		T133	6		T130	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T127	16		T135	13		T221	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	10		T32	11		T33	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T201	2		T222	7		T286	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T34	4		T231	11		T223	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T231	11		T270	4		T279	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T123	7		T94	10		T141	19

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T140	1		T281	1		T235	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T34	5		T31	2		T282	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T94	9		T199	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	3		T11	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T76	1		T123	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T125	2		T207	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T24	5		T88	12		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	8		T129	1		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T23	1		T127	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T76	1		T102	14		T89	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	3		T9	2		T102	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	12		T8	5		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	4		T33	2		T94	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	13		T28	2		T13	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	10		T125	10		T29	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T124	14		T125	2		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T40	1		T143	1		T89	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T136	12		T139	1		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	1		T76	1		T40	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T3	1		T9	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1437	1			T1	1		T2	20		T7	29
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T283	13		T197	1		T287	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T34	4		T223	12		T288	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T94	10		T199	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	3		T123	12		T93	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T123	7		T141	19		T15	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T210	2		T150	12		T258	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T24	2		T88	12		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	9		T146	9		T145	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T23	4		T127	14		T148	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T89	4		T94	7		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	1		T88	17		T16	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T226	2		T212	3		T216	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T6	1		T33	1		T94	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	14		T28	2		T13	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	10		T125	9		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T124	13		T134	11		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T89	7		T72	14		T14	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T213	15		T227	15		T285	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	7		T220	10		T133	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T9	9		T23	2		T127	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1232	1			T1	10		T32	11		T33	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1