Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23926

1

T1

44

T2

20

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3288

1

T1

31

T5

12

T6

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21061

1

T1

44

T3

4

T4

17

auto[1]

6153

1

T1

31

T2

20

T5

39

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	473	1			T6	3		T8	19		T9	6
values[0]	78	1			T123	13		T244	4		T289	29
values[1]	686	1			T1	11		T9	17		T23	5
values[2]	2809	1			T1	20		T2	20		T3	1
values[3]	783	1			T24	7		T33	3		T40	21
values[4]	653	1			T98	10		T88	24		T93	1
values[5]	616	1			T6	5		T11	1		T40	1
values[6]	687	1			T9	4		T32	23		T89	2
values[7]	754	1			T5	27		T9	10		T125	2
values[8]	635	1			T3	3		T8	5		T11	1
values[9]	1162	1			T5	12		T8	6		T23	3
minimum	17878	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	860	1			T1	31		T9	17		T23	5
values[1]	2905	1			T2	20		T3	1		T7	29
values[2]	765	1			T24	7		T33	3		T125	19
values[3]	561	1			T98	10		T130	18		T131	18
values[4]	660	1			T6	5		T11	1		T28	4
values[5]	740	1			T9	4		T32	23		T40	1
values[6]	687	1			T5	27		T8	5		T9	10
values[7]	600	1			T3	3		T5	12		T11	1
values[8]	903	1			T8	6		T23	3		T76	1
values[9]	191	1			T125	2		T143	1		T135	23
minimum	18342	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	13		T23	5		T123	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	22		T76	1		T91	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1501	1			T2	2		T3	1		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T33	12		T102	1		T133	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T24	4		T33	2		T125	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T88	13		T68	1		T69	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T130	15		T208	1		T141	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T98	1		T131	1		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	1		T28	4		T93	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	4		T89	5		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	1		T40	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	2		T32	12		T127	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	15		T8	3		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	10		T135	11		T29	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T11	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	1		T76	1		T124	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	5		T40	1		T94	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T23	3		T76	1		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T143	1		T135	13		T179	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T125	1		T129	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18195	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T147	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	4		T128	3		T140	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	9		T130	5		T75	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T2	18		T7	26		T34	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	15		T102	13		T132	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	3		T33	1		T125	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T88	11		T68	7		T13	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T130	3		T187	4		T203	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T98	9		T131	17		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T126	8		T199	13		T290	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	1		T89	14		T205	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T89	1		T129	13		T136	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	1		T32	11		T136	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	12		T8	2		T125	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T135	2		T29	8		T213	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	2		T128	7		T126	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T5	11		T124	13		T94	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	1		T94	16		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T102	11		T88	12		T89	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T135	10		T233	8		T291	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T125	1		T292	3		T293	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	458	1			T6	3		T8	19		T9	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T294	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T123	13		T289	17		T295	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T244	2		T296	1		T77	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	13		T23	5		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	11		T76	1		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1464	1			T2	2		T3	1		T7	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	11		T33	12		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T24	4		T33	2		T40	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T133	7		T68	1		T69	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T93	1		T208	1		T297	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T98	1		T88	13		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	1		T40	1		T28	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	4		T89	5		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T89	1		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	2		T32	12		T127	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	15		T125	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	10		T135	11		T29	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	1		T8	3		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T76	1		T124	14		T89	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T8	5		T40	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T5	1		T23	3		T76	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17736	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T294	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T289	12		T298	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T244	2		T77	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	4		T140	12		T252	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T102	13		T130	5		T75	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T2	18		T7	26		T34	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	9		T33	15		T132	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T24	3		T33	1		T40	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T68	7		T13	7		T212	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T203	8		T235	7		T152	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T98	9		T88	11		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T130	3		T126	8		T199	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	1		T89	14		T131	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T89	1		T129	13		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	1		T32	11		T136	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	12		T125	1		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T135	2		T29	8		T213	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	2		T8	2		T128	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T124	13		T89	5		T94	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T8	1		T94	16		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	11		T102	11		T125	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T9	8		T23	1		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	11		T76	1		T91	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T2	20		T3	1		T7	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T33	16		T102	14		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T24	5		T33	2		T125	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T88	12		T68	8		T69	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T130	4		T208	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T98	10		T131	18		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T28	2		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	4		T89	15		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	1		T40	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	2		T32	12		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	13		T8	5		T125	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T135	3		T29	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	3		T11	1		T128	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	12		T76	1		T124	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T8	3		T40	1		T94	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T23	1		T76	1		T102	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T143	1		T135	11		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T125	2		T129	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18337	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T147	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	9		T23	4		T123	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	20		T130	13		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T34	4		T40	7		T127	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T33	11		T133	6		T258	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	2		T33	1		T125	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T88	12		T69	16		T13	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T130	14		T141	19		T187	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T146	9		T14	7		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T28	2		T93	18		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	1		T89	4		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T242	3		T212	1		T16	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	1		T32	11		T127	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	14		T130	12		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	9		T135	10		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T134	11		T148	11		T247	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T124	13		T94	14		T135	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	3		T94	17		T141	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T23	2		T123	7		T88	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T135	12		T179	18		T233	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T234	11		T292	2		T286	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T147	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	458	1			T6	3		T8	19		T9	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T294	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T123	1		T289	13		T295	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T244	4		T296	1		T77	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	8		T23	1		T140	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	1		T76	1		T102	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T2	20		T3	1		T7	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	10		T33	16		T132	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T24	5		T33	2		T40	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T133	1		T68	8		T69	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T93	1		T208	1		T297	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T98	10		T88	12		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	1		T40	1		T28	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	4		T89	15		T131	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	1		T89	2		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	2		T32	12		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	13		T125	2		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T135	3		T29	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	3		T8	5		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T76	1		T124	14		T89	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T8	3		T40	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T5	12		T23	1		T76	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17878	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T294	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T123	12		T289	16		T295	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T80	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	9		T23	4		T252	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	10		T130	13		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T34	4		T168	23		T214	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T1	10		T33	11		T258	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T24	2		T33	1		T40	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T133	6		T69	16		T13	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T141	19		T203	8		T299	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T88	12		T146	9		T14	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T28	2		T93	18		T220	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T6	1		T89	4		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T130	12		T300	5		T290	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	1		T32	11		T127	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	14		T226	2		T30	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T9	9		T135	10		T29	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T134	11		T144	5		T148	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T124	13		T89	7		T94	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	3		T94	17		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T23	2		T123	7		T88	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1