Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23625

1

T1

55

T2

20

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3589

1

T1

20

T5

12

T6

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21342

1

T1

75

T3

1

T4

17

auto[1]

5872

1

T2

20

T3

3

T5

39

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	75	1			T212	5		T301	7		T20	8
values[0]	93	1			T11	1		T24	7		T129	1
values[1]	485	1			T3	3		T23	3		T76	1
values[2]	558	1			T3	1		T5	27		T34	9
values[3]	747	1			T9	3		T32	23		T102	12
values[4]	2915	1			T1	20		T2	20		T7	29
values[5]	770	1			T6	5		T143	1		T88	30
values[6]	723	1			T5	12		T9	1		T28	4
values[7]	657	1			T9	10		T23	5		T76	1
values[8]	681	1			T9	17		T123	13		T135	13
values[9]	1174	1			T1	11		T98	10		T33	30
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	651	1			T3	4		T11	1		T23	3
values[1]	660	1			T5	27		T34	9		T102	12
values[2]	776	1			T1	20		T8	6		T9	3
values[3]	2906	1			T2	20		T7	29		T8	5
values[4]	660	1			T6	5		T9	1		T143	1
values[5]	859	1			T91	1		T93	19		T135	23
values[6]	568	1			T5	12		T9	10		T23	5
values[7]	751	1			T9	17		T98	10		T33	27
values[8]	818	1			T33	3		T102	14		T124	27
values[9]	222	1			T1	11		T136	12		T246	4
minimum	18343	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	2		T23	3		T24	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	1		T76	1		T88	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	15		T34	5		T94	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T102	1		T130	15		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	5		T125	1		T127	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	11		T9	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T2	2		T7	3		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T123	8		T89	8		T220	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T91	1		T241	1		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	4		T9	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T129	1		T69	7		T30	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T91	1		T93	19		T135	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T23	5		T76	1		T28	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	1		T9	10		T89	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	13		T40	8		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T98	1		T33	12		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T124	14		T143	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T33	2		T102	1		T123	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T1	11		T246	4		T20	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T136	1		T20	1		T302	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18199	1			T1	44		T4	17		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	2		T24	3		T125	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T88	11		T89	1		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	12		T34	4		T94	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T102	11		T130	3		T15	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	1		T125	1		T126	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	9		T9	1		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T2	18		T7	26		T8	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T89	5		T128	3		T135	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	9		T209	17		T148	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	1		T68	7		T29	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T129	13		T30	2		T14	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T135	10		T130	13		T73	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T135	2		T68	7		T146	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T5	11		T89	14		T131	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T9	4		T40	13		T213	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T98	9		T33	15		T130	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T124	13		T94	5		T136	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T33	1		T102	13		T94	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T20	4		T216	14		T283	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T136	11		T257	4		T303	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T8	3		T9	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T212	3		T20	4		T273	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T301	7		T304	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T24	4		T305	1		T287	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T11	1		T129	1		T306	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T23	3		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T76	1		T88	13		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	1		T5	15		T34	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T89	1		T130	15		T31	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T125	1		T127	13		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T9	2		T32	12		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T2	2		T7	3		T8	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	11		T11	1		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T88	18		T72	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	4		T143	1		T89	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T28	4		T91	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T9	1		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T23	5		T76	1		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	10		T89	5		T93	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	13		T135	11		T68	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T123	13		T131	2		T213	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	11		T124	14		T40	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T98	1		T33	14		T102	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T212	2		T20	4		T77	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T304	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T24	3		T305	2		T307	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T285	2		T308	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	2		T125	1		T148	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T88	11		T18	1		T289	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	12		T34	4		T125	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T89	1		T130	3		T252	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T125	1		T128	7		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	1		T32	11		T102	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T2	18		T7	26		T8	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	9		T135	17		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T88	12		T72	13		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T89	5		T128	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T129	13		T30	2		T14	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	11		T135	10		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T146	10		T132	2		T204	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T89	14		T131	17		T260	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T9	4		T135	2		T68	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T131	21		T213	13		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T124	13		T40	13		T94	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T98	9		T33	16		T102	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	4		T23	1		T24	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	1		T76	1		T88	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	13		T34	5		T94	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T102	12		T130	4		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	3		T125	2		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	10		T9	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T2	20		T7	29		T8	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T123	1		T89	6		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T91	1		T241	1		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	4		T9	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T129	14		T69	1		T30	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T91	1		T93	1		T135	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T23	1		T76	1		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	12		T9	1		T89	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	8		T40	14		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T98	10		T33	16		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T124	14		T143	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T33	2		T102	14		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T1	1		T246	1		T20	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T136	12		T20	1		T302	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18341	1			T1	44		T4	17		T5	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T23	2		T24	2		T125	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T88	12		T141	7		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	14		T34	4		T94	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T130	14		T141	8		T15	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	3		T127	12		T134	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	10		T9	1		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T88	17		T127	16		T168	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T123	7		T89	7		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T146	9		T209	22		T231	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	1		T29	1		T13	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T69	6		T30	4		T14	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T93	18		T135	12		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T23	4		T28	2		T135	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T9	9		T89	4		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	9		T40	7		T213	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T33	11		T130	13		T213	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T124	13		T94	14		T133	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T33	1		T123	12		T94	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T1	10		T246	3		T20	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T302	11		T303	15		T159	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T309	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T212	4		T20	6		T273	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T301	1		T304	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T24	5		T305	3		T287	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T11	1		T129	1		T306	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	3		T23	1		T125	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T76	1		T88	12		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T5	13		T34	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T89	2		T130	4		T31	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T125	2		T127	1		T128	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T9	2		T32	12		T102	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T2	20		T7	29		T8	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	10		T11	1		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T88	13		T72	14		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	4		T143	1		T89	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T28	2		T91	1		T129	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	12		T9	1		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T23	1		T76	1		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	1		T89	15		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	8		T135	3		T68	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T123	1		T131	23		T213	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	1		T124	14		T40	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T98	10		T33	18		T102	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T212	1		T20	2		T77	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T301	6		T304	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T24	2		T287	6		T307	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T285	10		T308	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T23	2		T148	21		T218	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T88	12		T141	15		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	14		T34	4		T125	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T130	14		T252	11		T227	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T127	12		T134	11		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	1		T32	11		T70	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1118	1			T8	3		T127	16		T168	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	10		T123	7		T127	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T88	17		T146	9		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	1		T89	7		T128	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T28	2		T69	6		T30	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T135	12		T130	12		T213	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T23	4		T146	11		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	9		T89	4		T93	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	9		T135	10		T213	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T123	12		T213	12		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	10		T124	13		T40	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T33	12		T94	7		T130	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1