Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

75

T2

20

T3

4

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23653

1

T1

64

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3561

1

T1

11

T3

3

T5

39

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21399

1

T1

44

T3

1

T4

17

auto[1]

5815

1

T1

31

T2

20

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23170

1

T1

66

T2

2

T3

2

auto[1]

4044

1

T1

9

T2

18

T3

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T131	18		T310	12		-	-
values[0]	73	1			T276	1		T25	20		T311	16
values[1]	578	1			T24	7		T34	9		T40	21
values[2]	539	1			T1	20		T133	7		T129	14
values[3]	681	1			T5	39		T9	17		T76	1
values[4]	764	1			T9	10		T11	2		T76	1
values[5]	606	1			T6	5		T8	6		T9	1
values[6]	709	1			T1	11		T23	3		T32	23
values[7]	863	1			T3	3		T76	1		T125	2
values[8]	2870	1			T2	20		T7	29		T8	5
values[9]	1165	1			T3	1		T23	5		T33	3
minimum	18336	1			T1	44		T4	17		T5	21

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	745	1			T24	7		T34	9		T40	21
values[1]	503	1			T1	20		T133	7		T129	14
values[2]	818	1			T5	39		T9	27		T11	1
values[3]	714	1			T9	1		T11	1		T98	10
values[4]	671	1			T1	11		T8	6		T32	23
values[5]	687	1			T3	3		T6	5		T23	3
values[6]	3020	1			T2	20		T7	29		T10	3
values[7]	838	1			T8	5		T9	3		T23	5
values[8]	728	1			T102	12		T40	1		T91	1
values[9]	128	1			T3	1		T126	11		T310	12
minimum	18362	1			T1	44		T4	17		T5	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

3919

1

T1

20

T5

14

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T34	5		T28	4		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T24	4		T40	8		T91	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T1	11		T129	1		T75	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T133	7		T209	23		T225	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T124	14		T125	10		T89	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	16		T9	23		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T89	1		T129	1		T68	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	1		T11	1		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T8	5		T32	12		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	11		T102	1		T123	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T125	1		T28	1		T68	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T6	4		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T2	2		T7	3		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T73	1		T131	2		T138	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T9	2		T23	5		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	3		T127	17		T130	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T102	1		T40	1		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T127	13		T70	13		T146	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T3	1		T251	1		T312	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T126	1		T310	1		T156	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T231	12		T293	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	4		T146	7		T205	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T24	3		T40	13		T94	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T1	9		T129	13		T75	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T209	17		T242	7		T289	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T124	13		T125	9		T89	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	23		T9	4		T130	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T89	1		T68	7		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T98	9		T33	15		T94	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	1		T32	11		T136	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T102	13		T125	1		T128	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T125	1		T68	7		T213	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	2		T6	1		T13	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1098	1			T2	18		T7	26		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T73	3		T131	21		T132	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	1		T33	1		T88	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	2		T130	13		T126	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T102	11		T131	17		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T70	11		T146	9		T140	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T251	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T126	10		T310	11		T282	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T293	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T131	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T310	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T25	10		T313	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T276	1		T311	10		T314	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T34	5		T28	4		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T24	4		T40	8		T91	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	11		T129	1		T75	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T133	7		T136	1		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T125	10		T213	3		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	16		T9	13		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T124	14		T89	8		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T9	10		T11	2		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	5		T89	1		T68	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	4		T9	1		T33	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T32	12		T28	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	11		T23	3		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T76	1		T125	1		T94	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T131	1		T315	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T2	2		T7	3		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	3		T127	17		T130	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T3	1		T23	5		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T127	13		T126	1		T70	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18194	1			T1	44		T4	17		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T131	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T310	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T25	10		T313	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T311	6		T314	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T34	4		T205	6		T244	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T24	3		T40	13		T94	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	9		T129	13		T75	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T136	4		T242	7		T251	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T125	9		T204	6		T270	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	23		T9	4		T130	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T124	13		T89	5		T173	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T98	9		T94	8		T135	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	1		T89	1		T68	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	1		T33	15		T102	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T32	11		T136	11		T173	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	7		T243	13		T316	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T125	1		T94	5		T68	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	2		T131	12		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T2	18		T7	26		T9	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	2		T130	13		T126	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T33	1		T102	11		T88	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T126	10		T70	11		T72	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T8	3		T9	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	5		T28	2		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T24	5		T40	14		T91	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	10		T129	14		T75	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T133	1		T209	18		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T124	14		T125	10		T89	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	25		T9	9		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T89	2		T129	1		T68	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T11	1		T98	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	3		T32	12		T136	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	1		T102	14		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T125	2		T28	1		T68	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	3		T6	4		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T2	20		T7	29		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T73	4		T131	23		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T9	2		T23	1		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	5		T127	1		T130	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T102	12		T40	1		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T127	1		T70	12		T146	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T3	1		T251	7		T312	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T126	11		T310	12		T156	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T231	1		T293	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T34	4		T28	2		T146	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T24	2		T40	7		T94	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T1	10		T150	8		T301	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T133	6		T209	22		T225	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T124	13		T125	9		T89	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	14		T9	18		T130	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T147	4		T173	9		T219	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	11		T93	18		T94	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	3		T32	11		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	10		T123	12		T220	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T213	12		T141	8		T173	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T23	2		T69	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T94	14		T168	23		T214	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T138	11		T147	9		T247	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T23	4		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	16		T130	12		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T146	11		T299	12		T227	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T127	12		T70	12		T146	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T312	5		T266	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T202	13		T190	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T231	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T131	18		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T310	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T25	12		T313	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T276	1		T311	7		T314	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T34	5		T28	2		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T24	5		T40	14		T91	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	10		T129	14		T75	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T133	1		T136	5		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T125	10		T213	1		T204	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	25		T9	8		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T124	14		T89	6		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T9	1		T11	2		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	3		T89	2		T68	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	4		T9	1		T33	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T32	12		T28	1		T136	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T23	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T76	1		T125	2		T94	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	3		T131	13		T315	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T2	20		T7	29		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	5		T127	1		T130	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T3	1		T23	1		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T127	1		T126	11		T70	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18336	1			T1	44		T4	17		T5	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T25	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T311	9		T314	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T34	4		T28	2		T218	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	2		T40	7		T94	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T1	10		T146	9		T270	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T133	6		T225	6		T242	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T125	9		T213	2		T161	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	14		T9	9		T130	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T124	13		T89	7		T173	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	9		T93	18		T94	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	3		T144	9		T147	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T6	1		T33	11		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T32	11		T145	6		T141	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	10		T23	2		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T94	14		T213	12		T141	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T147	9		T247	4		T252	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T9	1		T88	12		T89	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T127	16		T130	12		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T23	4		T33	1		T123	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T127	12		T70	12		T146	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23295

1

T1

55

T2

20

T3

4

auto[1]

auto[0]

3919

1

T1

20

T5

14

T6

1