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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.59


Total test records in report: 918
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T795 /workspace/coverage/default/17.adc_ctrl_filters_both.4081248953 Jun 23 05:55:54 PM PDT 24 Jun 23 05:56:58 PM PDT 24 167358694119 ps
T796 /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3056598996 Jun 23 05:57:51 PM PDT 24 Jun 23 06:11:01 PM PDT 24 323976505190 ps
T797 /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2721328568 Jun 23 05:56:14 PM PDT 24 Jun 23 06:07:23 PM PDT 24 327491887313 ps
T46 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2195487166 Jun 23 06:16:24 PM PDT 24 Jun 23 06:16:31 PM PDT 24 8864921549 ps
T116 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2327577267 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:21 PM PDT 24 395335590 ps
T798 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2590287555 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:21 PM PDT 24 401733652 ps
T49 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.210179811 Jun 23 06:16:06 PM PDT 24 Jun 23 06:16:09 PM PDT 24 988033768 ps
T78 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.727593352 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:08 PM PDT 24 451408229 ps
T799 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1458791464 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:22 PM PDT 24 483341559 ps
T800 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2189660433 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:26 PM PDT 24 413388384 ps
T50 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.321766759 Jun 23 06:16:12 PM PDT 24 Jun 23 06:16:15 PM PDT 24 522963130 ps
T54 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1904641560 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:07 PM PDT 24 544079213 ps
T117 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.592162832 Jun 23 06:16:01 PM PDT 24 Jun 23 06:16:03 PM PDT 24 416520504 ps
T47 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4025545436 Jun 23 06:16:12 PM PDT 24 Jun 23 06:16:33 PM PDT 24 8144301164 ps
T56 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1594763322 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:24 PM PDT 24 547538056 ps
T801 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3569075125 Jun 23 06:16:24 PM PDT 24 Jun 23 06:16:26 PM PDT 24 287954567 ps
T48 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2913463570 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:31 PM PDT 24 8610886283 ps
T42 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2110779913 Jun 23 06:16:11 PM PDT 24 Jun 23 06:16:16 PM PDT 24 3561650987 ps
T802 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.388590870 Jun 23 06:16:24 PM PDT 24 Jun 23 06:16:26 PM PDT 24 491856879 ps
T43 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1203271924 Jun 23 06:15:59 PM PDT 24 Jun 23 06:16:02 PM PDT 24 2404458793 ps
T60 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1215792881 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:23 PM PDT 24 747908228 ps
T55 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3771753608 Jun 23 06:16:17 PM PDT 24 Jun 23 06:16:18 PM PDT 24 525327412 ps
T803 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.695083018 Jun 23 06:16:28 PM PDT 24 Jun 23 06:16:29 PM PDT 24 328020781 ps
T118 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.805190175 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:21 PM PDT 24 602697129 ps
T804 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.97862142 Jun 23 06:16:33 PM PDT 24 Jun 23 06:16:34 PM PDT 24 354045937 ps
T96 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.115899731 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:26 PM PDT 24 4105500372 ps
T805 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.181728570 Jun 23 06:16:29 PM PDT 24 Jun 23 06:16:31 PM PDT 24 382697928 ps
T45 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2479967499 Jun 23 06:16:02 PM PDT 24 Jun 23 06:16:04 PM PDT 24 553603070 ps
T44 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.663600503 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:29 PM PDT 24 2627261087 ps
T806 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3199292561 Jun 23 06:15:59 PM PDT 24 Jun 23 06:16:04 PM PDT 24 4806500235 ps
T807 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3080184954 Jun 23 06:16:26 PM PDT 24 Jun 23 06:16:27 PM PDT 24 436683343 ps
T808 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1581851761 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:24 PM PDT 24 383065564 ps
T61 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.809825390 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:25 PM PDT 24 777449870 ps
T122 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.934762026 Jun 23 06:16:06 PM PDT 24 Jun 23 06:16:09 PM PDT 24 1012450056 ps
T59 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3290108477 Jun 23 06:16:12 PM PDT 24 Jun 23 06:16:15 PM PDT 24 576015695 ps
T809 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1841594825 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:22 PM PDT 24 350833036 ps
T103 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.767565084 Jun 23 06:16:15 PM PDT 24 Jun 23 06:16:16 PM PDT 24 845598663 ps
T810 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.231074961 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:24 PM PDT 24 387241086 ps
T811 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2883480387 Jun 23 06:16:29 PM PDT 24 Jun 23 06:16:31 PM PDT 24 385481489 ps
T57 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2696150061 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:26 PM PDT 24 810504160 ps
T119 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.748934748 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:27 PM PDT 24 2599229983 ps
T104 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1655463693 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:34 PM PDT 24 24367188094 ps
T812 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3811548815 Jun 23 06:16:12 PM PDT 24 Jun 23 06:16:58 PM PDT 24 26085443024 ps
T105 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1974609396 Jun 23 06:16:06 PM PDT 24 Jun 23 06:17:08 PM PDT 24 50709647432 ps
T120 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.191494298 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:24 PM PDT 24 521553117 ps
T58 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.491455417 Jun 23 06:16:02 PM PDT 24 Jun 23 06:16:08 PM PDT 24 4632585085 ps
T62 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3003784923 Jun 23 06:15:56 PM PDT 24 Jun 23 06:15:58 PM PDT 24 372466105 ps
T813 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4193553067 Jun 23 06:16:12 PM PDT 24 Jun 23 06:16:16 PM PDT 24 321418973 ps
T814 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1670985453 Jun 23 06:16:27 PM PDT 24 Jun 23 06:16:29 PM PDT 24 400133259 ps
T121 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4278504603 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:27 PM PDT 24 4734087967 ps
T815 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.77619265 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:22 PM PDT 24 375958129 ps
T816 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1381729845 Jun 23 06:16:27 PM PDT 24 Jun 23 06:16:28 PM PDT 24 447447285 ps
T817 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2465469953 Jun 23 06:16:25 PM PDT 24 Jun 23 06:16:26 PM PDT 24 625255397 ps
T818 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1259340653 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:23 PM PDT 24 351414394 ps
T819 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1762763531 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:07 PM PDT 24 535742992 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.192948301 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:24 PM PDT 24 498435208 ps
T821 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3390989140 Jun 23 06:16:12 PM PDT 24 Jun 23 06:16:13 PM PDT 24 475439958 ps
T822 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2417003546 Jun 23 06:16:14 PM PDT 24 Jun 23 06:16:18 PM PDT 24 2902328238 ps
T823 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3178743331 Jun 23 06:16:17 PM PDT 24 Jun 23 06:16:20 PM PDT 24 5016044500 ps
T824 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4125635497 Jun 23 06:16:16 PM PDT 24 Jun 23 06:16:20 PM PDT 24 1117101269 ps
T825 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2192486076 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:08 PM PDT 24 2182254118 ps
T826 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1748984877 Jun 23 06:16:13 PM PDT 24 Jun 23 06:16:17 PM PDT 24 2707765577 ps
T827 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2131023305 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:32 PM PDT 24 2427659101 ps
T828 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2967299190 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:23 PM PDT 24 406925715 ps
T829 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3011110647 Jun 23 06:16:24 PM PDT 24 Jun 23 06:16:26 PM PDT 24 339237991 ps
T830 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1047707373 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:26 PM PDT 24 573816876 ps
T106 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2572873729 Jun 23 06:16:11 PM PDT 24 Jun 23 06:16:13 PM PDT 24 526543667 ps
T831 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3746030748 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:23 PM PDT 24 354995983 ps
T832 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1454735545 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:21 PM PDT 24 492335189 ps
T833 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2939948496 Jun 23 06:16:10 PM PDT 24 Jun 23 06:16:12 PM PDT 24 361308355 ps
T834 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1052753894 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:07 PM PDT 24 430171998 ps
T346 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2045326640 Jun 23 06:16:11 PM PDT 24 Jun 23 06:16:19 PM PDT 24 9262181952 ps
T835 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1786134550 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:25 PM PDT 24 328116995 ps
T836 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1328962447 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:06 PM PDT 24 685199353 ps
T837 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2588634422 Jun 23 06:16:02 PM PDT 24 Jun 23 06:16:04 PM PDT 24 339084263 ps
T838 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2693051046 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:25 PM PDT 24 440835062 ps
T839 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3924506616 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:19 PM PDT 24 287505477 ps
T840 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2630789068 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:25 PM PDT 24 401884246 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.101041711 Jun 23 06:16:17 PM PDT 24 Jun 23 06:16:19 PM PDT 24 331437735 ps
T842 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.803469995 Jun 23 06:15:59 PM PDT 24 Jun 23 06:16:01 PM PDT 24 1287206309 ps
T843 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2015175812 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:23 PM PDT 24 502964414 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.30218028 Jun 23 06:15:58 PM PDT 24 Jun 23 06:15:59 PM PDT 24 315570869 ps
T107 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2259591193 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:22 PM PDT 24 431352843 ps
T845 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3688697940 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:27 PM PDT 24 611312169 ps
T108 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2452855193 Jun 23 06:16:07 PM PDT 24 Jun 23 06:16:11 PM PDT 24 1115501321 ps
T846 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.812015886 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:25 PM PDT 24 469282765 ps
T847 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3310469732 Jun 23 06:16:01 PM PDT 24 Jun 23 06:16:02 PM PDT 24 342410909 ps
T848 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.963247557 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:25 PM PDT 24 397036730 ps
T63 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1060510839 Jun 23 06:16:24 PM PDT 24 Jun 23 06:16:37 PM PDT 24 8213920353 ps
T109 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.324532684 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:07 PM PDT 24 1269520534 ps
T849 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.967660481 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:25 PM PDT 24 512330258 ps
T850 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2123857570 Jun 23 06:16:16 PM PDT 24 Jun 23 06:16:18 PM PDT 24 450240031 ps
T851 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2688828637 Jun 23 06:16:13 PM PDT 24 Jun 23 06:16:18 PM PDT 24 4280041645 ps
T852 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3239788514 Jun 23 06:16:17 PM PDT 24 Jun 23 06:16:19 PM PDT 24 646511632 ps
T853 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3041607164 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:21 PM PDT 24 632848891 ps
T64 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3067832469 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:26 PM PDT 24 10337319897 ps
T854 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2394374574 Jun 23 06:16:26 PM PDT 24 Jun 23 06:16:28 PM PDT 24 322556720 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.264448123 Jun 23 06:15:57 PM PDT 24 Jun 23 06:16:00 PM PDT 24 644516351 ps
T856 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2349971744 Jun 23 06:16:17 PM PDT 24 Jun 23 06:16:27 PM PDT 24 3870615423 ps
T857 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3451388254 Jun 23 06:16:17 PM PDT 24 Jun 23 06:16:19 PM PDT 24 412441154 ps
T858 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3140203114 Jun 23 06:16:02 PM PDT 24 Jun 23 06:16:25 PM PDT 24 5611602901 ps
T859 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1201409911 Jun 23 06:16:16 PM PDT 24 Jun 23 06:16:28 PM PDT 24 4486260580 ps
T860 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1632491891 Jun 23 06:16:00 PM PDT 24 Jun 23 06:16:01 PM PDT 24 411243756 ps
T861 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1997477386 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:21 PM PDT 24 444339510 ps
T862 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1547652386 Jun 23 06:16:13 PM PDT 24 Jun 23 06:16:20 PM PDT 24 3545962931 ps
T863 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2434083812 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:26 PM PDT 24 534370772 ps
T864 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2640160082 Jun 23 06:16:03 PM PDT 24 Jun 23 06:16:07 PM PDT 24 641429791 ps
T65 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1296275974 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:26 PM PDT 24 8662713562 ps
T865 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.875896677 Jun 23 06:16:07 PM PDT 24 Jun 23 06:16:11 PM PDT 24 1228476252 ps
T866 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4294660230 Jun 23 06:16:06 PM PDT 24 Jun 23 06:16:10 PM PDT 24 4725506490 ps
T867 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3845552829 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:24 PM PDT 24 2525981274 ps
T868 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2989852360 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:25 PM PDT 24 4493878298 ps
T869 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1216251919 Jun 23 06:16:28 PM PDT 24 Jun 23 06:16:30 PM PDT 24 375343227 ps
T870 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2952139695 Jun 23 06:16:02 PM PDT 24 Jun 23 06:16:15 PM PDT 24 4521509461 ps
T871 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2280815689 Jun 23 06:16:17 PM PDT 24 Jun 23 06:16:21 PM PDT 24 372332758 ps
T872 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2375936872 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:32 PM PDT 24 4357953665 ps
T873 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1982034177 Jun 23 06:16:13 PM PDT 24 Jun 23 06:16:15 PM PDT 24 568311289 ps
T874 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4113467268 Jun 23 06:16:10 PM PDT 24 Jun 23 06:16:13 PM PDT 24 625663888 ps
T875 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1122010194 Jun 23 06:16:26 PM PDT 24 Jun 23 06:16:27 PM PDT 24 395667391 ps
T876 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2628885791 Jun 23 06:16:30 PM PDT 24 Jun 23 06:16:31 PM PDT 24 293688317 ps
T877 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2325917023 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:31 PM PDT 24 2345490277 ps
T878 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3794118476 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:31 PM PDT 24 4317691708 ps
T879 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.322066046 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:25 PM PDT 24 291869423 ps
T880 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3780141613 Jun 23 06:16:27 PM PDT 24 Jun 23 06:16:28 PM PDT 24 448480031 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1797570247 Jun 23 06:16:12 PM PDT 24 Jun 23 06:16:14 PM PDT 24 491299693 ps
T882 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.597427093 Jun 23 06:16:23 PM PDT 24 Jun 23 06:16:26 PM PDT 24 2652237736 ps
T883 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1039691111 Jun 23 06:16:07 PM PDT 24 Jun 23 06:16:10 PM PDT 24 1347302199 ps
T884 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2817432923 Jun 23 06:16:02 PM PDT 24 Jun 23 06:16:05 PM PDT 24 661306988 ps
T885 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.773401208 Jun 23 06:16:27 PM PDT 24 Jun 23 06:16:29 PM PDT 24 381932271 ps
T886 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3901178793 Jun 23 06:16:33 PM PDT 24 Jun 23 06:16:34 PM PDT 24 463577612 ps
T887 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1531257288 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:07 PM PDT 24 448667748 ps
T888 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1690490937 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:27 PM PDT 24 8725260647 ps
T889 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2261394780 Jun 23 06:16:14 PM PDT 24 Jun 23 06:16:15 PM PDT 24 394125433 ps
T890 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2413508757 Jun 23 06:16:27 PM PDT 24 Jun 23 06:16:28 PM PDT 24 598809366 ps
T891 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.722204699 Jun 23 06:16:14 PM PDT 24 Jun 23 06:16:34 PM PDT 24 8269813444 ps
T892 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.493177214 Jun 23 06:16:33 PM PDT 24 Jun 23 06:16:35 PM PDT 24 440311845 ps
T893 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2146043077 Jun 23 06:16:26 PM PDT 24 Jun 23 06:16:28 PM PDT 24 396391432 ps
T894 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4044135110 Jun 23 06:16:05 PM PDT 24 Jun 23 06:16:08 PM PDT 24 487197619 ps
T895 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3843935318 Jun 23 06:16:29 PM PDT 24 Jun 23 06:16:30 PM PDT 24 496853431 ps
T896 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.487972077 Jun 23 06:16:16 PM PDT 24 Jun 23 06:16:20 PM PDT 24 4534168240 ps
T897 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2454926342 Jun 23 06:16:12 PM PDT 24 Jun 23 06:16:15 PM PDT 24 436482969 ps
T898 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3451922196 Jun 23 06:16:13 PM PDT 24 Jun 23 06:16:19 PM PDT 24 4241207223 ps
T899 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3951054773 Jun 23 06:16:28 PM PDT 24 Jun 23 06:16:30 PM PDT 24 478241653 ps
T900 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1780832888 Jun 23 06:16:31 PM PDT 24 Jun 23 06:16:32 PM PDT 24 534030140 ps
T110 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.4137368474 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:24 PM PDT 24 447606416 ps
T901 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3678643827 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:24 PM PDT 24 403323799 ps
T902 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.524865871 Jun 23 06:16:15 PM PDT 24 Jun 23 06:16:17 PM PDT 24 599459327 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3702262220 Jun 23 06:16:00 PM PDT 24 Jun 23 06:16:47 PM PDT 24 51521954952 ps
T112 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3232086794 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:21 PM PDT 24 377537439 ps
T903 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.654290810 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:22 PM PDT 24 361099012 ps
T904 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.676860622 Jun 23 06:16:08 PM PDT 24 Jun 23 06:16:10 PM PDT 24 320861393 ps
T905 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.935916594 Jun 23 06:16:22 PM PDT 24 Jun 23 06:16:34 PM PDT 24 2880346550 ps
T906 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.327018206 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:25 PM PDT 24 563331591 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.866916206 Jun 23 06:16:19 PM PDT 24 Jun 23 06:16:20 PM PDT 24 523528113 ps
T115 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3531955739 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:22 PM PDT 24 530980418 ps
T908 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1567839535 Jun 23 06:16:06 PM PDT 24 Jun 23 06:16:09 PM PDT 24 801711337 ps
T113 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.472357718 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:20 PM PDT 24 404416338 ps
T909 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2843901769 Jun 23 06:16:24 PM PDT 24 Jun 23 06:16:26 PM PDT 24 480183669 ps
T910 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2006060839 Jun 23 06:16:10 PM PDT 24 Jun 23 06:16:12 PM PDT 24 480352987 ps
T114 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3669741937 Jun 23 06:16:08 PM PDT 24 Jun 23 06:16:11 PM PDT 24 604527420 ps
T911 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1535739510 Jun 23 06:16:18 PM PDT 24 Jun 23 06:16:21 PM PDT 24 771142842 ps
T912 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4217926559 Jun 23 06:16:10 PM PDT 24 Jun 23 06:16:11 PM PDT 24 497599015 ps
T913 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3584788850 Jun 23 06:16:06 PM PDT 24 Jun 23 06:16:08 PM PDT 24 587767272 ps
T914 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3294541217 Jun 23 06:16:21 PM PDT 24 Jun 23 06:16:23 PM PDT 24 514218768 ps
T915 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1781529802 Jun 23 06:16:25 PM PDT 24 Jun 23 06:16:29 PM PDT 24 4498248415 ps
T916 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2652614247 Jun 23 06:16:00 PM PDT 24 Jun 23 06:18:00 PM PDT 24 38694486250 ps
T917 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3606786978 Jun 23 06:16:16 PM PDT 24 Jun 23 06:16:23 PM PDT 24 4718962870 ps
T918 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1420699540 Jun 23 06:16:20 PM PDT 24 Jun 23 06:16:22 PM PDT 24 412840134 ps

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3962307370
Short name T9
Test name
Test status
Simulation time 615199147457 ps
CPU time 449.57 seconds
Started Jun 23 05:57:11 PM PDT 24
Finished Jun 23 06:04:41 PM PDT 24
Peak memory 210948 kb
Host smart-8cadde03-04a4-4d78-a6c4-8ee8b8760ab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962307370 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3962307370
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1070722294
Short name T40
Test name
Test status
Simulation time 597134966620 ps
CPU time 1368.42 seconds
Started Jun 23 05:55:55 PM PDT 24
Finished Jun 23 06:18:44 PM PDT 24
Peak memory 210784 kb
Host smart-4e347915-5ab3-4f8c-bc2c-0d28b0f57a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070722294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1070722294
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1995096969
Short name T8
Test name
Test status
Simulation time 1723616627137 ps
CPU time 258.54 seconds
Started Jun 23 05:55:07 PM PDT 24
Finished Jun 23 05:59:26 PM PDT 24
Peak memory 210880 kb
Host smart-15239449-d13a-4253-93d7-e51a61834611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995096969 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1995096969
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.4248148182
Short name T212
Test name
Test status
Simulation time 294702488163 ps
CPU time 233.85 seconds
Started Jun 23 05:56:17 PM PDT 24
Finished Jun 23 06:00:11 PM PDT 24
Peak memory 213060 kb
Host smart-44d220f7-c141-444c-9dde-81b640e4c758
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248148182 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.4248148182
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1350829020
Short name T76
Test name
Test status
Simulation time 488702697640 ps
CPU time 1100.01 seconds
Started Jun 23 05:57:12 PM PDT 24
Finished Jun 23 06:15:33 PM PDT 24
Peak memory 202148 kb
Host smart-d4a21aea-c57b-4cb7-8ee8-7737a91b4699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350829020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1350829020
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4287953022
Short name T146
Test name
Test status
Simulation time 501070469042 ps
CPU time 295.85 seconds
Started Jun 23 05:56:24 PM PDT 24
Finished Jun 23 06:01:21 PM PDT 24
Peak memory 202256 kb
Host smart-9fb8aa0d-6805-43e7-b4d0-a82bd4c324a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287953022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4287953022
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.433308610
Short name T89
Test name
Test status
Simulation time 503965891231 ps
CPU time 761.12 seconds
Started Jun 23 05:56:20 PM PDT 24
Finished Jun 23 06:09:01 PM PDT 24
Peak memory 202260 kb
Host smart-a03c3c7c-4a7e-4ad1-aa44-65794812f42f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433308610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.433308610
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3621122387
Short name T130
Test name
Test status
Simulation time 534977905242 ps
CPU time 1252.73 seconds
Started Jun 23 05:55:10 PM PDT 24
Finished Jun 23 06:16:03 PM PDT 24
Peak memory 202320 kb
Host smart-2775d1e4-656d-4db1-b35f-6bf3241a573d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621122387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3621122387
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1788927578
Short name T16
Test name
Test status
Simulation time 427730510194 ps
CPU time 332.03 seconds
Started Jun 23 05:58:08 PM PDT 24
Finished Jun 23 06:03:40 PM PDT 24
Peak memory 210928 kb
Host smart-21a9be1c-2c9e-4a13-bc17-d66314fab62e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788927578 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1788927578
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2913463570
Short name T48
Test name
Test status
Simulation time 8610886283 ps
CPU time 12.5 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:31 PM PDT 24
Peak memory 201456 kb
Host smart-fb5eedd9-7004-4297-bcc1-e532d35e2d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913463570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2913463570
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2815349899
Short name T135
Test name
Test status
Simulation time 518024921370 ps
CPU time 605.14 seconds
Started Jun 23 05:59:54 PM PDT 24
Finished Jun 23 06:10:00 PM PDT 24
Peak memory 202284 kb
Host smart-4e7e33f7-ff9e-4483-8ddd-7556f588b9c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815349899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2815349899
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1253009098
Short name T152
Test name
Test status
Simulation time 494882230087 ps
CPU time 69.58 seconds
Started Jun 23 05:56:46 PM PDT 24
Finished Jun 23 05:57:56 PM PDT 24
Peak memory 202316 kb
Host smart-065c337f-b93e-46d9-8aaf-e0f42e599838
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253009098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1253009098
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2909056767
Short name T3
Test name
Test status
Simulation time 328953083804 ps
CPU time 212.61 seconds
Started Jun 23 05:59:54 PM PDT 24
Finished Jun 23 06:03:27 PM PDT 24
Peak memory 202260 kb
Host smart-d563f67d-a516-4f5e-a24c-bde69ccb2b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909056767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2909056767
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1592820039
Short name T136
Test name
Test status
Simulation time 495158063680 ps
CPU time 558.64 seconds
Started Jun 23 05:56:23 PM PDT 24
Finished Jun 23 06:05:42 PM PDT 24
Peak memory 202208 kb
Host smart-053192fe-6a42-43c0-b854-29630f0e155d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592820039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1592820039
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3613283696
Short name T51
Test name
Test status
Simulation time 4009823041 ps
CPU time 5.9 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 05:55:09 PM PDT 24
Peak memory 217776 kb
Host smart-79fbf39b-9169-403f-8c67-fdc2a0f674c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613283696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3613283696
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.323239373
Short name T25
Test name
Test status
Simulation time 1185189966344 ps
CPU time 930.32 seconds
Started Jun 23 05:58:59 PM PDT 24
Finished Jun 23 06:14:29 PM PDT 24
Peak memory 210908 kb
Host smart-105b270d-b321-45df-bc75-d0004b9dfc1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323239373 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.323239373
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2479967499
Short name T45
Test name
Test status
Simulation time 553603070 ps
CPU time 1.16 seconds
Started Jun 23 06:16:02 PM PDT 24
Finished Jun 23 06:16:04 PM PDT 24
Peak memory 201152 kb
Host smart-fe5d455e-949c-4d71-94aa-720ff422e19c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479967499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2479967499
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.682709251
Short name T34
Test name
Test status
Simulation time 164500223946 ps
CPU time 186.93 seconds
Started Jun 23 05:56:47 PM PDT 24
Finished Jun 23 05:59:54 PM PDT 24
Peak memory 202248 kb
Host smart-f611fa26-3a10-4cc7-878a-2cc4b0ae6d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682709251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.682709251
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1891132715
Short name T126
Test name
Test status
Simulation time 330634825805 ps
CPU time 790.22 seconds
Started Jun 23 05:55:44 PM PDT 24
Finished Jun 23 06:08:55 PM PDT 24
Peak memory 202304 kb
Host smart-898834fb-8e92-4a37-947f-dedd465582e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891132715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1891132715
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2696150061
Short name T57
Test name
Test status
Simulation time 810504160 ps
CPU time 2.62 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201432 kb
Host smart-0affb847-5962-459e-b78f-54c15367d4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696150061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2696150061
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.565800320
Short name T125
Test name
Test status
Simulation time 529624091554 ps
CPU time 540.42 seconds
Started Jun 23 05:57:00 PM PDT 24
Finished Jun 23 06:06:00 PM PDT 24
Peak memory 202256 kb
Host smart-ab7fb782-54c1-450c-ae6e-7ac9d818a7db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565800320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.565800320
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3386456534
Short name T33
Test name
Test status
Simulation time 351911335011 ps
CPU time 66.55 seconds
Started Jun 23 05:59:32 PM PDT 24
Finished Jun 23 06:00:39 PM PDT 24
Peak memory 202188 kb
Host smart-a302d1fb-a083-459f-805f-e3daadc63f56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386456534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3386456534
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.491470756
Short name T216
Test name
Test status
Simulation time 532016155687 ps
CPU time 330.34 seconds
Started Jun 23 05:55:02 PM PDT 24
Finished Jun 23 06:00:33 PM PDT 24
Peak memory 202220 kb
Host smart-41f5d868-be01-4834-b62e-4c11e7d3225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491470756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.491470756
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3896988492
Short name T285
Test name
Test status
Simulation time 355529788230 ps
CPU time 265.72 seconds
Started Jun 23 05:56:07 PM PDT 24
Finished Jun 23 06:00:33 PM PDT 24
Peak memory 202164 kb
Host smart-3406f230-2eb0-4bd7-a1f5-81193d2f2d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896988492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3896988492
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2132946423
Short name T231
Test name
Test status
Simulation time 384031869108 ps
CPU time 439 seconds
Started Jun 23 05:57:28 PM PDT 24
Finished Jun 23 06:04:47 PM PDT 24
Peak memory 202296 kb
Host smart-83f65c00-854c-46e6-bbf4-54fce25d21f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132946423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2132946423
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2829849514
Short name T73
Test name
Test status
Simulation time 487269014473 ps
CPU time 315.03 seconds
Started Jun 23 05:55:01 PM PDT 24
Finished Jun 23 06:00:16 PM PDT 24
Peak memory 202292 kb
Host smart-c3d9f001-151a-4c9f-8cb7-def8e480ba51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829849514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2829849514
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1704759287
Short name T246
Test name
Test status
Simulation time 591540311739 ps
CPU time 364.2 seconds
Started Jun 23 05:55:25 PM PDT 24
Finished Jun 23 06:01:30 PM PDT 24
Peak memory 202252 kb
Host smart-61c01f25-91de-424d-af76-f6a62bbb5e2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704759287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1704759287
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.193981289
Short name T240
Test name
Test status
Simulation time 346268064105 ps
CPU time 561.86 seconds
Started Jun 23 05:55:13 PM PDT 24
Finished Jun 23 06:04:35 PM PDT 24
Peak memory 202244 kb
Host smart-52a14347-e1b6-476c-9abf-ff7a4ec172d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193981289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.193981289
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.266215176
Short name T372
Test name
Test status
Simulation time 474616738 ps
CPU time 1.37 seconds
Started Jun 23 05:55:49 PM PDT 24
Finished Jun 23 05:55:51 PM PDT 24
Peak memory 201900 kb
Host smart-1f6d71f2-fa35-458a-818b-fb7f1af2aa18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266215176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.266215176
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.881997655
Short name T14
Test name
Test status
Simulation time 166475012052 ps
CPU time 150.27 seconds
Started Jun 23 05:58:46 PM PDT 24
Finished Jun 23 06:01:17 PM PDT 24
Peak memory 210956 kb
Host smart-ec00e256-d7b7-475b-adc7-20817c2b2b83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881997655 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.881997655
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4075298644
Short name T173
Test name
Test status
Simulation time 523189267155 ps
CPU time 131.97 seconds
Started Jun 23 05:56:34 PM PDT 24
Finished Jun 23 05:58:46 PM PDT 24
Peak memory 202220 kb
Host smart-93354a28-518e-4658-a6f3-fc46e35a7205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075298644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4075298644
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.621782096
Short name T289
Test name
Test status
Simulation time 380977706931 ps
CPU time 110.39 seconds
Started Jun 23 05:56:06 PM PDT 24
Finished Jun 23 05:57:57 PM PDT 24
Peak memory 202204 kb
Host smart-582f77ac-7164-44a5-93be-7ab53041bb3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621782096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.621782096
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3095865880
Short name T148
Test name
Test status
Simulation time 520892963698 ps
CPU time 769.69 seconds
Started Jun 23 05:57:55 PM PDT 24
Finished Jun 23 06:10:45 PM PDT 24
Peak memory 202196 kb
Host smart-6070a9f1-1f5a-48a3-87c4-07d7a69e9050
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095865880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3095865880
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.262861708
Short name T197
Test name
Test status
Simulation time 162587873734 ps
CPU time 197.46 seconds
Started Jun 23 05:58:29 PM PDT 24
Finished Jun 23 06:01:47 PM PDT 24
Peak memory 202340 kb
Host smart-075726c5-1bb6-43fc-b3f4-2c501d8ad631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262861708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.262861708
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1282745289
Short name T5
Test name
Test status
Simulation time 375745796074 ps
CPU time 887.41 seconds
Started Jun 23 05:59:19 PM PDT 24
Finished Jun 23 06:14:07 PM PDT 24
Peak memory 202176 kb
Host smart-602314ae-2e00-4077-95e0-46d8bd086b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282745289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1282745289
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1901045445
Short name T24
Test name
Test status
Simulation time 203860053367 ps
CPU time 275.07 seconds
Started Jun 23 05:55:53 PM PDT 24
Finished Jun 23 06:00:29 PM PDT 24
Peak memory 210880 kb
Host smart-cc84ce20-3f68-4149-8632-2dea1abcab53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901045445 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1901045445
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3836874257
Short name T222
Test name
Test status
Simulation time 326872523518 ps
CPU time 676.19 seconds
Started Jun 23 05:56:10 PM PDT 24
Finished Jun 23 06:07:27 PM PDT 24
Peak memory 202244 kb
Host smart-b00633e1-8a05-43af-b688-048dca37419b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836874257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3836874257
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1306523912
Short name T199
Test name
Test status
Simulation time 220466836132 ps
CPU time 36.64 seconds
Started Jun 23 05:56:45 PM PDT 24
Finished Jun 23 05:57:22 PM PDT 24
Peak memory 202248 kb
Host smart-c4f70041-98be-4b4b-8f6e-b023aa8a29a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306523912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1306523912
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1594763322
Short name T56
Test name
Test status
Simulation time 547538056 ps
CPU time 2.9 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:24 PM PDT 24
Peak memory 201352 kb
Host smart-453b7cc5-16b5-4932-ae9b-11cf9c07d579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594763322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1594763322
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3563186066
Short name T330
Test name
Test status
Simulation time 412465932588 ps
CPU time 475.73 seconds
Started Jun 23 05:56:56 PM PDT 24
Finished Jun 23 06:04:52 PM PDT 24
Peak memory 202196 kb
Host smart-8674c6d9-1271-4b23-ba22-487f445a778f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563186066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3563186066
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3328630069
Short name T234
Test name
Test status
Simulation time 525444285760 ps
CPU time 577.69 seconds
Started Jun 23 05:55:50 PM PDT 24
Finished Jun 23 06:05:28 PM PDT 24
Peak memory 202324 kb
Host smart-91a90e8f-966c-4623-a635-dfc13908db38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328630069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3328630069
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1943970322
Short name T238
Test name
Test status
Simulation time 420720873753 ps
CPU time 410.1 seconds
Started Jun 23 05:56:31 PM PDT 24
Finished Jun 23 06:03:22 PM PDT 24
Peak memory 202632 kb
Host smart-b5251446-d9c9-407f-ae49-0632a83a5f51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943970322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1943970322
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1582268173
Short name T261
Test name
Test status
Simulation time 506656112722 ps
CPU time 1036.9 seconds
Started Jun 23 05:55:23 PM PDT 24
Finished Jun 23 06:12:40 PM PDT 24
Peak memory 202236 kb
Host smart-573788cb-af36-4c4c-8633-241d02e4712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582268173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1582268173
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1749008290
Short name T294
Test name
Test status
Simulation time 490012932508 ps
CPU time 311.03 seconds
Started Jun 23 05:55:30 PM PDT 24
Finished Jun 23 06:00:41 PM PDT 24
Peak memory 202264 kb
Host smart-8d118c0a-cd5f-4270-9611-4f16f83aaf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749008290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1749008290
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1294006867
Short name T327
Test name
Test status
Simulation time 1177500358454 ps
CPU time 1033.91 seconds
Started Jun 23 05:54:56 PM PDT 24
Finished Jun 23 06:12:11 PM PDT 24
Peak memory 202624 kb
Host smart-a02a32b5-164e-4e0a-8df5-ee7d2f88bab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294006867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1294006867
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1761342789
Short name T263
Test name
Test status
Simulation time 339788585878 ps
CPU time 673.62 seconds
Started Jun 23 05:56:19 PM PDT 24
Finished Jun 23 06:07:33 PM PDT 24
Peak memory 202332 kb
Host smart-54399c6d-4bde-485a-a140-dcb438b7d026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761342789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1761342789
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1148522404
Short name T26
Test name
Test status
Simulation time 649394355501 ps
CPU time 121.14 seconds
Started Jun 23 05:57:49 PM PDT 24
Finished Jun 23 05:59:51 PM PDT 24
Peak memory 202240 kb
Host smart-159be3c8-fced-4cf3-873e-02c557208277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148522404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1148522404
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1472592160
Short name T225
Test name
Test status
Simulation time 336403456459 ps
CPU time 405.82 seconds
Started Jun 23 05:58:41 PM PDT 24
Finished Jun 23 06:05:27 PM PDT 24
Peak memory 202328 kb
Host smart-7212473f-5024-491a-a69a-3b6e3b811762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472592160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1472592160
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1289062713
Short name T82
Test name
Test status
Simulation time 332721687455 ps
CPU time 757.01 seconds
Started Jun 23 05:55:32 PM PDT 24
Finished Jun 23 06:08:09 PM PDT 24
Peak memory 202244 kb
Host smart-96f98c2e-2577-42dd-8cec-59293a9ecdf4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289062713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1289062713
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1168746433
Short name T314
Test name
Test status
Simulation time 365147280004 ps
CPU time 880.51 seconds
Started Jun 23 05:56:34 PM PDT 24
Finished Jun 23 06:11:16 PM PDT 24
Peak memory 202296 kb
Host smart-0ca59013-9aeb-40ff-a734-009ac98600c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168746433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1168746433
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3333295509
Short name T80
Test name
Test status
Simulation time 357126796727 ps
CPU time 733.41 seconds
Started Jun 23 05:56:49 PM PDT 24
Finished Jun 23 06:09:03 PM PDT 24
Peak memory 202336 kb
Host smart-b38b3f92-04d3-4971-a9f3-5f858629bd72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333295509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3333295509
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.868106190
Short name T219
Test name
Test status
Simulation time 327553538258 ps
CPU time 292.97 seconds
Started Jun 23 05:58:12 PM PDT 24
Finished Jun 23 06:03:06 PM PDT 24
Peak memory 202292 kb
Host smart-97a582a4-7d58-4971-9667-fa431cb9a9c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868106190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.868106190
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3560018921
Short name T265
Test name
Test status
Simulation time 336722047746 ps
CPU time 119.48 seconds
Started Jun 23 05:59:41 PM PDT 24
Finished Jun 23 06:01:41 PM PDT 24
Peak memory 202244 kb
Host smart-82803a23-a57d-4aca-ad16-25630d9a2393
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560018921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3560018921
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.55797898
Short name T84
Test name
Test status
Simulation time 200845514681 ps
CPU time 98.79 seconds
Started Jun 23 05:54:59 PM PDT 24
Finished Jun 23 05:56:38 PM PDT 24
Peak memory 202352 kb
Host smart-648234d5-eb8c-49dc-b42f-73bc5045fb77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55797898 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.55797898
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1963354109
Short name T335
Test name
Test status
Simulation time 367518927231 ps
CPU time 820.95 seconds
Started Jun 23 05:55:48 PM PDT 24
Finished Jun 23 06:09:30 PM PDT 24
Peak memory 202256 kb
Host smart-91b3a64f-de4c-46cb-b1f1-69a8493ae9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963354109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1963354109
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3517556396
Short name T228
Test name
Test status
Simulation time 419398232998 ps
CPU time 1010.78 seconds
Started Jun 23 05:56:19 PM PDT 24
Finished Jun 23 06:13:10 PM PDT 24
Peak memory 202280 kb
Host smart-e933695e-d4ba-48b3-8272-8a8c3863b74b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517556396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3517556396
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.166943186
Short name T308
Test name
Test status
Simulation time 164831911309 ps
CPU time 44.5 seconds
Started Jun 23 05:55:02 PM PDT 24
Finished Jun 23 05:55:47 PM PDT 24
Peak memory 202272 kb
Host smart-845d84a5-1084-4802-8ade-25b8165ea6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166943186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.166943186
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.4146288830
Short name T310
Test name
Test status
Simulation time 337493502581 ps
CPU time 759.41 seconds
Started Jun 23 05:58:27 PM PDT 24
Finished Jun 23 06:11:07 PM PDT 24
Peak memory 202404 kb
Host smart-5f723112-aa99-45ad-b9d3-52af40aae492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146288830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.4146288830
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2279461631
Short name T194
Test name
Test status
Simulation time 118421767791 ps
CPU time 424.85 seconds
Started Jun 23 05:58:53 PM PDT 24
Finished Jun 23 06:05:58 PM PDT 24
Peak memory 202636 kb
Host smart-ac89ab28-1ac3-42c8-a172-95efe1c92a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279461631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2279461631
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1628172275
Short name T1
Test name
Test status
Simulation time 367147067042 ps
CPU time 104.92 seconds
Started Jun 23 05:55:13 PM PDT 24
Finished Jun 23 05:56:58 PM PDT 24
Peak memory 202236 kb
Host smart-ea44412f-26bf-401b-9d41-14d95b24fb7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628172275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1628172275
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2765009591
Short name T304
Test name
Test status
Simulation time 523915958654 ps
CPU time 340.72 seconds
Started Jun 23 05:55:24 PM PDT 24
Finished Jun 23 06:01:05 PM PDT 24
Peak memory 202224 kb
Host smart-a407a655-2b5c-4b6b-9bdb-17a66596c571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765009591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2765009591
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1060510839
Short name T63
Test name
Test status
Simulation time 8213920353 ps
CPU time 11.88 seconds
Started Jun 23 06:16:24 PM PDT 24
Finished Jun 23 06:16:37 PM PDT 24
Peak memory 201408 kb
Host smart-c2dccfdc-d021-4646-838a-de70ad7bcd8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060510839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1060510839
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1203271924
Short name T43
Test name
Test status
Simulation time 2404458793 ps
CPU time 2.2 seconds
Started Jun 23 06:15:59 PM PDT 24
Finished Jun 23 06:16:02 PM PDT 24
Peak memory 201228 kb
Host smart-093f0dec-eee4-4e97-8a10-1d576b60a60a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203271924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1203271924
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.316334812
Short name T190
Test name
Test status
Simulation time 384033985327 ps
CPU time 186.84 seconds
Started Jun 23 05:55:39 PM PDT 24
Finished Jun 23 05:58:47 PM PDT 24
Peak memory 210788 kb
Host smart-0841f655-6a0d-4dc4-97eb-0f58633aa0fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316334812 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.316334812
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3875747913
Short name T233
Test name
Test status
Simulation time 323884453822 ps
CPU time 179.63 seconds
Started Jun 23 05:55:45 PM PDT 24
Finished Jun 23 05:58:45 PM PDT 24
Peak memory 202324 kb
Host smart-e92b5bf0-bd5e-486c-a895-9a1559a30f6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875747913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3875747913
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3435032554
Short name T328
Test name
Test status
Simulation time 167478754118 ps
CPU time 393.8 seconds
Started Jun 23 05:55:43 PM PDT 24
Finished Jun 23 06:02:17 PM PDT 24
Peak memory 202256 kb
Host smart-0ac8b7c2-fe2d-4ec6-ba5f-3bb89fd96e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435032554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3435032554
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2639011518
Short name T397
Test name
Test status
Simulation time 415324683332 ps
CPU time 487.43 seconds
Started Jun 23 05:55:41 PM PDT 24
Finished Jun 23 06:03:49 PM PDT 24
Peak memory 202304 kb
Host smart-2084dbe5-310b-4a2d-b12e-f97ff433f0a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639011518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2639011518
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.183309765
Short name T313
Test name
Test status
Simulation time 327524332428 ps
CPU time 668.66 seconds
Started Jun 23 05:55:05 PM PDT 24
Finished Jun 23 06:06:14 PM PDT 24
Peak memory 202272 kb
Host smart-bca3446d-267a-4d85-975d-79c1136e8be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183309765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.183309765
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.918291048
Short name T336
Test name
Test status
Simulation time 169930991890 ps
CPU time 401.49 seconds
Started Jun 23 05:56:15 PM PDT 24
Finished Jun 23 06:02:57 PM PDT 24
Peak memory 202260 kb
Host smart-e1684cf8-645b-448f-9f37-f2f52428b850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918291048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.918291048
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3381251320
Short name T326
Test name
Test status
Simulation time 624319994157 ps
CPU time 315.09 seconds
Started Jun 23 05:55:07 PM PDT 24
Finished Jun 23 06:00:22 PM PDT 24
Peak memory 202332 kb
Host smart-24b47961-4029-436d-9c48-47950e9afa10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381251320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3381251320
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2761501738
Short name T248
Test name
Test status
Simulation time 160349037099 ps
CPU time 348.08 seconds
Started Jun 23 05:58:22 PM PDT 24
Finished Jun 23 06:04:10 PM PDT 24
Peak memory 202200 kb
Host smart-0dbf2ba2-6ae1-4052-9869-f16ee87073c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761501738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2761501738
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.386774302
Short name T147
Test name
Test status
Simulation time 352259048720 ps
CPU time 176.93 seconds
Started Jun 23 05:58:25 PM PDT 24
Finished Jun 23 06:01:23 PM PDT 24
Peak memory 202300 kb
Host smart-ada28ea3-2d7e-49a7-8e5d-25e259c6d6bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386774302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.386774302
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1760691945
Short name T131
Test name
Test status
Simulation time 502022486239 ps
CPU time 279.71 seconds
Started Jun 23 05:59:01 PM PDT 24
Finished Jun 23 06:03:41 PM PDT 24
Peak memory 202236 kb
Host smart-0cc8257a-fe16-4700-adc4-06521597d1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760691945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1760691945
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1293767253
Short name T138
Test name
Test status
Simulation time 171280232960 ps
CPU time 98.68 seconds
Started Jun 23 05:55:15 PM PDT 24
Finished Jun 23 05:56:54 PM PDT 24
Peak memory 202264 kb
Host smart-9ffefaab-7665-45ed-a7f9-4b7594180e7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293767253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1293767253
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1441318078
Short name T266
Test name
Test status
Simulation time 559850871427 ps
CPU time 324.8 seconds
Started Jun 23 05:56:02 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 202260 kb
Host smart-65b9fa18-2d9c-4cd3-a996-e5ea6a9494d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441318078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1441318078
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1989535243
Short name T352
Test name
Test status
Simulation time 97891470305 ps
CPU time 369.26 seconds
Started Jun 23 05:56:06 PM PDT 24
Finished Jun 23 06:02:15 PM PDT 24
Peak memory 202508 kb
Host smart-2b38f486-538f-44ed-8dc7-8dfb433785bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989535243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1989535243
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3787806817
Short name T302
Test name
Test status
Simulation time 165764728027 ps
CPU time 352.84 seconds
Started Jun 23 05:56:10 PM PDT 24
Finished Jun 23 06:02:03 PM PDT 24
Peak memory 202304 kb
Host smart-9ac2b368-2368-4fe0-8a89-9f04f78a909e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787806817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3787806817
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3236920682
Short name T77
Test name
Test status
Simulation time 798594918953 ps
CPU time 204.23 seconds
Started Jun 23 05:59:59 PM PDT 24
Finished Jun 23 06:03:23 PM PDT 24
Peak memory 213116 kb
Host smart-9c51e79f-64cf-470a-a3cf-2fdb43caa391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236920682 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3236920682
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3396878232
Short name T236
Test name
Test status
Simulation time 488471192854 ps
CPU time 1055.24 seconds
Started Jun 23 05:54:53 PM PDT 24
Finished Jun 23 06:12:29 PM PDT 24
Peak memory 202348 kb
Host smart-009bbbec-af99-4f55-aa8a-46af4cab5527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396878232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3396878232
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1861689415
Short name T88
Test name
Test status
Simulation time 352911855394 ps
CPU time 776.99 seconds
Started Jun 23 05:55:31 PM PDT 24
Finished Jun 23 06:08:28 PM PDT 24
Peak memory 202248 kb
Host smart-15591d85-2f18-4804-bb63-5a4618e9697b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861689415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1861689415
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3149020171
Short name T213
Test name
Test status
Simulation time 515102727533 ps
CPU time 248.25 seconds
Started Jun 23 05:55:46 PM PDT 24
Finished Jun 23 05:59:55 PM PDT 24
Peak memory 202256 kb
Host smart-73933a3c-7048-4635-bafa-72d1b3a9500e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149020171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3149020171
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.347675706
Short name T186
Test name
Test status
Simulation time 84341841588 ps
CPU time 365.07 seconds
Started Jun 23 05:55:49 PM PDT 24
Finished Jun 23 06:01:55 PM PDT 24
Peak memory 202564 kb
Host smart-c3a99f19-dd47-4eaa-9fec-39cbbddcb37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347675706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.347675706
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3019642261
Short name T351
Test name
Test status
Simulation time 76941000643 ps
CPU time 347.07 seconds
Started Jun 23 05:56:02 PM PDT 24
Finished Jun 23 06:01:50 PM PDT 24
Peak memory 202572 kb
Host smart-3e6d8c87-a503-4791-ad87-b962ba43cd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019642261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3019642261
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2457999211
Short name T339
Test name
Test status
Simulation time 164778098808 ps
CPU time 85.21 seconds
Started Jun 23 05:56:09 PM PDT 24
Finished Jun 23 05:57:34 PM PDT 24
Peak memory 202292 kb
Host smart-0cb2a3d8-6f71-4720-96b4-b7f2ab0b8178
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457999211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2457999211
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2629515747
Short name T315
Test name
Test status
Simulation time 236865280277 ps
CPU time 760.62 seconds
Started Jun 23 05:56:17 PM PDT 24
Finished Jun 23 06:08:58 PM PDT 24
Peak memory 210764 kb
Host smart-750de791-b5a8-4daa-845b-bcd0aa798231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629515747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2629515747
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.932099523
Short name T274
Test name
Test status
Simulation time 332873256228 ps
CPU time 387.47 seconds
Started Jun 23 05:57:29 PM PDT 24
Finished Jun 23 06:03:57 PM PDT 24
Peak memory 202284 kb
Host smart-2c952d84-4a3f-496d-b25f-77e8bed8aac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932099523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.932099523
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1968944608
Short name T309
Test name
Test status
Simulation time 334736832150 ps
CPU time 744.65 seconds
Started Jun 23 05:57:46 PM PDT 24
Finished Jun 23 06:10:11 PM PDT 24
Peak memory 202236 kb
Host smart-3adcc34d-4956-4293-b171-b095b7ab8549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968944608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1968944608
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.673023618
Short name T251
Test name
Test status
Simulation time 327931098458 ps
CPU time 764.68 seconds
Started Jun 23 05:58:13 PM PDT 24
Finished Jun 23 06:10:58 PM PDT 24
Peak memory 202304 kb
Host smart-00b1be2e-668d-42e7-a12d-c712486a6cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673023618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.673023618
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1569042213
Short name T331
Test name
Test status
Simulation time 503226648005 ps
CPU time 560.53 seconds
Started Jun 23 05:59:26 PM PDT 24
Finished Jun 23 06:08:47 PM PDT 24
Peak memory 202260 kb
Host smart-81b54392-4e10-4fd2-b1c7-862d1715fdef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569042213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1569042213
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3689888306
Short name T237
Test name
Test status
Simulation time 493767027771 ps
CPU time 1222.18 seconds
Started Jun 23 05:59:43 PM PDT 24
Finished Jun 23 06:20:06 PM PDT 24
Peak memory 202260 kb
Host smart-6217f9f3-ca1a-4cc5-a803-9e888d25e827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689888306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3689888306
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.281294912
Short name T224
Test name
Test status
Simulation time 525184346835 ps
CPU time 1098.78 seconds
Started Jun 23 05:55:11 PM PDT 24
Finished Jun 23 06:13:30 PM PDT 24
Peak memory 202244 kb
Host smart-00204e2f-c40e-41d8-8eb0-2b2347cd3eb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281294912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.281294912
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2126252538
Short name T311
Test name
Test status
Simulation time 324190614073 ps
CPU time 365.72 seconds
Started Jun 23 05:55:21 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 202244 kb
Host smart-2eeb68e9-6f26-428c-80a6-285a41fb35e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126252538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2126252538
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.411356580
Short name T293
Test name
Test status
Simulation time 489267973970 ps
CPU time 1138.88 seconds
Started Jun 23 05:55:20 PM PDT 24
Finished Jun 23 06:14:19 PM PDT 24
Peak memory 202204 kb
Host smart-b6bfd654-e4e8-4452-bc97-f84aa580d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411356580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.411356580
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3669741937
Short name T114
Test name
Test status
Simulation time 604527420 ps
CPU time 1.9 seconds
Started Jun 23 06:16:08 PM PDT 24
Finished Jun 23 06:16:11 PM PDT 24
Peak memory 201344 kb
Host smart-615ab7ee-b841-4c0f-9b3d-9c93df3420b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669741937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3669741937
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3702262220
Short name T111
Test name
Test status
Simulation time 51521954952 ps
CPU time 46.5 seconds
Started Jun 23 06:16:00 PM PDT 24
Finished Jun 23 06:16:47 PM PDT 24
Peak memory 201440 kb
Host smart-7a5da7d2-641f-4707-9df7-1fb0fa48231b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702262220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3702262220
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1039691111
Short name T883
Test name
Test status
Simulation time 1347302199 ps
CPU time 2.32 seconds
Started Jun 23 06:16:07 PM PDT 24
Finished Jun 23 06:16:10 PM PDT 24
Peak memory 201160 kb
Host smart-9fe703ea-3e5d-4c78-b571-37314538c74c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039691111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1039691111
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3584788850
Short name T913
Test name
Test status
Simulation time 587767272 ps
CPU time 1.28 seconds
Started Jun 23 06:16:06 PM PDT 24
Finished Jun 23 06:16:08 PM PDT 24
Peak memory 201228 kb
Host smart-ee262cd9-227f-4511-9566-f782e0374d11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584788850 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3584788850
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.592162832
Short name T117
Test name
Test status
Simulation time 416520504 ps
CPU time 1.65 seconds
Started Jun 23 06:16:01 PM PDT 24
Finished Jun 23 06:16:03 PM PDT 24
Peak memory 201180 kb
Host smart-d12a70fe-8b06-4f0e-b229-2c6ce473ce80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592162832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.592162832
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.30218028
Short name T844
Test name
Test status
Simulation time 315570869 ps
CPU time 0.8 seconds
Started Jun 23 06:15:58 PM PDT 24
Finished Jun 23 06:15:59 PM PDT 24
Peak memory 201176 kb
Host smart-aad94cf4-f9b9-4630-8b15-105148fd3126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30218028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.30218028
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3140203114
Short name T858
Test name
Test status
Simulation time 5611602901 ps
CPU time 22.05 seconds
Started Jun 23 06:16:02 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201388 kb
Host smart-7b89c740-64aa-4561-bc9d-1615d6de2088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140203114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3140203114
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2640160082
Short name T864
Test name
Test status
Simulation time 641429791 ps
CPU time 2.89 seconds
Started Jun 23 06:16:03 PM PDT 24
Finished Jun 23 06:16:07 PM PDT 24
Peak memory 201436 kb
Host smart-b51c3bf7-e555-4f30-aabb-bf47b95e32de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640160082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2640160082
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2952139695
Short name T870
Test name
Test status
Simulation time 4521509461 ps
CPU time 12.5 seconds
Started Jun 23 06:16:02 PM PDT 24
Finished Jun 23 06:16:15 PM PDT 24
Peak memory 201432 kb
Host smart-a5ed6303-4422-4662-8695-4faa24eceecb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952139695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2952139695
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.934762026
Short name T122
Test name
Test status
Simulation time 1012450056 ps
CPU time 2.24 seconds
Started Jun 23 06:16:06 PM PDT 24
Finished Jun 23 06:16:09 PM PDT 24
Peak memory 201300 kb
Host smart-53777de4-d269-4ca4-8cb8-907955cf5804
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934762026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.934762026
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2652614247
Short name T916
Test name
Test status
Simulation time 38694486250 ps
CPU time 119.67 seconds
Started Jun 23 06:16:00 PM PDT 24
Finished Jun 23 06:18:00 PM PDT 24
Peak memory 201396 kb
Host smart-e64498aa-6c09-4474-8382-137455617073
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652614247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2652614247
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.767565084
Short name T103
Test name
Test status
Simulation time 845598663 ps
CPU time 1.12 seconds
Started Jun 23 06:16:15 PM PDT 24
Finished Jun 23 06:16:16 PM PDT 24
Peak memory 201156 kb
Host smart-b084af36-9349-4ee9-be60-135e694fe30d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767565084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.767565084
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.264448123
Short name T855
Test name
Test status
Simulation time 644516351 ps
CPU time 2.43 seconds
Started Jun 23 06:15:57 PM PDT 24
Finished Jun 23 06:16:00 PM PDT 24
Peak memory 201200 kb
Host smart-42ce832c-4fe3-4d5d-a504-52bfb3e23da9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264448123 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.264448123
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2588634422
Short name T837
Test name
Test status
Simulation time 339084263 ps
CPU time 1.54 seconds
Started Jun 23 06:16:02 PM PDT 24
Finished Jun 23 06:16:04 PM PDT 24
Peak memory 201140 kb
Host smart-ff319c0d-5742-4963-a9b3-6ad7626dacdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588634422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2588634422
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1632491891
Short name T860
Test name
Test status
Simulation time 411243756 ps
CPU time 1.12 seconds
Started Jun 23 06:16:00 PM PDT 24
Finished Jun 23 06:16:01 PM PDT 24
Peak memory 201324 kb
Host smart-0ed931c5-6174-48dd-bcfa-24e2aa9a0810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632491891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1632491891
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3003784923
Short name T62
Test name
Test status
Simulation time 372466105 ps
CPU time 1.96 seconds
Started Jun 23 06:15:56 PM PDT 24
Finished Jun 23 06:15:58 PM PDT 24
Peak memory 201460 kb
Host smart-cc4a7d6e-412d-4cd4-8a43-55c4801312b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003784923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3003784923
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3199292561
Short name T806
Test name
Test status
Simulation time 4806500235 ps
CPU time 4.46 seconds
Started Jun 23 06:15:59 PM PDT 24
Finished Jun 23 06:16:04 PM PDT 24
Peak memory 201460 kb
Host smart-6256743e-8496-4a23-b205-7938476e022f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199292561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3199292561
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.654290810
Short name T903
Test name
Test status
Simulation time 361099012 ps
CPU time 1.52 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:22 PM PDT 24
Peak memory 201160 kb
Host smart-ae5a5d80-0ca3-4a63-b7a6-94a5ecf052ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654290810 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.654290810
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.866916206
Short name T907
Test name
Test status
Simulation time 523528113 ps
CPU time 0.98 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:20 PM PDT 24
Peak memory 201164 kb
Host smart-26a7c0d4-8dec-4971-930c-5cce4f072e44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866916206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.866916206
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1786134550
Short name T835
Test name
Test status
Simulation time 328116995 ps
CPU time 0.81 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201156 kb
Host smart-33bf81d6-9983-4771-b958-2c99e3d19bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786134550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1786134550
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2349971744
Short name T856
Test name
Test status
Simulation time 3870615423 ps
CPU time 10.11 seconds
Started Jun 23 06:16:17 PM PDT 24
Finished Jun 23 06:16:27 PM PDT 24
Peak memory 201324 kb
Host smart-ac5688f9-2691-4669-9e0e-c9a1351bd073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349971744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2349971744
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2434083812
Short name T863
Test name
Test status
Simulation time 534370772 ps
CPU time 2.99 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201420 kb
Host smart-d05956dc-c642-4c9b-a3e8-d205a95cb7bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434083812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2434083812
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.115899731
Short name T96
Test name
Test status
Simulation time 4105500372 ps
CPU time 6.93 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201428 kb
Host smart-fd7a8362-4c82-4739-a36f-bfab3e176741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115899731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.115899731
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2123857570
Short name T850
Test name
Test status
Simulation time 450240031 ps
CPU time 1.03 seconds
Started Jun 23 06:16:16 PM PDT 24
Finished Jun 23 06:16:18 PM PDT 24
Peak memory 201204 kb
Host smart-6ac0ea7c-bd54-481b-a00e-83dfc9826a58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123857570 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2123857570
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3232086794
Short name T112
Test name
Test status
Simulation time 377537439 ps
CPU time 0.96 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 201132 kb
Host smart-06aab003-c7be-42f1-820f-9208b03e69c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232086794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3232086794
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1841594825
Short name T809
Test name
Test status
Simulation time 350833036 ps
CPU time 0.88 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:22 PM PDT 24
Peak memory 201132 kb
Host smart-d03ad765-6b55-4f1b-b9b0-da393a4c2803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841594825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1841594825
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.935916594
Short name T905
Test name
Test status
Simulation time 2880346550 ps
CPU time 11.39 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:34 PM PDT 24
Peak memory 201220 kb
Host smart-806d8d15-578e-4cc6-9a6d-277771f1ecab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935916594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.935916594
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.327018206
Short name T906
Test name
Test status
Simulation time 563331591 ps
CPU time 2.58 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201424 kb
Host smart-d7141b09-b6d2-4329-922d-db481e126d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327018206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.327018206
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1201409911
Short name T859
Test name
Test status
Simulation time 4486260580 ps
CPU time 11.59 seconds
Started Jun 23 06:16:16 PM PDT 24
Finished Jun 23 06:16:28 PM PDT 24
Peak memory 201396 kb
Host smart-3080fc14-f7e4-4822-967d-6b87262accd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201409911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1201409911
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.192948301
Short name T820
Test name
Test status
Simulation time 498435208 ps
CPU time 1.69 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:24 PM PDT 24
Peak memory 201236 kb
Host smart-4623bbdf-5073-4ee5-9767-5c54a93253bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192948301 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.192948301
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1454735545
Short name T832
Test name
Test status
Simulation time 492335189 ps
CPU time 1.01 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 201140 kb
Host smart-b1cea4ec-677b-45b4-9dff-7057c3afb926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454735545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1454735545
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1458791464
Short name T799
Test name
Test status
Simulation time 483341559 ps
CPU time 1.77 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:22 PM PDT 24
Peak memory 201124 kb
Host smart-1abae2a6-abcd-4beb-b574-762420b07b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458791464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1458791464
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.487972077
Short name T896
Test name
Test status
Simulation time 4534168240 ps
CPU time 3.53 seconds
Started Jun 23 06:16:16 PM PDT 24
Finished Jun 23 06:16:20 PM PDT 24
Peak memory 201424 kb
Host smart-a5642ad0-829e-4853-9ca8-d402f3fd2105
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487972077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.487972077
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3041607164
Short name T853
Test name
Test status
Simulation time 632848891 ps
CPU time 3.04 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 217804 kb
Host smart-4e2f71c2-e615-4fdc-a727-8c3f3ad85f71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041607164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3041607164
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3794118476
Short name T878
Test name
Test status
Simulation time 4317691708 ps
CPU time 10.56 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:31 PM PDT 24
Peak memory 201336 kb
Host smart-bd77bfc3-6706-4fde-8792-7c34b0b7739e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794118476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3794118476
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.101041711
Short name T841
Test name
Test status
Simulation time 331437735 ps
CPU time 1.5 seconds
Started Jun 23 06:16:17 PM PDT 24
Finished Jun 23 06:16:19 PM PDT 24
Peak memory 201232 kb
Host smart-76c6c8ea-3951-43be-9cdf-623cf4fe0aac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101041711 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.101041711
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.805190175
Short name T118
Test name
Test status
Simulation time 602697129 ps
CPU time 1.27 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 201136 kb
Host smart-c3f3dd6a-ab40-4b91-b6b2-ece8b7e18e74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805190175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.805190175
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.963247557
Short name T848
Test name
Test status
Simulation time 397036730 ps
CPU time 1.43 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201164 kb
Host smart-02e93dca-5b7c-4cd1-a13e-728e6f40bee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963247557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.963247557
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.663600503
Short name T44
Test name
Test status
Simulation time 2627261087 ps
CPU time 6.6 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:29 PM PDT 24
Peak memory 201184 kb
Host smart-986dacef-068a-464d-b8c1-c3214c3830d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663600503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.663600503
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1535739510
Short name T911
Test name
Test status
Simulation time 771142842 ps
CPU time 2.31 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 217772 kb
Host smart-db357bb1-5ea8-4726-84c5-3b374930a637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535739510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1535739510
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3178743331
Short name T823
Test name
Test status
Simulation time 5016044500 ps
CPU time 2.37 seconds
Started Jun 23 06:16:17 PM PDT 24
Finished Jun 23 06:16:20 PM PDT 24
Peak memory 201432 kb
Host smart-71ee49b6-88f9-4e1d-982f-25ba93927c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178743331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3178743331
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.77619265
Short name T815
Test name
Test status
Simulation time 375958129 ps
CPU time 1.63 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:22 PM PDT 24
Peak memory 201204 kb
Host smart-eb77a3be-1571-49ba-8d49-1920bfa8db9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77619265 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.77619265
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.4137368474
Short name T110
Test name
Test status
Simulation time 447606416 ps
CPU time 1.34 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:24 PM PDT 24
Peak memory 201164 kb
Host smart-a839909a-e95d-4d8f-87cf-45ff13f40edc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137368474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.4137368474
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3451388254
Short name T857
Test name
Test status
Simulation time 412441154 ps
CPU time 1.54 seconds
Started Jun 23 06:16:17 PM PDT 24
Finished Jun 23 06:16:19 PM PDT 24
Peak memory 201164 kb
Host smart-ea5cd85d-10d6-454b-a337-7e50fa2a619e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451388254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3451388254
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.748934748
Short name T119
Test name
Test status
Simulation time 2599229983 ps
CPU time 8.07 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:27 PM PDT 24
Peak memory 201196 kb
Host smart-9ce2f464-2a16-4770-92c8-230f4d69b5de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748934748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.748934748
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2280815689
Short name T871
Test name
Test status
Simulation time 372332758 ps
CPU time 2.87 seconds
Started Jun 23 06:16:17 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 201432 kb
Host smart-668e8533-b24a-4541-ab09-aed535cb5dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280815689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2280815689
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3239788514
Short name T852
Test name
Test status
Simulation time 646511632 ps
CPU time 1.26 seconds
Started Jun 23 06:16:17 PM PDT 24
Finished Jun 23 06:16:19 PM PDT 24
Peak memory 201252 kb
Host smart-1e892533-28db-4667-a743-4b4bb55fa8cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239788514 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3239788514
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1997477386
Short name T861
Test name
Test status
Simulation time 444339510 ps
CPU time 1.75 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 201168 kb
Host smart-8706b39d-c919-4ed8-aaa5-35adcc3ce199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997477386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1997477386
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3294541217
Short name T914
Test name
Test status
Simulation time 514218768 ps
CPU time 0.94 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:23 PM PDT 24
Peak memory 201112 kb
Host smart-cf633007-b410-4562-8b39-2ff090122769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294541217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3294541217
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4278504603
Short name T121
Test name
Test status
Simulation time 4734087967 ps
CPU time 8.65 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:27 PM PDT 24
Peak memory 201396 kb
Host smart-d9993509-94dd-4236-9521-4f7b4c714414
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278504603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.4278504603
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1296275974
Short name T65
Test name
Test status
Simulation time 8662713562 ps
CPU time 7.67 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201424 kb
Host smart-5ed4c722-13a8-4a9b-83ff-d0321428b19a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296275974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1296275974
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1581851761
Short name T808
Test name
Test status
Simulation time 383065564 ps
CPU time 1.24 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:24 PM PDT 24
Peak memory 201232 kb
Host smart-3bc7c353-9663-4567-8476-fb93e7f96ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581851761 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1581851761
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.472357718
Short name T113
Test name
Test status
Simulation time 404416338 ps
CPU time 1.65 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:20 PM PDT 24
Peak memory 201140 kb
Host smart-091ee8be-7625-4c9a-b37a-08524590bd44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472357718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.472357718
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2967299190
Short name T828
Test name
Test status
Simulation time 406925715 ps
CPU time 1.5 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:23 PM PDT 24
Peak memory 201112 kb
Host smart-67ebfa57-4131-475e-aa09-6a5f71a8a016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967299190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2967299190
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2131023305
Short name T827
Test name
Test status
Simulation time 2427659101 ps
CPU time 9.85 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:32 PM PDT 24
Peak memory 201236 kb
Host smart-9e774ac5-39e2-49ea-a705-be159fc95b04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131023305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2131023305
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3067832469
Short name T64
Test name
Test status
Simulation time 10337319897 ps
CPU time 7.5 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201428 kb
Host smart-182ce646-07f7-408c-ae80-6cb66ddc024f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067832469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3067832469
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2465469953
Short name T817
Test name
Test status
Simulation time 625255397 ps
CPU time 1.18 seconds
Started Jun 23 06:16:25 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201216 kb
Host smart-9008fef8-de5b-4f10-9aa8-84914036b8a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465469953 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2465469953
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1420699540
Short name T918
Test name
Test status
Simulation time 412840134 ps
CPU time 1.03 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:22 PM PDT 24
Peak memory 201124 kb
Host smart-6b96fa59-8e95-4c77-a020-e1a8f85a6d34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420699540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1420699540
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2590287555
Short name T798
Test name
Test status
Simulation time 401733652 ps
CPU time 1.5 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 201128 kb
Host smart-4018bb9f-712f-4232-901c-db80e71a894a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590287555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2590287555
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1781529802
Short name T915
Test name
Test status
Simulation time 4498248415 ps
CPU time 3.96 seconds
Started Jun 23 06:16:25 PM PDT 24
Finished Jun 23 06:16:29 PM PDT 24
Peak memory 201392 kb
Host smart-79e6c989-4483-4688-8b10-a18424020559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781529802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1781529802
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4125635497
Short name T824
Test name
Test status
Simulation time 1117101269 ps
CPU time 3.67 seconds
Started Jun 23 06:16:16 PM PDT 24
Finished Jun 23 06:16:20 PM PDT 24
Peak memory 209712 kb
Host smart-ea458f73-4b79-46a7-b584-248b08b3a597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125635497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.4125635497
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1690490937
Short name T888
Test name
Test status
Simulation time 8725260647 ps
CPU time 7.5 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:27 PM PDT 24
Peak memory 201460 kb
Host smart-45375ead-f570-42c0-a863-7a1f9c32ee02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690490937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1690490937
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.809825390
Short name T61
Test name
Test status
Simulation time 777449870 ps
CPU time 1.22 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201204 kb
Host smart-6fedd6b5-3a58-46d8-a0ef-ccea5bdc5f2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809825390 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.809825390
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2843901769
Short name T909
Test name
Test status
Simulation time 480183669 ps
CPU time 1.71 seconds
Started Jun 23 06:16:24 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201148 kb
Host smart-2ed09012-10fd-4ae1-9d69-14d917daaf57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843901769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2843901769
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.322066046
Short name T879
Test name
Test status
Simulation time 291869423 ps
CPU time 1.04 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201156 kb
Host smart-3c91b1c3-41c9-4a15-90d4-c6962cdb6641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322066046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.322066046
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3845552829
Short name T867
Test name
Test status
Simulation time 2525981274 ps
CPU time 1.27 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:24 PM PDT 24
Peak memory 201216 kb
Host smart-9a895744-72b7-4fc8-ae3f-cebed77d13af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845552829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3845552829
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3688697940
Short name T845
Test name
Test status
Simulation time 611312169 ps
CPU time 3.38 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:27 PM PDT 24
Peak memory 201456 kb
Host smart-c69c28fc-2c89-49df-a26b-c2e41dc15407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688697940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3688697940
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2195487166
Short name T46
Test name
Test status
Simulation time 8864921549 ps
CPU time 6.13 seconds
Started Jun 23 06:16:24 PM PDT 24
Finished Jun 23 06:16:31 PM PDT 24
Peak memory 201392 kb
Host smart-eee9d826-1014-43a5-af08-8179104c095a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195487166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2195487166
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1215792881
Short name T60
Test name
Test status
Simulation time 747908228 ps
CPU time 1.21 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:23 PM PDT 24
Peak memory 201232 kb
Host smart-67f9c1c6-2694-4784-8054-c8ea56b8c520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215792881 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1215792881
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2630789068
Short name T840
Test name
Test status
Simulation time 401884246 ps
CPU time 0.79 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201144 kb
Host smart-e8c22a80-1d67-4f56-9f05-7a5d9bb40f6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630789068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2630789068
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.231074961
Short name T810
Test name
Test status
Simulation time 387241086 ps
CPU time 0.79 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:24 PM PDT 24
Peak memory 201156 kb
Host smart-3ab378bc-a19e-47ba-a0c7-028724ac8a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231074961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.231074961
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.597427093
Short name T882
Test name
Test status
Simulation time 2652237736 ps
CPU time 2.39 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201224 kb
Host smart-66164323-a812-488e-a167-24fa4f35ea55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597427093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.597427093
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1047707373
Short name T830
Test name
Test status
Simulation time 573816876 ps
CPU time 2.85 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201344 kb
Host smart-0354b2ae-1369-4b3e-815f-76a4dc586bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047707373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1047707373
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.875896677
Short name T865
Test name
Test status
Simulation time 1228476252 ps
CPU time 3.53 seconds
Started Jun 23 06:16:07 PM PDT 24
Finished Jun 23 06:16:11 PM PDT 24
Peak memory 201360 kb
Host smart-eaa36c22-93fa-4d29-aa67-6d6704fbe885
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875896677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.875896677
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1974609396
Short name T105
Test name
Test status
Simulation time 50709647432 ps
CPU time 61.69 seconds
Started Jun 23 06:16:06 PM PDT 24
Finished Jun 23 06:17:08 PM PDT 24
Peak memory 201356 kb
Host smart-250c6780-3f37-4b8a-bb3c-bbd83200edb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974609396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1974609396
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.803469995
Short name T842
Test name
Test status
Simulation time 1287206309 ps
CPU time 2.12 seconds
Started Jun 23 06:15:59 PM PDT 24
Finished Jun 23 06:16:01 PM PDT 24
Peak memory 201152 kb
Host smart-6f429e69-53f8-4caa-bf58-89ec4701e40f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803469995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.803469995
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4044135110
Short name T894
Test name
Test status
Simulation time 487197619 ps
CPU time 1.94 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:08 PM PDT 24
Peak memory 201200 kb
Host smart-364a5a6e-fab1-433e-9fe3-93d8eebfee84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044135110 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.4044135110
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3310469732
Short name T847
Test name
Test status
Simulation time 342410909 ps
CPU time 0.87 seconds
Started Jun 23 06:16:01 PM PDT 24
Finished Jun 23 06:16:02 PM PDT 24
Peak memory 201324 kb
Host smart-b2a3e87f-53cb-47c3-8d05-ec08f4cb65e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310469732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3310469732
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4294660230
Short name T866
Test name
Test status
Simulation time 4725506490 ps
CPU time 3.76 seconds
Started Jun 23 06:16:06 PM PDT 24
Finished Jun 23 06:16:10 PM PDT 24
Peak memory 201372 kb
Host smart-451639d5-4488-42bd-ad5d-656b8d8e9015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294660230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.4294660230
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2817432923
Short name T884
Test name
Test status
Simulation time 661306988 ps
CPU time 2.81 seconds
Started Jun 23 06:16:02 PM PDT 24
Finished Jun 23 06:16:05 PM PDT 24
Peak memory 209636 kb
Host smart-09bc8ac7-d788-4a59-95df-e703671d6620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817432923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2817432923
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.491455417
Short name T58
Test name
Test status
Simulation time 4632585085 ps
CPU time 5.24 seconds
Started Jun 23 06:16:02 PM PDT 24
Finished Jun 23 06:16:08 PM PDT 24
Peak memory 201408 kb
Host smart-09d4f5bd-d917-4e76-847e-b2d0612d38e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491455417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.491455417
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1259340653
Short name T818
Test name
Test status
Simulation time 351414394 ps
CPU time 1.02 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:23 PM PDT 24
Peak memory 201080 kb
Host smart-d8941f9b-7104-4034-95f8-8c6a96be93b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259340653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1259340653
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2693051046
Short name T838
Test name
Test status
Simulation time 440835062 ps
CPU time 1.68 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201168 kb
Host smart-99b76238-016c-4f71-ae6e-7c08b7d44284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693051046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2693051046
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3569075125
Short name T801
Test name
Test status
Simulation time 287954567 ps
CPU time 1.35 seconds
Started Jun 23 06:16:24 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201164 kb
Host smart-3e1499e2-1280-460d-bbc0-210662e1ee8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569075125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3569075125
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3080184954
Short name T807
Test name
Test status
Simulation time 436683343 ps
CPU time 0.8 seconds
Started Jun 23 06:16:26 PM PDT 24
Finished Jun 23 06:16:27 PM PDT 24
Peak memory 201152 kb
Host smart-de18141c-bdc5-48af-9bd4-338645a49d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080184954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3080184954
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.388590870
Short name T802
Test name
Test status
Simulation time 491856879 ps
CPU time 1.84 seconds
Started Jun 23 06:16:24 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201152 kb
Host smart-1bf2a18c-be66-4b64-80d3-a4b9cec2698d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388590870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.388590870
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2883480387
Short name T811
Test name
Test status
Simulation time 385481489 ps
CPU time 1.65 seconds
Started Jun 23 06:16:29 PM PDT 24
Finished Jun 23 06:16:31 PM PDT 24
Peak memory 201124 kb
Host smart-a33d45e6-4563-4134-8c2a-448025d718e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883480387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2883480387
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2146043077
Short name T893
Test name
Test status
Simulation time 396391432 ps
CPU time 1.55 seconds
Started Jun 23 06:16:26 PM PDT 24
Finished Jun 23 06:16:28 PM PDT 24
Peak memory 201156 kb
Host smart-012ce045-c4f6-4652-8719-ef1a8f8cf2f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146043077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2146043077
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2189660433
Short name T800
Test name
Test status
Simulation time 413388384 ps
CPU time 1.62 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201128 kb
Host smart-46f8c211-5291-4eed-a67b-80478c10f405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189660433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2189660433
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.967660481
Short name T849
Test name
Test status
Simulation time 512330258 ps
CPU time 0.91 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201152 kb
Host smart-90da1ac1-f672-4e97-b467-1e7d9da1b45d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967660481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.967660481
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.812015886
Short name T846
Test name
Test status
Simulation time 469282765 ps
CPU time 0.81 seconds
Started Jun 23 06:16:23 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201164 kb
Host smart-6d1ace3c-4be1-4af7-8d0b-59c2d1e1e87f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812015886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.812015886
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2452855193
Short name T108
Test name
Test status
Simulation time 1115501321 ps
CPU time 2.94 seconds
Started Jun 23 06:16:07 PM PDT 24
Finished Jun 23 06:16:11 PM PDT 24
Peak memory 201404 kb
Host smart-4e36d090-ea07-40b3-86b2-565c2affe667
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452855193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2452855193
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1655463693
Short name T104
Test name
Test status
Simulation time 24367188094 ps
CPU time 28.62 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:34 PM PDT 24
Peak memory 201380 kb
Host smart-63c2fdab-1358-479e-8cbd-e1f16b584a38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655463693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1655463693
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1328962447
Short name T836
Test name
Test status
Simulation time 685199353 ps
CPU time 1.11 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:06 PM PDT 24
Peak memory 201128 kb
Host smart-5453bf91-e6a7-4186-aa95-33a9377727d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328962447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1328962447
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.727593352
Short name T78
Test name
Test status
Simulation time 451408229 ps
CPU time 1.84 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:08 PM PDT 24
Peak memory 201228 kb
Host smart-f577f057-3006-4f9f-bd7c-0b3bf1eb32e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727593352 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.727593352
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1052753894
Short name T834
Test name
Test status
Simulation time 430171998 ps
CPU time 1.01 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:07 PM PDT 24
Peak memory 201144 kb
Host smart-a54f595e-64e6-4388-afcf-3d9423b84e3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052753894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1052753894
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1762763531
Short name T819
Test name
Test status
Simulation time 535742992 ps
CPU time 1.84 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:07 PM PDT 24
Peak memory 201324 kb
Host smart-cd9268bd-b11a-469f-992e-495752a4420f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762763531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1762763531
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2192486076
Short name T825
Test name
Test status
Simulation time 2182254118 ps
CPU time 2.24 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:08 PM PDT 24
Peak memory 201236 kb
Host smart-a0422fe5-bbd7-4d87-a2e2-f66700d6cc8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192486076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2192486076
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.210179811
Short name T49
Test name
Test status
Simulation time 988033768 ps
CPU time 2.95 seconds
Started Jun 23 06:16:06 PM PDT 24
Finished Jun 23 06:16:09 PM PDT 24
Peak memory 201396 kb
Host smart-313ded5c-05d0-47e7-8890-e423ab3db8ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210179811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.210179811
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4025545436
Short name T47
Test name
Test status
Simulation time 8144301164 ps
CPU time 20.52 seconds
Started Jun 23 06:16:12 PM PDT 24
Finished Jun 23 06:16:33 PM PDT 24
Peak memory 201364 kb
Host smart-c5ac6879-d319-470d-b087-5c81853aa544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025545436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.4025545436
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3746030748
Short name T831
Test name
Test status
Simulation time 354995983 ps
CPU time 0.77 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:23 PM PDT 24
Peak memory 201088 kb
Host smart-2ddaa89a-8672-4f4b-b0de-beff01648642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746030748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3746030748
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3678643827
Short name T901
Test name
Test status
Simulation time 403323799 ps
CPU time 1.61 seconds
Started Jun 23 06:16:22 PM PDT 24
Finished Jun 23 06:16:24 PM PDT 24
Peak memory 201308 kb
Host smart-8770babb-193d-4674-8726-c5c7c60c9cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678643827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3678643827
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3011110647
Short name T829
Test name
Test status
Simulation time 339237991 ps
CPU time 1.46 seconds
Started Jun 23 06:16:24 PM PDT 24
Finished Jun 23 06:16:26 PM PDT 24
Peak memory 201128 kb
Host smart-3bc1d569-bde6-412a-87c1-fbf415a2f539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011110647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3011110647
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2628885791
Short name T876
Test name
Test status
Simulation time 293688317 ps
CPU time 1.12 seconds
Started Jun 23 06:16:30 PM PDT 24
Finished Jun 23 06:16:31 PM PDT 24
Peak memory 201156 kb
Host smart-6b298101-08cf-438b-9238-135294d549e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628885791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2628885791
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.181728570
Short name T805
Test name
Test status
Simulation time 382697928 ps
CPU time 1.67 seconds
Started Jun 23 06:16:29 PM PDT 24
Finished Jun 23 06:16:31 PM PDT 24
Peak memory 201164 kb
Host smart-db1a4f01-b962-41f1-9f91-f2cbb3fc1fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181728570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.181728570
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3843935318
Short name T895
Test name
Test status
Simulation time 496853431 ps
CPU time 1.24 seconds
Started Jun 23 06:16:29 PM PDT 24
Finished Jun 23 06:16:30 PM PDT 24
Peak memory 201164 kb
Host smart-1a840e45-e422-43dc-89c6-1b7374a6b630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843935318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3843935318
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1122010194
Short name T875
Test name
Test status
Simulation time 395667391 ps
CPU time 0.9 seconds
Started Jun 23 06:16:26 PM PDT 24
Finished Jun 23 06:16:27 PM PDT 24
Peak memory 201132 kb
Host smart-0c5105b5-461a-43d0-9fd9-52061d0619f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122010194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1122010194
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3780141613
Short name T880
Test name
Test status
Simulation time 448480031 ps
CPU time 0.83 seconds
Started Jun 23 06:16:27 PM PDT 24
Finished Jun 23 06:16:28 PM PDT 24
Peak memory 201164 kb
Host smart-b7fd52b9-f9e8-4f84-bf27-3a5c52369908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780141613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3780141613
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.97862142
Short name T804
Test name
Test status
Simulation time 354045937 ps
CPU time 0.87 seconds
Started Jun 23 06:16:33 PM PDT 24
Finished Jun 23 06:16:34 PM PDT 24
Peak memory 201168 kb
Host smart-64abc194-9899-408d-b028-094cb22b3dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97862142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.97862142
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1381729845
Short name T816
Test name
Test status
Simulation time 447447285 ps
CPU time 1.11 seconds
Started Jun 23 06:16:27 PM PDT 24
Finished Jun 23 06:16:28 PM PDT 24
Peak memory 201136 kb
Host smart-876f9ecf-4fd7-4433-bf00-b1ef716c34f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381729845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1381729845
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1567839535
Short name T908
Test name
Test status
Simulation time 801711337 ps
CPU time 3.18 seconds
Started Jun 23 06:16:06 PM PDT 24
Finished Jun 23 06:16:09 PM PDT 24
Peak memory 201332 kb
Host smart-97efda08-336c-4f01-b502-6f24537ada39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567839535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1567839535
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3811548815
Short name T812
Test name
Test status
Simulation time 26085443024 ps
CPU time 46.4 seconds
Started Jun 23 06:16:12 PM PDT 24
Finished Jun 23 06:16:58 PM PDT 24
Peak memory 201408 kb
Host smart-1e60ca22-301f-4eda-a85d-9794bee3897f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811548815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3811548815
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.324532684
Short name T109
Test name
Test status
Simulation time 1269520534 ps
CPU time 1.25 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:07 PM PDT 24
Peak memory 201144 kb
Host smart-c8f69d1c-2692-4d0e-853b-5bf5edc68640
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324532684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.324532684
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1797570247
Short name T881
Test name
Test status
Simulation time 491299693 ps
CPU time 1.04 seconds
Started Jun 23 06:16:12 PM PDT 24
Finished Jun 23 06:16:14 PM PDT 24
Peak memory 201244 kb
Host smart-a93d7a43-769b-4c5b-8425-dba0b3bc861a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797570247 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1797570247
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1531257288
Short name T887
Test name
Test status
Simulation time 448667748 ps
CPU time 1.34 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:07 PM PDT 24
Peak memory 201144 kb
Host smart-22aa0bcb-cd85-48d8-be15-1c461f96f023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531257288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1531257288
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.676860622
Short name T904
Test name
Test status
Simulation time 320861393 ps
CPU time 1.42 seconds
Started Jun 23 06:16:08 PM PDT 24
Finished Jun 23 06:16:10 PM PDT 24
Peak memory 201152 kb
Host smart-6150373f-e667-45de-8608-217a70fc9989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676860622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.676860622
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2110779913
Short name T42
Test name
Test status
Simulation time 3561650987 ps
CPU time 5.01 seconds
Started Jun 23 06:16:11 PM PDT 24
Finished Jun 23 06:16:16 PM PDT 24
Peak memory 201428 kb
Host smart-33942c18-0b6e-4158-b67d-128f62ee8881
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110779913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2110779913
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1904641560
Short name T54
Test name
Test status
Simulation time 544079213 ps
CPU time 1.81 seconds
Started Jun 23 06:16:05 PM PDT 24
Finished Jun 23 06:16:07 PM PDT 24
Peak memory 201420 kb
Host smart-c70841fe-552d-4dc9-a887-4d342078b62a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904641560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1904641560
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.722204699
Short name T891
Test name
Test status
Simulation time 8269813444 ps
CPU time 20.15 seconds
Started Jun 23 06:16:14 PM PDT 24
Finished Jun 23 06:16:34 PM PDT 24
Peak memory 201392 kb
Host smart-4340d0d8-4d0f-4ab0-b18c-38394916ec27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722204699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.722204699
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1670985453
Short name T814
Test name
Test status
Simulation time 400133259 ps
CPU time 0.86 seconds
Started Jun 23 06:16:27 PM PDT 24
Finished Jun 23 06:16:29 PM PDT 24
Peak memory 201172 kb
Host smart-84644310-73d9-4bf2-aae6-76c3c7867dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670985453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1670985453
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.773401208
Short name T885
Test name
Test status
Simulation time 381932271 ps
CPU time 0.9 seconds
Started Jun 23 06:16:27 PM PDT 24
Finished Jun 23 06:16:29 PM PDT 24
Peak memory 201316 kb
Host smart-8e6de240-9fb6-4e75-8c27-58be6aebcd60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773401208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.773401208
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1780832888
Short name T900
Test name
Test status
Simulation time 534030140 ps
CPU time 1.21 seconds
Started Jun 23 06:16:31 PM PDT 24
Finished Jun 23 06:16:32 PM PDT 24
Peak memory 201124 kb
Host smart-e14e5e3f-09bc-4071-a8a8-705783f6e58b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780832888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1780832888
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.695083018
Short name T803
Test name
Test status
Simulation time 328020781 ps
CPU time 1 seconds
Started Jun 23 06:16:28 PM PDT 24
Finished Jun 23 06:16:29 PM PDT 24
Peak memory 201124 kb
Host smart-98996fee-d5c0-4322-9dea-6c02e13574f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695083018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.695083018
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3901178793
Short name T886
Test name
Test status
Simulation time 463577612 ps
CPU time 0.92 seconds
Started Jun 23 06:16:33 PM PDT 24
Finished Jun 23 06:16:34 PM PDT 24
Peak memory 201168 kb
Host smart-186e4b3c-2ba0-463a-9775-4c52cbf4ac99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901178793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3901178793
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3951054773
Short name T899
Test name
Test status
Simulation time 478241653 ps
CPU time 0.88 seconds
Started Jun 23 06:16:28 PM PDT 24
Finished Jun 23 06:16:30 PM PDT 24
Peak memory 201152 kb
Host smart-eb4ba914-bdd1-41e4-bb84-c82024e15945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951054773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3951054773
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1216251919
Short name T869
Test name
Test status
Simulation time 375343227 ps
CPU time 1.5 seconds
Started Jun 23 06:16:28 PM PDT 24
Finished Jun 23 06:16:30 PM PDT 24
Peak memory 201164 kb
Host smart-d8102596-a7a7-47cd-b69c-4391c30fef95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216251919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1216251919
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2413508757
Short name T890
Test name
Test status
Simulation time 598809366 ps
CPU time 0.73 seconds
Started Jun 23 06:16:27 PM PDT 24
Finished Jun 23 06:16:28 PM PDT 24
Peak memory 201128 kb
Host smart-cdc5f9db-534d-4e2c-aae6-76b6655a5738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413508757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2413508757
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2394374574
Short name T854
Test name
Test status
Simulation time 322556720 ps
CPU time 1.28 seconds
Started Jun 23 06:16:26 PM PDT 24
Finished Jun 23 06:16:28 PM PDT 24
Peak memory 201324 kb
Host smart-02b11529-3622-4cac-a087-fc82368a8af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394374574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2394374574
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.493177214
Short name T892
Test name
Test status
Simulation time 440311845 ps
CPU time 1.15 seconds
Started Jun 23 06:16:33 PM PDT 24
Finished Jun 23 06:16:35 PM PDT 24
Peak memory 201168 kb
Host smart-2e4e0906-377b-41b2-8458-f7cf8b22ff12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493177214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.493177214
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4113467268
Short name T874
Test name
Test status
Simulation time 625663888 ps
CPU time 2.37 seconds
Started Jun 23 06:16:10 PM PDT 24
Finished Jun 23 06:16:13 PM PDT 24
Peak memory 201232 kb
Host smart-dbbc7ce6-3cae-4127-ab48-770ecb6ebd59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113467268 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.4113467268
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2259591193
Short name T107
Test name
Test status
Simulation time 431352843 ps
CPU time 1.02 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:22 PM PDT 24
Peak memory 201164 kb
Host smart-9187ad46-548f-415a-8580-9c632f267a39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259591193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2259591193
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2261394780
Short name T889
Test name
Test status
Simulation time 394125433 ps
CPU time 0.89 seconds
Started Jun 23 06:16:14 PM PDT 24
Finished Jun 23 06:16:15 PM PDT 24
Peak memory 201104 kb
Host smart-dd9dbbeb-f0a8-4c26-aef9-9be3ef30e801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261394780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2261394780
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3451922196
Short name T898
Test name
Test status
Simulation time 4241207223 ps
CPU time 5.85 seconds
Started Jun 23 06:16:13 PM PDT 24
Finished Jun 23 06:16:19 PM PDT 24
Peak memory 201424 kb
Host smart-43cd9fbf-f8f0-4c2a-a4a5-28f350b48509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451922196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3451922196
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4193553067
Short name T813
Test name
Test status
Simulation time 321418973 ps
CPU time 3.38 seconds
Started Jun 23 06:16:12 PM PDT 24
Finished Jun 23 06:16:16 PM PDT 24
Peak memory 210688 kb
Host smart-fa586643-bc8e-4e1a-9fdf-e4b6fd430076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193553067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4193553067
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2989852360
Short name T868
Test name
Test status
Simulation time 4493878298 ps
CPU time 4.28 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:25 PM PDT 24
Peak memory 201452 kb
Host smart-865f8a86-2f3d-422e-bbdd-499061d94b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989852360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2989852360
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4217926559
Short name T912
Test name
Test status
Simulation time 497599015 ps
CPU time 1.27 seconds
Started Jun 23 06:16:10 PM PDT 24
Finished Jun 23 06:16:11 PM PDT 24
Peak memory 201244 kb
Host smart-66bc6842-5822-444f-b7e6-7a05e0a09219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217926559 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.4217926559
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2572873729
Short name T106
Test name
Test status
Simulation time 526543667 ps
CPU time 1.01 seconds
Started Jun 23 06:16:11 PM PDT 24
Finished Jun 23 06:16:13 PM PDT 24
Peak memory 201168 kb
Host smart-ffbcba1e-a22f-46df-86da-0ca93773657d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572873729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2572873729
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3390989140
Short name T821
Test name
Test status
Simulation time 475439958 ps
CPU time 0.9 seconds
Started Jun 23 06:16:12 PM PDT 24
Finished Jun 23 06:16:13 PM PDT 24
Peak memory 201156 kb
Host smart-faf99a6c-6dd5-4ced-8544-c4642656ac53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390989140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3390989140
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2417003546
Short name T822
Test name
Test status
Simulation time 2902328238 ps
CPU time 3.62 seconds
Started Jun 23 06:16:14 PM PDT 24
Finished Jun 23 06:16:18 PM PDT 24
Peak memory 201224 kb
Host smart-a8181918-4321-4af1-ad59-9211d9ed42f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417003546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2417003546
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.524865871
Short name T902
Test name
Test status
Simulation time 599459327 ps
CPU time 2.07 seconds
Started Jun 23 06:16:15 PM PDT 24
Finished Jun 23 06:16:17 PM PDT 24
Peak memory 201444 kb
Host smart-9b211688-147a-418d-88c1-213771be2102
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524865871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.524865871
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2688828637
Short name T851
Test name
Test status
Simulation time 4280041645 ps
CPU time 4.67 seconds
Started Jun 23 06:16:13 PM PDT 24
Finished Jun 23 06:16:18 PM PDT 24
Peak memory 201404 kb
Host smart-d94683b8-5f3e-4573-8228-a84a3f71e5fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688828637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2688828637
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2006060839
Short name T910
Test name
Test status
Simulation time 480352987 ps
CPU time 1.05 seconds
Started Jun 23 06:16:10 PM PDT 24
Finished Jun 23 06:16:12 PM PDT 24
Peak memory 201228 kb
Host smart-eda30d3e-50b7-4a35-bc83-5bc42cf4fc25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006060839 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2006060839
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.191494298
Short name T120
Test name
Test status
Simulation time 521553117 ps
CPU time 2.05 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:24 PM PDT 24
Peak memory 201168 kb
Host smart-df33f945-cafa-421f-8520-bd13b2293234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191494298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.191494298
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2939948496
Short name T833
Test name
Test status
Simulation time 361308355 ps
CPU time 1.51 seconds
Started Jun 23 06:16:10 PM PDT 24
Finished Jun 23 06:16:12 PM PDT 24
Peak memory 201164 kb
Host smart-677c63b7-a6e4-4bdc-b19d-e2aa85c167f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939948496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2939948496
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1748984877
Short name T826
Test name
Test status
Simulation time 2707765577 ps
CPU time 3.87 seconds
Started Jun 23 06:16:13 PM PDT 24
Finished Jun 23 06:16:17 PM PDT 24
Peak memory 201224 kb
Host smart-f6090021-701a-4261-ba43-4ec1ac58d726
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748984877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1748984877
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1982034177
Short name T873
Test name
Test status
Simulation time 568311289 ps
CPU time 1.47 seconds
Started Jun 23 06:16:13 PM PDT 24
Finished Jun 23 06:16:15 PM PDT 24
Peak memory 201348 kb
Host smart-1b34274f-308d-47c4-be21-f08468457d74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982034177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1982034177
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3606786978
Short name T917
Test name
Test status
Simulation time 4718962870 ps
CPU time 6.87 seconds
Started Jun 23 06:16:16 PM PDT 24
Finished Jun 23 06:16:23 PM PDT 24
Peak memory 201456 kb
Host smart-a5704608-689e-4983-9b82-af22854368fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606786978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3606786978
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2015175812
Short name T843
Test name
Test status
Simulation time 502964414 ps
CPU time 2 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:23 PM PDT 24
Peak memory 201228 kb
Host smart-ab3c2a4f-dd4c-4a7d-ad4e-f7c0f74a1b7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015175812 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2015175812
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3531955739
Short name T115
Test name
Test status
Simulation time 530980418 ps
CPU time 1.39 seconds
Started Jun 23 06:16:20 PM PDT 24
Finished Jun 23 06:16:22 PM PDT 24
Peak memory 201164 kb
Host smart-464040ce-31b0-4546-913b-e04edee3af5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531955739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3531955739
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2454926342
Short name T897
Test name
Test status
Simulation time 436482969 ps
CPU time 1.6 seconds
Started Jun 23 06:16:12 PM PDT 24
Finished Jun 23 06:16:15 PM PDT 24
Peak memory 201124 kb
Host smart-8b7de1a6-87c4-424f-ab7a-ff315112056f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454926342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2454926342
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1547652386
Short name T862
Test name
Test status
Simulation time 3545962931 ps
CPU time 6.3 seconds
Started Jun 23 06:16:13 PM PDT 24
Finished Jun 23 06:16:20 PM PDT 24
Peak memory 201432 kb
Host smart-a9326cc8-6a55-4212-8a0a-2beae13b3d2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547652386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1547652386
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3290108477
Short name T59
Test name
Test status
Simulation time 576015695 ps
CPU time 3.09 seconds
Started Jun 23 06:16:12 PM PDT 24
Finished Jun 23 06:16:15 PM PDT 24
Peak memory 201468 kb
Host smart-72f688ee-f9f4-4709-ad89-5844e4e03b7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290108477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3290108477
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2045326640
Short name T346
Test name
Test status
Simulation time 9262181952 ps
CPU time 7.81 seconds
Started Jun 23 06:16:11 PM PDT 24
Finished Jun 23 06:16:19 PM PDT 24
Peak memory 201424 kb
Host smart-a6b53e11-be1f-4b47-9196-2ef319297385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045326640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2045326640
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3771753608
Short name T55
Test name
Test status
Simulation time 525327412 ps
CPU time 1.35 seconds
Started Jun 23 06:16:17 PM PDT 24
Finished Jun 23 06:16:18 PM PDT 24
Peak memory 201248 kb
Host smart-bf28c137-f07e-4e6a-a58c-b7766f6c9893
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771753608 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3771753608
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2327577267
Short name T116
Test name
Test status
Simulation time 395335590 ps
CPU time 1.18 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 201168 kb
Host smart-e5ff0344-6337-4dcd-a681-3b4722c93c64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327577267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2327577267
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3924506616
Short name T839
Test name
Test status
Simulation time 287505477 ps
CPU time 0.91 seconds
Started Jun 23 06:16:18 PM PDT 24
Finished Jun 23 06:16:19 PM PDT 24
Peak memory 201120 kb
Host smart-866a8971-8c21-4263-8a93-1b7f884c84ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924506616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3924506616
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2325917023
Short name T877
Test name
Test status
Simulation time 2345490277 ps
CPU time 9.1 seconds
Started Jun 23 06:16:21 PM PDT 24
Finished Jun 23 06:16:31 PM PDT 24
Peak memory 201220 kb
Host smart-2b7a8f44-06fe-4dae-a03b-3ecdec687f66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325917023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2325917023
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.321766759
Short name T50
Test name
Test status
Simulation time 522963130 ps
CPU time 2.62 seconds
Started Jun 23 06:16:12 PM PDT 24
Finished Jun 23 06:16:15 PM PDT 24
Peak memory 201420 kb
Host smart-44b6d37c-3edf-4eab-9dd7-ba95ea12e4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321766759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.321766759
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2375936872
Short name T872
Test name
Test status
Simulation time 4357953665 ps
CPU time 12.44 seconds
Started Jun 23 06:16:19 PM PDT 24
Finished Jun 23 06:16:32 PM PDT 24
Peak memory 201388 kb
Host smart-19344836-7f22-4a91-808d-d189c36f9cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375936872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2375936872
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.4161105668
Short name T580
Test name
Test status
Simulation time 378872235 ps
CPU time 0.8 seconds
Started Jun 23 05:54:58 PM PDT 24
Finished Jun 23 05:54:59 PM PDT 24
Peak memory 201968 kb
Host smart-69536044-5242-4087-836c-7696f7103687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161105668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.4161105668
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.400158467
Short name T316
Test name
Test status
Simulation time 163353131336 ps
CPU time 363.93 seconds
Started Jun 23 05:54:56 PM PDT 24
Finished Jun 23 06:01:00 PM PDT 24
Peak memory 202320 kb
Host smart-671b14c2-5787-49ba-b57d-0bec29148196
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400158467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.400158467
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.27542580
Short name T253
Test name
Test status
Simulation time 183742354684 ps
CPU time 411.35 seconds
Started Jun 23 05:54:56 PM PDT 24
Finished Jun 23 06:01:48 PM PDT 24
Peak memory 202288 kb
Host smart-a912c703-dbc2-4c0d-8034-09a8378e7b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27542580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.27542580
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3696530226
Short name T519
Test name
Test status
Simulation time 317201664031 ps
CPU time 419.67 seconds
Started Jun 23 05:54:54 PM PDT 24
Finished Jun 23 06:01:54 PM PDT 24
Peak memory 202160 kb
Host smart-302f0c74-20f1-490c-9260-3a43ec9283e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696530226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3696530226
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.607334650
Short name T208
Test name
Test status
Simulation time 324781120586 ps
CPU time 764.55 seconds
Started Jun 23 05:54:57 PM PDT 24
Finished Jun 23 06:07:42 PM PDT 24
Peak memory 202200 kb
Host smart-bd0cdb97-2c52-4fa4-a403-16d13c890f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607334650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.607334650
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3635417504
Short name T356
Test name
Test status
Simulation time 166216321757 ps
CPU time 186.73 seconds
Started Jun 23 05:54:54 PM PDT 24
Finished Jun 23 05:58:02 PM PDT 24
Peak memory 202228 kb
Host smart-33c14f92-4b93-45c1-a24b-1221d6b0d3b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635417504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3635417504
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3008047702
Short name T560
Test name
Test status
Simulation time 176437465248 ps
CPU time 97.45 seconds
Started Jun 23 05:54:58 PM PDT 24
Finished Jun 23 05:56:36 PM PDT 24
Peak memory 202268 kb
Host smart-4706ca2d-9cd1-4650-9c36-95850cb6d97c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008047702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3008047702
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1289607495
Short name T435
Test name
Test status
Simulation time 604018930164 ps
CPU time 1162.68 seconds
Started Jun 23 05:54:57 PM PDT 24
Finished Jun 23 06:14:20 PM PDT 24
Peak memory 202248 kb
Host smart-0cb40199-15c1-4e70-8b82-ce5b8c661ef6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289607495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1289607495
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.677657911
Short name T621
Test name
Test status
Simulation time 117988567081 ps
CPU time 424.58 seconds
Started Jun 23 05:55:07 PM PDT 24
Finished Jun 23 06:02:12 PM PDT 24
Peak memory 202544 kb
Host smart-bb1f5427-6b51-499f-992f-e026f24a0862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677657911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.677657911
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1724545028
Short name T494
Test name
Test status
Simulation time 30237549554 ps
CPU time 13 seconds
Started Jun 23 05:54:57 PM PDT 24
Finished Jun 23 05:55:11 PM PDT 24
Peak memory 202080 kb
Host smart-6062169f-d213-4cc7-8f76-8d3d5a33c8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724545028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1724545028
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4290260714
Short name T707
Test name
Test status
Simulation time 5013620451 ps
CPU time 12.2 seconds
Started Jun 23 05:54:59 PM PDT 24
Finished Jun 23 05:55:11 PM PDT 24
Peak memory 202068 kb
Host smart-8fe7cda6-e04f-4e8d-93ef-1d770ff2d558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290260714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4290260714
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1024894898
Short name T53
Test name
Test status
Simulation time 4255849098 ps
CPU time 10.15 seconds
Started Jun 23 05:54:58 PM PDT 24
Finished Jun 23 05:55:08 PM PDT 24
Peak memory 217792 kb
Host smart-81d227e9-564e-4d18-999b-d924bc5c78a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024894898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1024894898
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1571387777
Short name T726
Test name
Test status
Simulation time 5933806235 ps
CPU time 14.25 seconds
Started Jun 23 05:54:53 PM PDT 24
Finished Jun 23 05:55:09 PM PDT 24
Peak memory 202016 kb
Host smart-24e6ee2d-8de1-4175-ae76-648ecafa0175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571387777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1571387777
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3255020069
Short name T458
Test name
Test status
Simulation time 463554788 ps
CPU time 0.9 seconds
Started Jun 23 05:54:59 PM PDT 24
Finished Jun 23 05:55:00 PM PDT 24
Peak memory 201948 kb
Host smart-c9c2d610-31f7-4567-8283-0e5ed60dcbf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255020069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3255020069
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3691246892
Short name T656
Test name
Test status
Simulation time 367182898798 ps
CPU time 226.49 seconds
Started Jun 23 05:55:00 PM PDT 24
Finished Jun 23 05:58:46 PM PDT 24
Peak memory 202280 kb
Host smart-df34923c-80c0-4cf2-bb93-d28c270e026b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691246892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3691246892
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3970134310
Short name T787
Test name
Test status
Simulation time 217332789142 ps
CPU time 509 seconds
Started Jun 23 05:54:58 PM PDT 24
Finished Jun 23 06:03:28 PM PDT 24
Peak memory 202212 kb
Host smart-28d439c7-fcfa-402a-be76-8b819a6eb4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970134310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3970134310
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1756034840
Short name T178
Test name
Test status
Simulation time 170077023175 ps
CPU time 31.07 seconds
Started Jun 23 05:54:58 PM PDT 24
Finished Jun 23 05:55:29 PM PDT 24
Peak memory 202196 kb
Host smart-b3d46c1e-30f0-43d1-b0c5-f5f91454433d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756034840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1756034840
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1575022539
Short name T198
Test name
Test status
Simulation time 164373797211 ps
CPU time 200.27 seconds
Started Jun 23 05:55:01 PM PDT 24
Finished Jun 23 05:58:21 PM PDT 24
Peak memory 202268 kb
Host smart-b558974b-65d2-4823-a256-ab556d205119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575022539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1575022539
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.405311023
Short name T10
Test name
Test status
Simulation time 496267176672 ps
CPU time 308.73 seconds
Started Jun 23 05:54:56 PM PDT 24
Finished Jun 23 06:00:06 PM PDT 24
Peak memory 202200 kb
Host smart-dbf2fb51-84a6-4906-a647-34c183702498
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=405311023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.405311023
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1298966677
Short name T638
Test name
Test status
Simulation time 206942724230 ps
CPU time 515.44 seconds
Started Jun 23 05:54:57 PM PDT 24
Finished Jun 23 06:03:32 PM PDT 24
Peak memory 202312 kb
Host smart-86e2611b-722c-4332-9563-98f09d74fd46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298966677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1298966677
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3773554580
Short name T611
Test name
Test status
Simulation time 213134282902 ps
CPU time 496.69 seconds
Started Jun 23 05:54:58 PM PDT 24
Finished Jun 23 06:03:15 PM PDT 24
Peak memory 202188 kb
Host smart-5846d673-43a6-4012-87f9-638d7c051e56
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773554580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3773554580
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1804760606
Short name T725
Test name
Test status
Simulation time 82237086892 ps
CPU time 330.39 seconds
Started Jun 23 05:54:58 PM PDT 24
Finished Jun 23 06:00:30 PM PDT 24
Peak memory 202628 kb
Host smart-f2aab716-dcf3-4b60-84b8-5d32b44bb857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804760606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1804760606
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1059227676
Short name T394
Test name
Test status
Simulation time 35897009350 ps
CPU time 37.4 seconds
Started Jun 23 05:55:00 PM PDT 24
Finished Jun 23 05:55:37 PM PDT 24
Peak memory 202004 kb
Host smart-8e3a6f30-dfcb-4932-b8c9-4df98ccce79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059227676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1059227676
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2126435116
Short name T4
Test name
Test status
Simulation time 4839721787 ps
CPU time 3.16 seconds
Started Jun 23 05:55:00 PM PDT 24
Finished Jun 23 05:55:03 PM PDT 24
Peak memory 202040 kb
Host smart-e6bd6ebd-817b-4b58-9f86-a9e876d91521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126435116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2126435116
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1829823894
Short name T52
Test name
Test status
Simulation time 4377002357 ps
CPU time 10.19 seconds
Started Jun 23 05:54:58 PM PDT 24
Finished Jun 23 05:55:09 PM PDT 24
Peak memory 217704 kb
Host smart-4bd3d5e5-d34d-4ad5-9331-9dbbc5261506
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829823894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1829823894
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.404176832
Short name T485
Test name
Test status
Simulation time 5750526900 ps
CPU time 3.92 seconds
Started Jun 23 05:54:58 PM PDT 24
Finished Jun 23 05:55:02 PM PDT 24
Peak memory 202044 kb
Host smart-9af9b1ff-48b1-4dc4-a991-f0f7712781ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404176832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.404176832
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3720995325
Short name T727
Test name
Test status
Simulation time 168730248542 ps
CPU time 30.14 seconds
Started Jun 23 05:54:59 PM PDT 24
Finished Jun 23 05:55:29 PM PDT 24
Peak memory 202236 kb
Host smart-82d78282-d663-42ce-9567-b39005760ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720995325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3720995325
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2870704457
Short name T31
Test name
Test status
Simulation time 18512606822 ps
CPU time 65.13 seconds
Started Jun 23 05:54:57 PM PDT 24
Finished Jun 23 05:56:02 PM PDT 24
Peak memory 211056 kb
Host smart-6a81a4fd-a883-4b05-a768-50b7a16dcb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870704457 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2870704457
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3995914369
Short name T601
Test name
Test status
Simulation time 334045830 ps
CPU time 1.32 seconds
Started Jun 23 05:55:33 PM PDT 24
Finished Jun 23 05:55:34 PM PDT 24
Peak memory 201896 kb
Host smart-81505493-e729-45d9-b93b-b22cb2bdface
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995914369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3995914369
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3618641856
Short name T319
Test name
Test status
Simulation time 162521965127 ps
CPU time 258.52 seconds
Started Jun 23 05:55:30 PM PDT 24
Finished Jun 23 05:59:49 PM PDT 24
Peak memory 202260 kb
Host smart-7480de3a-39b5-4b65-bd87-5d4b09f17732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618641856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3618641856
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2903335951
Short name T623
Test name
Test status
Simulation time 484069795448 ps
CPU time 1041.5 seconds
Started Jun 23 05:55:31 PM PDT 24
Finished Jun 23 06:12:53 PM PDT 24
Peak memory 202236 kb
Host smart-763e9f4c-99f5-4b59-b953-a609f516036d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903335951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2903335951
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.900755241
Short name T255
Test name
Test status
Simulation time 329276912543 ps
CPU time 771.02 seconds
Started Jun 23 05:55:32 PM PDT 24
Finished Jun 23 06:08:23 PM PDT 24
Peak memory 202312 kb
Host smart-a96263a0-43b6-4e9a-906c-6c1015f1e9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900755241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.900755241
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2703656600
Short name T475
Test name
Test status
Simulation time 481338695423 ps
CPU time 279.39 seconds
Started Jun 23 05:55:33 PM PDT 24
Finished Jun 23 06:00:13 PM PDT 24
Peak memory 202384 kb
Host smart-5ca198a0-1343-49b9-9642-92200e82cbeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703656600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2703656600
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2342954215
Short name T93
Test name
Test status
Simulation time 369241081336 ps
CPU time 770.46 seconds
Started Jun 23 05:55:28 PM PDT 24
Finished Jun 23 06:08:19 PM PDT 24
Peak memory 202300 kb
Host smart-9342e51b-65a9-44aa-84e6-29f4d5fc3868
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342954215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2342954215
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1763335614
Short name T487
Test name
Test status
Simulation time 196279414936 ps
CPU time 450.83 seconds
Started Jun 23 05:55:30 PM PDT 24
Finished Jun 23 06:03:01 PM PDT 24
Peak memory 202172 kb
Host smart-c7ed1967-6f24-4131-955e-b6fe96b271fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763335614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1763335614
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1094163432
Short name T193
Test name
Test status
Simulation time 132106238449 ps
CPU time 546.82 seconds
Started Jun 23 05:55:32 PM PDT 24
Finished Jun 23 06:04:40 PM PDT 24
Peak memory 202596 kb
Host smart-8cd1e825-e716-4879-b886-3028122bf6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094163432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1094163432
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3615978573
Short name T71
Test name
Test status
Simulation time 44415849492 ps
CPU time 94.09 seconds
Started Jun 23 05:55:30 PM PDT 24
Finished Jun 23 05:57:04 PM PDT 24
Peak memory 202064 kb
Host smart-7cc9898d-cae6-4d2e-8ffe-b291de4defc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615978573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3615978573
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.395104563
Short name T171
Test name
Test status
Simulation time 4034605694 ps
CPU time 1.27 seconds
Started Jun 23 05:55:29 PM PDT 24
Finished Jun 23 05:55:31 PM PDT 24
Peak memory 202076 kb
Host smart-a6b1cc08-c892-4fb1-9ef8-6dd14f36ab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395104563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.395104563
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2928750704
Short name T566
Test name
Test status
Simulation time 6052737675 ps
CPU time 8.2 seconds
Started Jun 23 05:55:31 PM PDT 24
Finished Jun 23 05:55:40 PM PDT 24
Peak memory 202028 kb
Host smart-9cc95ad6-3532-4b3b-a6b1-11b97cc50ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928750704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2928750704
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.573923508
Short name T284
Test name
Test status
Simulation time 441183188030 ps
CPU time 1303.82 seconds
Started Jun 23 05:55:37 PM PDT 24
Finished Jun 23 06:17:21 PM PDT 24
Peak memory 202552 kb
Host smart-b5e33a7b-8a4d-4ad8-b262-c3178b50d045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573923508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
573923508
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2174911165
Short name T177
Test name
Test status
Simulation time 262982409292 ps
CPU time 388.86 seconds
Started Jun 23 05:55:36 PM PDT 24
Finished Jun 23 06:02:06 PM PDT 24
Peak memory 210940 kb
Host smart-9b08d0ff-57c1-4294-ae6d-23f17217b8b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174911165 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2174911165
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2777476407
Short name T604
Test name
Test status
Simulation time 343459295 ps
CPU time 1.43 seconds
Started Jun 23 05:55:40 PM PDT 24
Finished Jun 23 05:55:42 PM PDT 24
Peak memory 201960 kb
Host smart-d6a68ab8-3ce6-44eb-80d7-7013465801df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777476407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2777476407
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2229919321
Short name T176
Test name
Test status
Simulation time 169860756463 ps
CPU time 200.32 seconds
Started Jun 23 05:55:36 PM PDT 24
Finished Jun 23 05:58:57 PM PDT 24
Peak memory 202344 kb
Host smart-f15855ed-da59-4f37-810d-42501dec0ea9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229919321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2229919321
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2852578597
Short name T541
Test name
Test status
Simulation time 482638380677 ps
CPU time 1179.08 seconds
Started Jun 23 05:55:32 PM PDT 24
Finished Jun 23 06:15:11 PM PDT 24
Peak memory 202212 kb
Host smart-b95db0d1-c713-43db-9ee5-a5ef78e7ca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852578597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2852578597
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.331549730
Short name T553
Test name
Test status
Simulation time 326347336076 ps
CPU time 741.65 seconds
Started Jun 23 05:55:32 PM PDT 24
Finished Jun 23 06:07:54 PM PDT 24
Peak memory 202236 kb
Host smart-6e3fd793-b7d7-48e7-b94d-2d2d4bb4bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331549730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.331549730
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2274905359
Short name T469
Test name
Test status
Simulation time 327221386030 ps
CPU time 742.73 seconds
Started Jun 23 05:55:33 PM PDT 24
Finished Jun 23 06:07:56 PM PDT 24
Peak memory 202216 kb
Host smart-2b24cff0-c326-4e03-a4a5-560daa9d2861
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274905359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2274905359
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2788112246
Short name T708
Test name
Test status
Simulation time 167510973620 ps
CPU time 354.07 seconds
Started Jun 23 05:55:32 PM PDT 24
Finished Jun 23 06:01:26 PM PDT 24
Peak memory 202180 kb
Host smart-9ae82122-57c7-4db1-8b7b-fd2bdedab24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788112246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2788112246
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3029013635
Short name T724
Test name
Test status
Simulation time 160205687558 ps
CPU time 49.75 seconds
Started Jun 23 05:55:40 PM PDT 24
Finished Jun 23 05:56:30 PM PDT 24
Peak memory 202220 kb
Host smart-5bbdbe75-e687-4c28-94a5-5744854e3f62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029013635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3029013635
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3724834939
Short name T142
Test name
Test status
Simulation time 430453867232 ps
CPU time 928.06 seconds
Started Jun 23 05:55:32 PM PDT 24
Finished Jun 23 06:11:01 PM PDT 24
Peak memory 202260 kb
Host smart-de730bd3-489d-4293-bd67-bd52af786f4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724834939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3724834939
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.286521187
Short name T500
Test name
Test status
Simulation time 209599638598 ps
CPU time 116.02 seconds
Started Jun 23 05:55:40 PM PDT 24
Finished Jun 23 05:57:36 PM PDT 24
Peak memory 202140 kb
Host smart-6bbb338e-ace5-472f-8014-5aec5def94bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286521187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.286521187
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.957357402
Short name T35
Test name
Test status
Simulation time 104235289392 ps
CPU time 369.64 seconds
Started Jun 23 05:55:38 PM PDT 24
Finished Jun 23 06:01:48 PM PDT 24
Peak memory 202564 kb
Host smart-e92b4109-9cae-4f29-a040-c586c2d2ff97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957357402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.957357402
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2594494515
Short name T154
Test name
Test status
Simulation time 24164136902 ps
CPU time 52.43 seconds
Started Jun 23 05:55:40 PM PDT 24
Finished Jun 23 05:56:33 PM PDT 24
Peak memory 202100 kb
Host smart-982887df-e39e-4d79-8529-5641c3f5e9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594494515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2594494515
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.115294690
Short name T536
Test name
Test status
Simulation time 4970590908 ps
CPU time 11.36 seconds
Started Jun 23 05:55:35 PM PDT 24
Finished Jun 23 05:55:46 PM PDT 24
Peak memory 202068 kb
Host smart-87bcb4f3-0ae9-4952-a51e-7931a4780d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115294690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.115294690
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2511770147
Short name T155
Test name
Test status
Simulation time 5913108400 ps
CPU time 14.82 seconds
Started Jun 23 05:55:34 PM PDT 24
Finished Jun 23 05:55:50 PM PDT 24
Peak memory 202004 kb
Host smart-d622dcd9-c1e4-4f85-9a7c-f186ecacbec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511770147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2511770147
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2236272238
Short name T712
Test name
Test status
Simulation time 663536895645 ps
CPU time 313.62 seconds
Started Jun 23 05:55:39 PM PDT 24
Finished Jun 23 06:00:54 PM PDT 24
Peak memory 202240 kb
Host smart-4a7e8a3f-83d3-4a46-ad06-01acdfb559d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236272238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2236272238
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2952036235
Short name T784
Test name
Test status
Simulation time 483280561 ps
CPU time 0.97 seconds
Started Jun 23 05:55:40 PM PDT 24
Finished Jun 23 05:55:42 PM PDT 24
Peak memory 201960 kb
Host smart-d270d9b4-22a7-4a39-9b98-740b63eed24b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952036235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2952036235
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3455613864
Short name T342
Test name
Test status
Simulation time 165453658224 ps
CPU time 37.07 seconds
Started Jun 23 05:55:42 PM PDT 24
Finished Jun 23 05:56:20 PM PDT 24
Peak memory 202284 kb
Host smart-d81f3ef8-c0a8-4f08-9af1-7868b573d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455613864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3455613864
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2437926167
Short name T511
Test name
Test status
Simulation time 326724548925 ps
CPU time 203.98 seconds
Started Jun 23 05:55:42 PM PDT 24
Finished Jun 23 05:59:07 PM PDT 24
Peak memory 202232 kb
Host smart-3d8f0fde-1c33-4c6d-9f11-f7512a5b5e71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437926167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2437926167
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.471203529
Short name T296
Test name
Test status
Simulation time 327519462459 ps
CPU time 186.16 seconds
Started Jun 23 05:55:40 PM PDT 24
Finished Jun 23 05:58:47 PM PDT 24
Peak memory 202172 kb
Host smart-4a31fd57-e25c-48a5-af94-d202541f243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471203529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.471203529
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.240569755
Short name T376
Test name
Test status
Simulation time 163955133301 ps
CPU time 96.56 seconds
Started Jun 23 05:55:33 PM PDT 24
Finished Jun 23 05:57:10 PM PDT 24
Peak memory 202292 kb
Host smart-6a7471dd-1f62-4ec2-8b62-1e0805b95520
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=240569755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.240569755
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2411701438
Short name T341
Test name
Test status
Simulation time 364977300125 ps
CPU time 207.09 seconds
Started Jun 23 05:55:43 PM PDT 24
Finished Jun 23 05:59:11 PM PDT 24
Peak memory 202240 kb
Host smart-58e58922-8da8-484b-9a4d-24002b1674d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411701438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2411701438
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3898150865
Short name T585
Test name
Test status
Simulation time 387908320211 ps
CPU time 226.75 seconds
Started Jun 23 05:55:42 PM PDT 24
Finished Jun 23 05:59:30 PM PDT 24
Peak memory 202232 kb
Host smart-87d43481-bca3-416f-a48f-f33c1863dd99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898150865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3898150865
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3253244457
Short name T664
Test name
Test status
Simulation time 83348704321 ps
CPU time 351.87 seconds
Started Jun 23 05:55:44 PM PDT 24
Finished Jun 23 06:01:36 PM PDT 24
Peak memory 202504 kb
Host smart-370df8a6-46cb-449a-8b95-199241762250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253244457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3253244457
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.460870330
Short name T443
Test name
Test status
Simulation time 36663722806 ps
CPU time 26.02 seconds
Started Jun 23 05:55:39 PM PDT 24
Finished Jun 23 05:56:06 PM PDT 24
Peak memory 202128 kb
Host smart-a41d471e-5a23-4122-8378-0343f3209a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460870330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.460870330
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.175709742
Short name T606
Test name
Test status
Simulation time 4039126947 ps
CPU time 9.5 seconds
Started Jun 23 05:55:42 PM PDT 24
Finished Jun 23 05:55:52 PM PDT 24
Peak memory 202064 kb
Host smart-8395f832-d105-4cb9-9022-704fd3580edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175709742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.175709742
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1416583961
Short name T653
Test name
Test status
Simulation time 5948827327 ps
CPU time 3.64 seconds
Started Jun 23 05:55:36 PM PDT 24
Finished Jun 23 05:55:40 PM PDT 24
Peak memory 202100 kb
Host smart-3369ee68-368c-4a6f-9e22-7526289e066d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416583961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1416583961
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.541761544
Short name T544
Test name
Test status
Simulation time 292848648928 ps
CPU time 801.42 seconds
Started Jun 23 05:55:42 PM PDT 24
Finished Jun 23 06:09:04 PM PDT 24
Peak memory 211716 kb
Host smart-fe35bd24-ebe0-4ddf-be71-7e925286c069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541761544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
541761544
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.125494834
Short name T29
Test name
Test status
Simulation time 91889553484 ps
CPU time 205.83 seconds
Started Jun 23 05:55:41 PM PDT 24
Finished Jun 23 05:59:08 PM PDT 24
Peak memory 210572 kb
Host smart-30d0db60-d82e-487f-a7d9-374c95f9487d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125494834 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.125494834
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.394237808
Short name T525
Test name
Test status
Simulation time 533453829 ps
CPU time 1.9 seconds
Started Jun 23 05:55:43 PM PDT 24
Finished Jun 23 05:55:46 PM PDT 24
Peak memory 201956 kb
Host smart-f0e09cc1-4f7d-4568-bc23-4e91b5d09bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394237808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.394237808
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.294990233
Short name T277
Test name
Test status
Simulation time 182810448384 ps
CPU time 206.47 seconds
Started Jun 23 05:55:39 PM PDT 24
Finished Jun 23 05:59:06 PM PDT 24
Peak memory 202188 kb
Host smart-74c18ffc-b6df-48b5-8aa2-e9bf7ab0f168
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294990233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.294990233
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1630982021
Short name T270
Test name
Test status
Simulation time 375417457554 ps
CPU time 845.23 seconds
Started Jun 23 05:55:43 PM PDT 24
Finished Jun 23 06:09:49 PM PDT 24
Peak memory 202208 kb
Host smart-378fc33c-56ac-4455-b105-f78756c93b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630982021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1630982021
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1032694489
Short name T703
Test name
Test status
Simulation time 173576079352 ps
CPU time 297.01 seconds
Started Jun 23 05:55:41 PM PDT 24
Finished Jun 23 06:00:39 PM PDT 24
Peak memory 202248 kb
Host smart-34c490b9-0de3-4a2d-9a00-3cfef8d497bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032694489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1032694489
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1309963565
Short name T625
Test name
Test status
Simulation time 323465203626 ps
CPU time 349.38 seconds
Started Jun 23 05:55:42 PM PDT 24
Finished Jun 23 06:01:32 PM PDT 24
Peak memory 202292 kb
Host smart-e15a173d-6e42-44b7-ba57-b7fa7f21d0f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309963565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1309963565
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2051779032
Short name T239
Test name
Test status
Simulation time 321054631394 ps
CPU time 186.3 seconds
Started Jun 23 05:55:42 PM PDT 24
Finished Jun 23 05:58:49 PM PDT 24
Peak memory 202212 kb
Host smart-6cfc27d3-3f87-407c-8442-704d0beaae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051779032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2051779032
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3245479076
Short name T729
Test name
Test status
Simulation time 167046060958 ps
CPU time 346.91 seconds
Started Jun 23 05:55:39 PM PDT 24
Finished Jun 23 06:01:26 PM PDT 24
Peak memory 202172 kb
Host smart-acef3cc7-3c51-454b-b02b-15fbfdb7c1ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245479076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3245479076
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3671108752
Short name T150
Test name
Test status
Simulation time 362180206780 ps
CPU time 213.51 seconds
Started Jun 23 05:55:41 PM PDT 24
Finished Jun 23 05:59:15 PM PDT 24
Peak memory 202324 kb
Host smart-3ba853d6-9a7f-4103-b62b-6e3ca214fb12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671108752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3671108752
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1674977095
Short name T620
Test name
Test status
Simulation time 108909700595 ps
CPU time 597.34 seconds
Started Jun 23 05:55:45 PM PDT 24
Finished Jun 23 06:05:43 PM PDT 24
Peak memory 202636 kb
Host smart-2baedb4b-4370-4429-9de2-e0c2987a95e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674977095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1674977095
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1735836199
Short name T86
Test name
Test status
Simulation time 28049527379 ps
CPU time 8.3 seconds
Started Jun 23 05:55:39 PM PDT 24
Finished Jun 23 05:55:48 PM PDT 24
Peak memory 201972 kb
Host smart-eb5afcdd-ec90-48b6-b09c-740e7171b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735836199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1735836199
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2837261828
Short name T548
Test name
Test status
Simulation time 3345850447 ps
CPU time 7.89 seconds
Started Jun 23 05:55:43 PM PDT 24
Finished Jun 23 05:55:51 PM PDT 24
Peak memory 202240 kb
Host smart-6fb51b4c-8a6c-48b9-84a4-3914cd89c966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837261828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2837261828
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2589853454
Short name T736
Test name
Test status
Simulation time 6139097272 ps
CPU time 1.75 seconds
Started Jun 23 05:55:39 PM PDT 24
Finished Jun 23 05:55:42 PM PDT 24
Peak memory 202016 kb
Host smart-a195e3e0-fb5c-42a0-8826-a11cbc1d6021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589853454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2589853454
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1466656806
Short name T267
Test name
Test status
Simulation time 335914874931 ps
CPU time 108.78 seconds
Started Jun 23 05:55:43 PM PDT 24
Finished Jun 23 05:57:33 PM PDT 24
Peak memory 202504 kb
Host smart-bf7da8be-1449-4289-8a3b-9e2ff0c3423a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466656806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1466656806
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.830988403
Short name T325
Test name
Test status
Simulation time 183843848445 ps
CPU time 183.63 seconds
Started Jun 23 05:55:46 PM PDT 24
Finished Jun 23 05:58:50 PM PDT 24
Peak memory 210916 kb
Host smart-5cabfcfc-48e1-4395-967f-b7a7d210b148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830988403 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.830988403
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.984411755
Short name T713
Test name
Test status
Simulation time 447331578 ps
CPU time 1.65 seconds
Started Jun 23 05:55:45 PM PDT 24
Finished Jun 23 05:55:47 PM PDT 24
Peak memory 201904 kb
Host smart-b15f41e1-b623-4c4e-9b70-76d9e05801ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984411755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.984411755
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.4114789953
Short name T218
Test name
Test status
Simulation time 519492244316 ps
CPU time 324.58 seconds
Started Jun 23 05:55:47 PM PDT 24
Finished Jun 23 06:01:13 PM PDT 24
Peak memory 202252 kb
Host smart-079b5954-3197-4cf1-b8c4-53c2ffd3b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114789953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4114789953
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1832208384
Short name T250
Test name
Test status
Simulation time 494963482704 ps
CPU time 1078.37 seconds
Started Jun 23 05:55:46 PM PDT 24
Finished Jun 23 06:13:45 PM PDT 24
Peak memory 202272 kb
Host smart-ee02b8c5-d692-4496-b2ae-679e824392ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832208384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1832208384
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3351278524
Short name T651
Test name
Test status
Simulation time 485495768763 ps
CPU time 307.74 seconds
Started Jun 23 05:55:48 PM PDT 24
Finished Jun 23 06:00:57 PM PDT 24
Peak memory 202216 kb
Host smart-ec25f5d7-9b05-4870-9c28-2ea88590c91b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351278524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3351278524
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.665786153
Short name T143
Test name
Test status
Simulation time 326883783488 ps
CPU time 692.5 seconds
Started Jun 23 05:55:47 PM PDT 24
Finished Jun 23 06:07:20 PM PDT 24
Peak memory 202336 kb
Host smart-fbd08ffe-54ad-4e2d-b33d-4b5440b4178c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665786153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.665786153
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.673569650
Short name T581
Test name
Test status
Simulation time 166927707044 ps
CPU time 311.56 seconds
Started Jun 23 05:55:46 PM PDT 24
Finished Jun 23 06:00:59 PM PDT 24
Peak memory 202212 kb
Host smart-c34f59c9-9553-4239-a5bf-5f1679094842
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=673569650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.673569650
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3610252726
Short name T127
Test name
Test status
Simulation time 588610555329 ps
CPU time 1366.71 seconds
Started Jun 23 05:55:48 PM PDT 24
Finished Jun 23 06:18:36 PM PDT 24
Peak memory 202252 kb
Host smart-76f54b3d-1e22-4c05-a08a-051868cb37af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610252726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3610252726
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.150190334
Short name T764
Test name
Test status
Simulation time 406505913924 ps
CPU time 470.94 seconds
Started Jun 23 05:55:50 PM PDT 24
Finished Jun 23 06:03:42 PM PDT 24
Peak memory 202240 kb
Host smart-20b27873-e2fa-4491-9d6f-c79378361bc4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150190334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.150190334
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3401355842
Short name T411
Test name
Test status
Simulation time 45754607543 ps
CPU time 29.26 seconds
Started Jun 23 05:55:50 PM PDT 24
Finished Jun 23 05:56:19 PM PDT 24
Peak memory 202092 kb
Host smart-f49b5a67-16c8-4c44-bc26-db3f5ac1922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401355842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3401355842
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.629444733
Short name T637
Test name
Test status
Simulation time 2955394723 ps
CPU time 7.65 seconds
Started Jun 23 05:55:44 PM PDT 24
Finished Jun 23 05:55:52 PM PDT 24
Peak memory 202076 kb
Host smart-9d5d50bb-be82-44a1-8480-8fff8880ebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629444733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.629444733
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.654136692
Short name T692
Test name
Test status
Simulation time 5803635888 ps
CPU time 4.31 seconds
Started Jun 23 05:55:44 PM PDT 24
Finished Jun 23 05:55:49 PM PDT 24
Peak memory 202072 kb
Host smart-5f015ac5-be9e-4b98-9e31-86e5a7b04445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654136692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.654136692
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1712479403
Short name T264
Test name
Test status
Simulation time 247317474165 ps
CPU time 364.82 seconds
Started Jun 23 05:55:43 PM PDT 24
Finished Jun 23 06:01:48 PM PDT 24
Peak memory 202188 kb
Host smart-f5cf146e-a69a-4854-ad81-31d0d4b1098e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712479403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1712479403
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1180025896
Short name T715
Test name
Test status
Simulation time 217964441710 ps
CPU time 125.85 seconds
Started Jun 23 05:55:48 PM PDT 24
Finished Jun 23 05:57:55 PM PDT 24
Peak memory 211592 kb
Host smart-d0b07a75-f34c-4cef-9402-55f89e7544d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180025896 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1180025896
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2435683123
Short name T711
Test name
Test status
Simulation time 321952325 ps
CPU time 1.31 seconds
Started Jun 23 05:55:47 PM PDT 24
Finished Jun 23 05:55:49 PM PDT 24
Peak memory 201952 kb
Host smart-e653db19-0919-430e-b6b5-01a7dd8ef05a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435683123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2435683123
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.143550135
Short name T699
Test name
Test status
Simulation time 324484909057 ps
CPU time 723.35 seconds
Started Jun 23 05:55:48 PM PDT 24
Finished Jun 23 06:07:52 PM PDT 24
Peak memory 202216 kb
Host smart-4690c470-4537-4db9-a28b-924ca1632a45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143550135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.143550135
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3430003548
Short name T440
Test name
Test status
Simulation time 331840735837 ps
CPU time 698.77 seconds
Started Jun 23 05:55:48 PM PDT 24
Finished Jun 23 06:07:27 PM PDT 24
Peak memory 202284 kb
Host smart-f11739c8-be9a-47dc-80fe-7b8fbbab3272
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430003548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3430003548
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.949471224
Short name T413
Test name
Test status
Simulation time 162033622330 ps
CPU time 316.97 seconds
Started Jun 23 05:55:47 PM PDT 24
Finished Jun 23 06:01:04 PM PDT 24
Peak memory 202204 kb
Host smart-8710187f-ae27-468a-aae0-6dd125dfc5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949471224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.949471224
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1362843017
Short name T383
Test name
Test status
Simulation time 326358544558 ps
CPU time 189.81 seconds
Started Jun 23 05:55:46 PM PDT 24
Finished Jun 23 05:58:57 PM PDT 24
Peak memory 202192 kb
Host smart-265e835c-53da-4d4b-ac58-062202e1c822
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362843017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1362843017
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3176520452
Short name T220
Test name
Test status
Simulation time 184864341585 ps
CPU time 303.87 seconds
Started Jun 23 05:55:47 PM PDT 24
Finished Jun 23 06:00:52 PM PDT 24
Peak memory 202296 kb
Host smart-9618b97a-624e-461a-922d-c6d48e2abc28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176520452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3176520452
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3731159073
Short name T468
Test name
Test status
Simulation time 195349158195 ps
CPU time 434.94 seconds
Started Jun 23 05:55:46 PM PDT 24
Finished Jun 23 06:03:01 PM PDT 24
Peak memory 202244 kb
Host smart-a14fd4a5-6386-497a-8331-9cee61cdc703
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731159073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3731159073
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3686261272
Short name T668
Test name
Test status
Simulation time 117791990260 ps
CPU time 539.5 seconds
Started Jun 23 05:55:51 PM PDT 24
Finished Jun 23 06:04:51 PM PDT 24
Peak memory 202784 kb
Host smart-7638a8bc-f840-4067-af5b-15d1cf72aa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686261272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3686261272
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3066594310
Short name T463
Test name
Test status
Simulation time 32719888062 ps
CPU time 17.69 seconds
Started Jun 23 05:55:51 PM PDT 24
Finished Jun 23 05:56:09 PM PDT 24
Peak memory 202044 kb
Host smart-b662f57a-f22c-4a53-9d95-57ef312f48dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066594310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3066594310
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3590219152
Short name T542
Test name
Test status
Simulation time 4126484535 ps
CPU time 3.13 seconds
Started Jun 23 05:55:47 PM PDT 24
Finished Jun 23 05:55:51 PM PDT 24
Peak memory 202076 kb
Host smart-8d769ca2-74a8-42bb-a9d3-4f2285b4f5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590219152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3590219152
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1242467550
Short name T357
Test name
Test status
Simulation time 5828567812 ps
CPU time 5.18 seconds
Started Jun 23 05:55:44 PM PDT 24
Finished Jun 23 05:55:49 PM PDT 24
Peak memory 202044 kb
Host smart-14affd21-465f-4954-bca0-a83f0cb94230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242467550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1242467550
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3063659748
Short name T680
Test name
Test status
Simulation time 749717341052 ps
CPU time 868.7 seconds
Started Jun 23 05:55:53 PM PDT 24
Finished Jun 23 06:10:22 PM PDT 24
Peak memory 213968 kb
Host smart-58126e1c-6b40-4cfa-a7a4-234c5392df8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063659748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3063659748
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3076663896
Short name T300
Test name
Test status
Simulation time 164390808685 ps
CPU time 282.82 seconds
Started Jun 23 05:55:50 PM PDT 24
Finished Jun 23 06:00:33 PM PDT 24
Peak memory 202332 kb
Host smart-0bf4178f-5b8f-4d60-85c6-eb1cf7355b11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076663896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3076663896
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3069446752
Short name T290
Test name
Test status
Simulation time 348514950838 ps
CPU time 208.45 seconds
Started Jun 23 05:55:50 PM PDT 24
Finished Jun 23 05:59:19 PM PDT 24
Peak memory 202256 kb
Host smart-c86e2f69-a451-42ae-aa55-eebe0278c3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069446752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3069446752
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.927836425
Short name T200
Test name
Test status
Simulation time 482428453081 ps
CPU time 706.78 seconds
Started Jun 23 05:55:52 PM PDT 24
Finished Jun 23 06:07:39 PM PDT 24
Peak memory 202324 kb
Host smart-d1b83587-f19b-4cb6-975d-125fc91ed755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927836425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.927836425
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2650943321
Short name T495
Test name
Test status
Simulation time 332510172322 ps
CPU time 826.89 seconds
Started Jun 23 05:55:50 PM PDT 24
Finished Jun 23 06:09:37 PM PDT 24
Peak memory 202200 kb
Host smart-ff24547d-f8d9-481c-ac67-26db19a25dda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650943321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2650943321
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3895081100
Short name T709
Test name
Test status
Simulation time 330164512137 ps
CPU time 79.45 seconds
Started Jun 23 05:55:51 PM PDT 24
Finished Jun 23 05:57:11 PM PDT 24
Peak memory 202268 kb
Host smart-717d3e59-740c-495b-a53d-d3216e133f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895081100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3895081100
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1562368922
Short name T445
Test name
Test status
Simulation time 334678024833 ps
CPU time 97.75 seconds
Started Jun 23 05:55:53 PM PDT 24
Finished Jun 23 05:57:31 PM PDT 24
Peak memory 202140 kb
Host smart-060b3ace-246d-4731-b4fb-10abc5afd26f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562368922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1562368922
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.630273102
Short name T734
Test name
Test status
Simulation time 400310042736 ps
CPU time 878.57 seconds
Started Jun 23 05:55:53 PM PDT 24
Finished Jun 23 06:10:32 PM PDT 24
Peak memory 202204 kb
Host smart-98ec2fe4-c3cb-4050-8e0a-fc420f65396c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630273102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.630273102
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1461195273
Short name T38
Test name
Test status
Simulation time 138831587866 ps
CPU time 697.76 seconds
Started Jun 23 05:55:52 PM PDT 24
Finished Jun 23 06:07:31 PM PDT 24
Peak memory 202556 kb
Host smart-4fbb9c1f-c565-493c-a79f-f1664e5034bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461195273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1461195273
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1011625190
Short name T735
Test name
Test status
Simulation time 24937454681 ps
CPU time 31.08 seconds
Started Jun 23 05:55:53 PM PDT 24
Finished Jun 23 05:56:25 PM PDT 24
Peak memory 201928 kb
Host smart-95468e8b-ac37-4263-ad8a-1ec8bd25b501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011625190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1011625190
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.803038963
Short name T385
Test name
Test status
Simulation time 4215923241 ps
CPU time 3.91 seconds
Started Jun 23 05:55:51 PM PDT 24
Finished Jun 23 05:55:55 PM PDT 24
Peak memory 202044 kb
Host smart-a1d6f68e-20a6-4ef6-b3a5-a1193d2f41a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803038963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.803038963
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.37035916
Short name T654
Test name
Test status
Simulation time 5591633940 ps
CPU time 12.1 seconds
Started Jun 23 05:55:48 PM PDT 24
Finished Jun 23 05:56:01 PM PDT 24
Peak memory 202116 kb
Host smart-2fb85f56-19f3-4f7d-9223-cd5a5042f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37035916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.37035916
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3445726784
Short name T215
Test name
Test status
Simulation time 367898454483 ps
CPU time 225.07 seconds
Started Jun 23 05:55:53 PM PDT 24
Finished Jun 23 05:59:38 PM PDT 24
Peak memory 202296 kb
Host smart-b21b2c59-50be-4efb-8811-349d43b1bbb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445726784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3445726784
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.210210131
Short name T744
Test name
Test status
Simulation time 250400615553 ps
CPU time 83.51 seconds
Started Jun 23 05:55:48 PM PDT 24
Finished Jun 23 05:57:12 PM PDT 24
Peak memory 202416 kb
Host smart-cf598983-e924-4492-96a8-22863a8e9331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210210131 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.210210131
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2550546574
Short name T457
Test name
Test status
Simulation time 467328394 ps
CPU time 1.66 seconds
Started Jun 23 05:55:56 PM PDT 24
Finished Jun 23 05:55:58 PM PDT 24
Peak memory 201912 kb
Host smart-25ab4510-582d-4c86-831d-33123dc123fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550546574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2550546574
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1219767670
Short name T262
Test name
Test status
Simulation time 527844042224 ps
CPU time 163.85 seconds
Started Jun 23 05:55:56 PM PDT 24
Finished Jun 23 05:58:40 PM PDT 24
Peak memory 202324 kb
Host smart-4a3a663d-8810-477a-ba76-8b6c91411bc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219767670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1219767670
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.4081248953
Short name T795
Test name
Test status
Simulation time 167358694119 ps
CPU time 63.96 seconds
Started Jun 23 05:55:54 PM PDT 24
Finished Jun 23 05:56:58 PM PDT 24
Peak memory 202176 kb
Host smart-ec0fc7b6-a390-46a2-8e75-8e4cf41fca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081248953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4081248953
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1042823794
Short name T539
Test name
Test status
Simulation time 486261028141 ps
CPU time 308.06 seconds
Started Jun 23 05:55:48 PM PDT 24
Finished Jun 23 06:00:57 PM PDT 24
Peak memory 202252 kb
Host smart-3aed894a-1bc7-4f49-9c8b-214f899f14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042823794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1042823794
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.611941484
Short name T633
Test name
Test status
Simulation time 162745874637 ps
CPU time 180.79 seconds
Started Jun 23 05:55:53 PM PDT 24
Finished Jun 23 05:58:54 PM PDT 24
Peak memory 202188 kb
Host smart-c9f213c9-d665-4335-aa0c-a7af7df1fa5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=611941484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.611941484
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1862932297
Short name T530
Test name
Test status
Simulation time 164560099230 ps
CPU time 380.26 seconds
Started Jun 23 05:55:51 PM PDT 24
Finished Jun 23 06:02:12 PM PDT 24
Peak memory 202320 kb
Host smart-479eaf8e-2447-42c6-b2c9-3b0bf6eb74fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862932297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1862932297
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.610466288
Short name T381
Test name
Test status
Simulation time 163526151490 ps
CPU time 343.03 seconds
Started Jun 23 05:55:52 PM PDT 24
Finished Jun 23 06:01:36 PM PDT 24
Peak memory 202236 kb
Host smart-b0a81de4-37c1-4091-8c1b-13d0ef589e19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=610466288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.610466288
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.247489015
Short name T561
Test name
Test status
Simulation time 547005521177 ps
CPU time 1121.85 seconds
Started Jun 23 05:55:54 PM PDT 24
Finished Jun 23 06:14:36 PM PDT 24
Peak memory 202304 kb
Host smart-b085d910-a1ec-437f-b77c-382700713202
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247489015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.247489015
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1326574181
Short name T763
Test name
Test status
Simulation time 207031584091 ps
CPU time 487.72 seconds
Started Jun 23 05:55:55 PM PDT 24
Finished Jun 23 06:04:03 PM PDT 24
Peak memory 202236 kb
Host smart-e86c7735-5b89-4c09-b487-9cd9bfd84f38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326574181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1326574181
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2420591259
Short name T460
Test name
Test status
Simulation time 114665247330 ps
CPU time 633.35 seconds
Started Jun 23 05:55:56 PM PDT 24
Finished Jun 23 06:06:30 PM PDT 24
Peak memory 202640 kb
Host smart-d46a0571-f776-44a6-899d-6c52858001a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420591259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2420591259
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1206917544
Short name T788
Test name
Test status
Simulation time 32721656800 ps
CPU time 20.38 seconds
Started Jun 23 05:55:58 PM PDT 24
Finished Jun 23 05:56:19 PM PDT 24
Peak memory 202036 kb
Host smart-29c45295-05f4-45f4-8b8a-20794ee9cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206917544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1206917544
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.128275878
Short name T579
Test name
Test status
Simulation time 4833939335 ps
CPU time 7.89 seconds
Started Jun 23 05:55:56 PM PDT 24
Finished Jun 23 05:56:04 PM PDT 24
Peak memory 202072 kb
Host smart-0bbe582b-9845-4599-aac5-7d2169969db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128275878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.128275878
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3329293947
Short name T675
Test name
Test status
Simulation time 5980628698 ps
CPU time 2.57 seconds
Started Jun 23 05:55:52 PM PDT 24
Finished Jun 23 05:55:55 PM PDT 24
Peak memory 202060 kb
Host smart-b061930d-2fdb-411e-8363-6303aae11f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329293947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3329293947
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.424164332
Short name T28
Test name
Test status
Simulation time 128297426004 ps
CPU time 36.6 seconds
Started Jun 23 05:55:56 PM PDT 24
Finished Jun 23 05:56:33 PM PDT 24
Peak memory 210556 kb
Host smart-332167ef-2586-4842-9123-269846405c20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424164332 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.424164332
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3937462354
Short name T737
Test name
Test status
Simulation time 397821646 ps
CPU time 0.82 seconds
Started Jun 23 05:56:01 PM PDT 24
Finished Jun 23 05:56:02 PM PDT 24
Peak memory 201960 kb
Host smart-09eb982c-6a4d-41cb-84e4-be957179cc45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937462354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3937462354
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4225498621
Short name T646
Test name
Test status
Simulation time 318656880514 ps
CPU time 698.38 seconds
Started Jun 23 05:55:55 PM PDT 24
Finished Jun 23 06:07:34 PM PDT 24
Peak memory 202204 kb
Host smart-7941cf3f-c3dd-41d0-9e9b-364965232dbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225498621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4225498621
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3726976945
Short name T166
Test name
Test status
Simulation time 332069131389 ps
CPU time 130.54 seconds
Started Jun 23 05:55:55 PM PDT 24
Finished Jun 23 05:58:06 PM PDT 24
Peak memory 202404 kb
Host smart-d8045e05-ed42-4765-81f3-c8ab267df643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726976945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3726976945
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.9841438
Short name T644
Test name
Test status
Simulation time 323707410796 ps
CPU time 208.93 seconds
Started Jun 23 05:55:55 PM PDT 24
Finished Jun 23 05:59:24 PM PDT 24
Peak memory 202236 kb
Host smart-3f8da3c3-dc1a-48de-be51-41e31e89aa4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=9841438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_
fixed.9841438
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4031479585
Short name T412
Test name
Test status
Simulation time 329628995396 ps
CPU time 394.97 seconds
Started Jun 23 05:55:54 PM PDT 24
Finished Jun 23 06:02:29 PM PDT 24
Peak memory 202304 kb
Host smart-f431f34b-8ae4-43be-9b03-44b2f2e81818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031479585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4031479585
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.408593139
Short name T389
Test name
Test status
Simulation time 489733087827 ps
CPU time 392.75 seconds
Started Jun 23 05:55:55 PM PDT 24
Finished Jun 23 06:02:29 PM PDT 24
Peak memory 202252 kb
Host smart-6bfe7fba-4ade-4bd9-a85f-14c56484bcea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=408593139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.408593139
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3350335940
Short name T69
Test name
Test status
Simulation time 349743300304 ps
CPU time 412.18 seconds
Started Jun 23 05:55:57 PM PDT 24
Finished Jun 23 06:02:49 PM PDT 24
Peak memory 202332 kb
Host smart-bd3a5864-4dc1-48e4-bb09-a845eeb9140e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350335940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3350335940
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1354528013
Short name T756
Test name
Test status
Simulation time 383432996176 ps
CPU time 548.48 seconds
Started Jun 23 05:55:58 PM PDT 24
Finished Jun 23 06:05:07 PM PDT 24
Peak memory 202312 kb
Host smart-6f0dd9ac-0836-4bf1-aa7c-422a0e391bca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354528013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1354528013
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3183808616
Short name T789
Test name
Test status
Simulation time 41382423401 ps
CPU time 21.7 seconds
Started Jun 23 05:56:03 PM PDT 24
Finished Jun 23 05:56:25 PM PDT 24
Peak memory 202092 kb
Host smart-1481d8e7-8285-4295-bf5e-a09abc3640b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183808616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3183808616
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.111333395
Short name T477
Test name
Test status
Simulation time 5359864980 ps
CPU time 12.48 seconds
Started Jun 23 05:55:58 PM PDT 24
Finished Jun 23 05:56:11 PM PDT 24
Peak memory 202032 kb
Host smart-eeb161ac-5c87-4f8f-b437-1efe853dc3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111333395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.111333395
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.915639019
Short name T496
Test name
Test status
Simulation time 5924792426 ps
CPU time 3.87 seconds
Started Jun 23 05:55:56 PM PDT 24
Finished Jun 23 05:56:00 PM PDT 24
Peak memory 202060 kb
Host smart-6985c482-25d7-447b-acf7-8d1cb49c9e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915639019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.915639019
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.141076924
Short name T778
Test name
Test status
Simulation time 168957488576 ps
CPU time 202.35 seconds
Started Jun 23 05:56:04 PM PDT 24
Finished Jun 23 05:59:27 PM PDT 24
Peak memory 202168 kb
Host smart-38bf1b5e-aab6-4790-898e-eec06c27e868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141076924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
141076924
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.726177364
Short name T244
Test name
Test status
Simulation time 266513942911 ps
CPU time 51.13 seconds
Started Jun 23 05:56:00 PM PDT 24
Finished Jun 23 05:56:51 PM PDT 24
Peak memory 211660 kb
Host smart-faf7da3e-99ce-4c42-b599-bd8b4bb1245c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726177364 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.726177364
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3689586626
Short name T379
Test name
Test status
Simulation time 531429867 ps
CPU time 0.95 seconds
Started Jun 23 05:56:04 PM PDT 24
Finished Jun 23 05:56:06 PM PDT 24
Peak memory 201960 kb
Host smart-e1f01177-aca5-46d5-9473-cb0f387da1c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689586626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3689586626
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.215107196
Short name T158
Test name
Test status
Simulation time 326215770624 ps
CPU time 70.13 seconds
Started Jun 23 05:55:59 PM PDT 24
Finished Jun 23 05:57:10 PM PDT 24
Peak memory 202204 kb
Host smart-d0fd93ce-adb8-4ec2-aa7e-ea04fe33b1dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215107196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.215107196
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2124340760
Short name T75
Test name
Test status
Simulation time 168071787289 ps
CPU time 414.51 seconds
Started Jun 23 05:56:02 PM PDT 24
Finished Jun 23 06:02:57 PM PDT 24
Peak memory 202336 kb
Host smart-25a38555-5e1f-4b6b-8d73-3c6b5abc87a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124340760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2124340760
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3904813786
Short name T157
Test name
Test status
Simulation time 163139954696 ps
CPU time 395.08 seconds
Started Jun 23 05:55:59 PM PDT 24
Finished Jun 23 06:02:34 PM PDT 24
Peak memory 202260 kb
Host smart-93b97cc2-1943-45e9-84b1-d3af458f2b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904813786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3904813786
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.566377846
Short name T547
Test name
Test status
Simulation time 169125368089 ps
CPU time 421.64 seconds
Started Jun 23 05:55:59 PM PDT 24
Finished Jun 23 06:03:01 PM PDT 24
Peak memory 202224 kb
Host smart-9c70c420-39ac-442b-8a80-a94725b3ae34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=566377846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.566377846
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3756509804
Short name T232
Test name
Test status
Simulation time 166176254038 ps
CPU time 224.41 seconds
Started Jun 23 05:56:04 PM PDT 24
Finished Jun 23 05:59:48 PM PDT 24
Peak memory 202188 kb
Host smart-50a2cc43-550b-404e-b843-c7b4d9f65b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756509804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3756509804
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2204092446
Short name T757
Test name
Test status
Simulation time 338118419676 ps
CPU time 391.27 seconds
Started Jun 23 05:55:57 PM PDT 24
Finished Jun 23 06:02:28 PM PDT 24
Peak memory 202296 kb
Host smart-0924d466-dc80-497a-b2f1-1d57cd3cd4f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204092446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2204092446
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2968239413
Short name T123
Test name
Test status
Simulation time 382568966961 ps
CPU time 880.59 seconds
Started Jun 23 05:56:00 PM PDT 24
Finished Jun 23 06:10:41 PM PDT 24
Peak memory 202324 kb
Host smart-c9094ecb-fbc7-4ace-a17f-613f9fb59a0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968239413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2968239413
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.615451473
Short name T320
Test name
Test status
Simulation time 403757072623 ps
CPU time 826.54 seconds
Started Jun 23 05:56:00 PM PDT 24
Finished Jun 23 06:09:47 PM PDT 24
Peak memory 202308 kb
Host smart-8f482fd4-bc2d-45e8-9507-af3f0d8a55b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615451473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.615451473
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4255860070
Short name T195
Test name
Test status
Simulation time 109322054211 ps
CPU time 399.61 seconds
Started Jun 23 05:56:04 PM PDT 24
Finished Jun 23 06:02:44 PM PDT 24
Peak memory 202512 kb
Host smart-7489f072-9b3c-43d4-a9cc-3c1a2a43e76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255860070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4255860070
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3026041961
Short name T783
Test name
Test status
Simulation time 22792902384 ps
CPU time 13.99 seconds
Started Jun 23 05:56:00 PM PDT 24
Finished Jun 23 05:56:14 PM PDT 24
Peak memory 202104 kb
Host smart-9ddfdd80-90da-4b98-9342-9ec1a4703d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026041961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3026041961
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1245721699
Short name T456
Test name
Test status
Simulation time 2907401139 ps
CPU time 2.43 seconds
Started Jun 23 05:56:01 PM PDT 24
Finished Jun 23 05:56:04 PM PDT 24
Peak memory 202056 kb
Host smart-0baff3c4-a7aa-47ae-9a28-6d064f3f1da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245721699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1245721699
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1197588296
Short name T567
Test name
Test status
Simulation time 6029416400 ps
CPU time 3.67 seconds
Started Jun 23 05:56:03 PM PDT 24
Finished Jun 23 05:56:07 PM PDT 24
Peak memory 202060 kb
Host smart-ba402f0a-d477-4139-b8df-e4eeb86ddcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197588296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1197588296
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2780119012
Short name T447
Test name
Test status
Simulation time 119950253963 ps
CPU time 417.78 seconds
Started Jun 23 05:56:01 PM PDT 24
Finished Jun 23 06:02:59 PM PDT 24
Peak memory 202596 kb
Host smart-0198a0ad-9ef1-4fd1-8898-8309ba4235ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780119012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2780119012
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3970189225
Short name T201
Test name
Test status
Simulation time 119622300257 ps
CPU time 167.83 seconds
Started Jun 23 05:56:03 PM PDT 24
Finished Jun 23 05:58:51 PM PDT 24
Peak memory 210964 kb
Host smart-e3a9febd-3cdf-46cc-bf6e-11123c868494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970189225 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3970189225
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.166882137
Short name T759
Test name
Test status
Simulation time 320845288 ps
CPU time 1.01 seconds
Started Jun 23 05:55:04 PM PDT 24
Finished Jun 23 05:55:05 PM PDT 24
Peak memory 201904 kb
Host smart-9abc1dcb-8c1b-43b0-b7b7-ef2f0ac7bade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166882137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.166882137
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3314536297
Short name T298
Test name
Test status
Simulation time 344579368325 ps
CPU time 737.93 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 06:07:22 PM PDT 24
Peak memory 202272 kb
Host smart-a1bb460a-5fcd-43dd-a4e1-0285283aee15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314536297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3314536297
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1340047814
Short name T515
Test name
Test status
Simulation time 324273572903 ps
CPU time 746.81 seconds
Started Jun 23 05:55:07 PM PDT 24
Finished Jun 23 06:07:35 PM PDT 24
Peak memory 202356 kb
Host smart-5b040746-861b-4f02-9b7c-63cd79ec6580
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340047814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1340047814
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.826401825
Short name T643
Test name
Test status
Simulation time 168363835734 ps
CPU time 193.59 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 05:58:17 PM PDT 24
Peak memory 202288 kb
Host smart-d3757429-f7a6-4488-82dd-bf6d19f777f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826401825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.826401825
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2276312855
Short name T670
Test name
Test status
Simulation time 163094071355 ps
CPU time 276.4 seconds
Started Jun 23 05:55:02 PM PDT 24
Finished Jun 23 05:59:39 PM PDT 24
Peak memory 202216 kb
Host smart-eec0f2f0-2a03-4419-b272-9060ff554e6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276312855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2276312855
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2510366333
Short name T794
Test name
Test status
Simulation time 397453202191 ps
CPU time 918.74 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 06:10:23 PM PDT 24
Peak memory 202232 kb
Host smart-37090be0-383e-4e79-85b7-e063e42b8cb6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510366333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2510366333
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.4094905520
Short name T508
Test name
Test status
Simulation time 409807572327 ps
CPU time 96.29 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 05:56:39 PM PDT 24
Peak memory 202312 kb
Host smart-352b9cad-f6f2-4c3a-af9e-820eef255fdb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094905520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.4094905520
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.723329474
Short name T564
Test name
Test status
Simulation time 91343386423 ps
CPU time 405.51 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 06:01:49 PM PDT 24
Peak memory 202592 kb
Host smart-22b5d4ce-5103-4a07-ac53-6a08e2d2d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723329474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.723329474
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1703061076
Short name T549
Test name
Test status
Simulation time 24712057002 ps
CPU time 46.17 seconds
Started Jun 23 05:55:02 PM PDT 24
Finished Jun 23 05:55:49 PM PDT 24
Peak memory 202052 kb
Host smart-dd57216e-169e-4b18-907a-f5f111b31d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703061076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1703061076
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.721057557
Short name T605
Test name
Test status
Simulation time 4156835172 ps
CPU time 11.14 seconds
Started Jun 23 05:55:04 PM PDT 24
Finished Jun 23 05:55:15 PM PDT 24
Peak memory 202000 kb
Host smart-bc012ac3-9c3d-4c1e-8023-d0166f5dd4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721057557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.721057557
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2571229319
Short name T499
Test name
Test status
Simulation time 6044437768 ps
CPU time 4.34 seconds
Started Jun 23 05:54:59 PM PDT 24
Finished Jun 23 05:55:04 PM PDT 24
Peak memory 202016 kb
Host smart-95b4c56e-25b3-40c9-a3d2-aea5f2cc7a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571229319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2571229319
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3321626890
Short name T268
Test name
Test status
Simulation time 340174680942 ps
CPU time 790.09 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 06:08:14 PM PDT 24
Peak memory 202332 kb
Host smart-2fa4752e-70e1-4f82-8cc4-d4dec4c628c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321626890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3321626890
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.4216876641
Short name T247
Test name
Test status
Simulation time 54898674642 ps
CPU time 65.48 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 05:56:09 PM PDT 24
Peak memory 210596 kb
Host smart-1e7d4704-f621-4fb5-bd3f-03e4b5a93b3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216876641 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.4216876641
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3486112728
Short name T358
Test name
Test status
Simulation time 279198496 ps
CPU time 1.23 seconds
Started Jun 23 05:56:04 PM PDT 24
Finished Jun 23 05:56:05 PM PDT 24
Peak memory 201956 kb
Host smart-96585e19-9c93-4312-b5a9-8ff2842f8d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486112728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3486112728
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3937806725
Short name T599
Test name
Test status
Simulation time 344304969506 ps
CPU time 769.16 seconds
Started Jun 23 05:56:08 PM PDT 24
Finished Jun 23 06:08:58 PM PDT 24
Peak memory 202256 kb
Host smart-83865547-1269-4731-9358-51678b300d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937806725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3937806725
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2311600699
Short name T254
Test name
Test status
Simulation time 159339655529 ps
CPU time 132.71 seconds
Started Jun 23 05:56:06 PM PDT 24
Finished Jun 23 05:58:19 PM PDT 24
Peak memory 202148 kb
Host smart-05137374-340e-4d8a-8191-5acc4631e333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311600699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2311600699
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3917390928
Short name T537
Test name
Test status
Simulation time 321863902846 ps
CPU time 793.97 seconds
Started Jun 23 05:56:07 PM PDT 24
Finished Jun 23 06:09:21 PM PDT 24
Peak memory 202216 kb
Host smart-54662132-e7e3-4f2e-84d8-a0dc192e8d15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917390928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3917390928
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.836005590
Short name T431
Test name
Test status
Simulation time 169001075553 ps
CPU time 405.79 seconds
Started Jun 23 05:56:07 PM PDT 24
Finished Jun 23 06:02:53 PM PDT 24
Peak memory 202264 kb
Host smart-1dacde1c-59e9-4355-a0d0-395412fe5b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836005590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.836005590
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1155506864
Short name T563
Test name
Test status
Simulation time 486983702627 ps
CPU time 268.5 seconds
Started Jun 23 05:56:06 PM PDT 24
Finished Jun 23 06:00:34 PM PDT 24
Peak memory 202312 kb
Host smart-1961690f-d927-43b6-95ee-a86fd5411464
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155506864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1155506864
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2776606929
Short name T165
Test name
Test status
Simulation time 366672000931 ps
CPU time 96.57 seconds
Started Jun 23 05:56:07 PM PDT 24
Finished Jun 23 05:57:44 PM PDT 24
Peak memory 202192 kb
Host smart-69a8bd90-2d18-450e-aad8-fc0211d1077f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776606929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2776606929
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3935547139
Short name T550
Test name
Test status
Simulation time 379441477163 ps
CPU time 288.65 seconds
Started Jun 23 05:56:07 PM PDT 24
Finished Jun 23 06:00:56 PM PDT 24
Peak memory 202200 kb
Host smart-89dd28e1-0c18-4809-b7ea-ff61d549bd34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935547139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3935547139
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.4114485353
Short name T436
Test name
Test status
Simulation time 35671935690 ps
CPU time 78.81 seconds
Started Jun 23 05:56:06 PM PDT 24
Finished Jun 23 05:57:26 PM PDT 24
Peak memory 202244 kb
Host smart-b7fcebd1-f518-4ba9-9060-9cc06477ee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114485353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.4114485353
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2756863511
Short name T706
Test name
Test status
Simulation time 3738612360 ps
CPU time 2.76 seconds
Started Jun 23 05:56:07 PM PDT 24
Finished Jun 23 05:56:10 PM PDT 24
Peak memory 202040 kb
Host smart-db93651a-f915-4e45-b12f-c606ab96b2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756863511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2756863511
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2458970658
Short name T439
Test name
Test status
Simulation time 5698157332 ps
CPU time 13.83 seconds
Started Jun 23 05:56:02 PM PDT 24
Finished Jun 23 05:56:16 PM PDT 24
Peak memory 201976 kb
Host smart-9a6862ea-0bd7-4215-9b36-edf308f60705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458970658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2458970658
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3560397516
Short name T276
Test name
Test status
Simulation time 1689732429420 ps
CPU time 1200.08 seconds
Started Jun 23 05:56:08 PM PDT 24
Finished Jun 23 06:16:09 PM PDT 24
Peak memory 213376 kb
Host smart-8edea0cf-7112-4194-a306-621b08419daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560397516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3560397516
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.85197642
Short name T30
Test name
Test status
Simulation time 105733627495 ps
CPU time 93.81 seconds
Started Jun 23 05:56:05 PM PDT 24
Finished Jun 23 05:57:39 PM PDT 24
Peak memory 210612 kb
Host smart-232b3b1a-51bc-493a-8228-a84c8bcf9581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85197642 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.85197642
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1204296886
Short name T589
Test name
Test status
Simulation time 476487292 ps
CPU time 1.17 seconds
Started Jun 23 05:56:10 PM PDT 24
Finished Jun 23 05:56:12 PM PDT 24
Peak memory 201928 kb
Host smart-0837d7dd-b309-46f3-a0cf-1c4fa285588b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204296886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1204296886
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1168577373
Short name T602
Test name
Test status
Simulation time 163855261121 ps
CPU time 388.83 seconds
Started Jun 23 05:56:03 PM PDT 24
Finished Jun 23 06:02:33 PM PDT 24
Peak memory 202252 kb
Host smart-7530588d-0110-4913-9e72-69c2fd97a6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168577373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1168577373
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3398372520
Short name T449
Test name
Test status
Simulation time 158841907454 ps
CPU time 123.22 seconds
Started Jun 23 05:56:07 PM PDT 24
Finished Jun 23 05:58:11 PM PDT 24
Peak memory 202216 kb
Host smart-951784ec-52ed-4331-a237-6043b1ac76bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398372520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3398372520
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.732278791
Short name T151
Test name
Test status
Simulation time 328090640473 ps
CPU time 44.63 seconds
Started Jun 23 05:56:06 PM PDT 24
Finished Jun 23 05:56:51 PM PDT 24
Peak memory 202264 kb
Host smart-fcd5ea56-7dd4-4c23-9a74-89e5e104212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732278791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.732278791
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2506183267
Short name T674
Test name
Test status
Simulation time 484484277664 ps
CPU time 133.36 seconds
Started Jun 23 05:56:03 PM PDT 24
Finished Jun 23 05:58:17 PM PDT 24
Peak memory 202232 kb
Host smart-f71331cf-ad7f-4b3d-8bbc-6d73d385bc98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506183267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2506183267
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.418363763
Short name T755
Test name
Test status
Simulation time 192827902274 ps
CPU time 110.53 seconds
Started Jun 23 05:56:08 PM PDT 24
Finished Jun 23 05:57:59 PM PDT 24
Peak memory 202260 kb
Host smart-fb27bf99-3800-48de-8f2a-5935f9cc86e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418363763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.418363763
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2281106835
Short name T390
Test name
Test status
Simulation time 602857495799 ps
CPU time 216.25 seconds
Started Jun 23 05:56:06 PM PDT 24
Finished Jun 23 05:59:42 PM PDT 24
Peak memory 202232 kb
Host smart-30eb9466-40c9-4b8b-88b3-f360e7bb9fce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281106835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2281106835
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3186093829
Short name T689
Test name
Test status
Simulation time 77155578456 ps
CPU time 426.38 seconds
Started Jun 23 05:56:17 PM PDT 24
Finished Jun 23 06:03:24 PM PDT 24
Peak memory 202564 kb
Host smart-7f216ef0-a439-4d1a-9e3a-f619ccc77245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186093829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3186093829
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2976674652
Short name T613
Test name
Test status
Simulation time 35519609970 ps
CPU time 21.07 seconds
Started Jun 23 05:56:05 PM PDT 24
Finished Jun 23 05:56:27 PM PDT 24
Peak memory 202032 kb
Host smart-5b71ad4c-7536-48c6-91e8-f046711e04d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976674652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2976674652
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3609811193
Short name T459
Test name
Test status
Simulation time 2914316351 ps
CPU time 7.32 seconds
Started Jun 23 05:56:10 PM PDT 24
Finished Jun 23 05:56:17 PM PDT 24
Peak memory 202020 kb
Host smart-6c33847f-a28a-4861-b864-40d7d59b07f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609811193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3609811193
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1584781229
Short name T87
Test name
Test status
Simulation time 5794099231 ps
CPU time 4.19 seconds
Started Jun 23 05:56:07 PM PDT 24
Finished Jun 23 05:56:12 PM PDT 24
Peak memory 202012 kb
Host smart-8e628796-8782-4468-b5d3-a8027bf38a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584781229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1584781229
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.5772092
Short name T522
Test name
Test status
Simulation time 55623244755 ps
CPU time 132.51 seconds
Started Jun 23 05:56:09 PM PDT 24
Finished Jun 23 05:58:22 PM PDT 24
Peak memory 202324 kb
Host smart-40105772-f725-47a8-a7bb-3a23f5e66b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5772092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.5772092
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1859821656
Short name T344
Test name
Test status
Simulation time 145672154162 ps
CPU time 55.29 seconds
Started Jun 23 05:56:10 PM PDT 24
Finished Jun 23 05:57:06 PM PDT 24
Peak memory 210612 kb
Host smart-21cbadc7-4dec-4c25-9ec7-adf4c7ba6790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859821656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1859821656
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2989385947
Short name T398
Test name
Test status
Simulation time 427784745 ps
CPU time 1.12 seconds
Started Jun 23 05:56:09 PM PDT 24
Finished Jun 23 05:56:10 PM PDT 24
Peak memory 201920 kb
Host smart-0b65ee44-e730-44f6-b60c-254f3e4f3472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989385947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2989385947
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.210823355
Short name T333
Test name
Test status
Simulation time 178742841786 ps
CPU time 418.15 seconds
Started Jun 23 05:56:11 PM PDT 24
Finished Jun 23 06:03:10 PM PDT 24
Peak memory 202344 kb
Host smart-de1da302-d913-4da2-8bd5-35ecb6eab07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210823355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.210823355
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.173294289
Short name T243
Test name
Test status
Simulation time 320893872115 ps
CPU time 680.99 seconds
Started Jun 23 05:56:12 PM PDT 24
Finished Jun 23 06:07:33 PM PDT 24
Peak memory 202340 kb
Host smart-49fc1b1b-d28d-482f-976a-3807c3b96709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173294289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.173294289
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1256626516
Short name T627
Test name
Test status
Simulation time 162021535143 ps
CPU time 98.37 seconds
Started Jun 23 05:56:10 PM PDT 24
Finished Jun 23 05:57:49 PM PDT 24
Peak memory 202220 kb
Host smart-0f735427-6c2b-4ad6-929c-e47a8def4a8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256626516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1256626516
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1539916171
Short name T752
Test name
Test status
Simulation time 328670352958 ps
CPU time 209.74 seconds
Started Jun 23 05:56:10 PM PDT 24
Finished Jun 23 05:59:41 PM PDT 24
Peak memory 202220 kb
Host smart-eca40f47-50a7-4c29-b5c6-7b50aecae2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539916171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1539916171
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.789793236
Short name T402
Test name
Test status
Simulation time 332357945994 ps
CPU time 219.57 seconds
Started Jun 23 05:56:09 PM PDT 24
Finished Jun 23 05:59:49 PM PDT 24
Peak memory 202172 kb
Host smart-aa5d740d-0082-4752-99e9-b7f455629f8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=789793236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.789793236
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.666979166
Short name T679
Test name
Test status
Simulation time 409456810389 ps
CPU time 429.15 seconds
Started Jun 23 05:56:10 PM PDT 24
Finished Jun 23 06:03:19 PM PDT 24
Peak memory 202176 kb
Host smart-87371832-5266-4474-8ee2-9635412a1c24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666979166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.666979166
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2575526834
Short name T184
Test name
Test status
Simulation time 126064193727 ps
CPU time 445.98 seconds
Started Jun 23 05:56:09 PM PDT 24
Finished Jun 23 06:03:35 PM PDT 24
Peak memory 202584 kb
Host smart-7e926954-2444-4185-9102-1038053f2aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575526834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2575526834
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3408161925
Short name T776
Test name
Test status
Simulation time 33085841252 ps
CPU time 44.65 seconds
Started Jun 23 05:56:11 PM PDT 24
Finished Jun 23 05:56:56 PM PDT 24
Peak memory 202044 kb
Host smart-69319892-0cb2-4f19-9dfa-22238becc7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408161925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3408161925
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2364533378
Short name T498
Test name
Test status
Simulation time 3864301916 ps
CPU time 10.12 seconds
Started Jun 23 05:56:17 PM PDT 24
Finished Jun 23 05:56:27 PM PDT 24
Peak memory 202088 kb
Host smart-84f728a7-4e1c-4c0d-8fb0-eb5f1487d02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364533378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2364533378
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.925093788
Short name T702
Test name
Test status
Simulation time 5620845710 ps
CPU time 2.71 seconds
Started Jun 23 05:56:09 PM PDT 24
Finished Jun 23 05:56:12 PM PDT 24
Peak memory 202076 kb
Host smart-02b952da-e21f-4ea3-92e7-a62ff0bc63e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925093788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.925093788
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1171731521
Short name T18
Test name
Test status
Simulation time 379741270156 ps
CPU time 279.93 seconds
Started Jun 23 05:56:12 PM PDT 24
Finished Jun 23 06:00:53 PM PDT 24
Peak memory 218272 kb
Host smart-91770efa-0efa-4c18-ae2b-39b39584e21b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171731521 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1171731521
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1592795975
Short name T400
Test name
Test status
Simulation time 452894911 ps
CPU time 0.94 seconds
Started Jun 23 05:56:17 PM PDT 24
Finished Jun 23 05:56:18 PM PDT 24
Peak memory 201948 kb
Host smart-78b8f52b-df4b-43e5-ac0d-2b4282a07fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592795975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1592795975
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2192762729
Short name T124
Test name
Test status
Simulation time 196956527445 ps
CPU time 114.86 seconds
Started Jun 23 05:56:16 PM PDT 24
Finished Jun 23 05:58:11 PM PDT 24
Peak memory 202336 kb
Host smart-4b5d35d8-81c3-49ca-b338-a6623195033f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192762729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2192762729
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2460852838
Short name T260
Test name
Test status
Simulation time 167284481493 ps
CPU time 354.32 seconds
Started Jun 23 05:56:23 PM PDT 24
Finished Jun 23 06:02:17 PM PDT 24
Peak memory 202256 kb
Host smart-81cdbc5b-10c5-4826-9090-53b96560e7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460852838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2460852838
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2375280652
Short name T140
Test name
Test status
Simulation time 495739617285 ps
CPU time 1177.76 seconds
Started Jun 23 05:56:16 PM PDT 24
Finished Jun 23 06:15:54 PM PDT 24
Peak memory 202216 kb
Host smart-1cbfaad2-6058-4441-a149-d583fee8846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375280652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2375280652
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.420684749
Short name T81
Test name
Test status
Simulation time 489910052318 ps
CPU time 1183.22 seconds
Started Jun 23 05:56:24 PM PDT 24
Finished Jun 23 06:16:08 PM PDT 24
Peak memory 202292 kb
Host smart-ac67fa0e-954a-4e60-ade6-04bace918575
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=420684749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.420684749
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3484594216
Short name T791
Test name
Test status
Simulation time 489965396090 ps
CPU time 1122.09 seconds
Started Jun 23 05:56:11 PM PDT 24
Finished Jun 23 06:14:53 PM PDT 24
Peak memory 202204 kb
Host smart-cf427eff-92bf-4a49-8719-d6bf32df6e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484594216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3484594216
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2601867217
Short name T170
Test name
Test status
Simulation time 324172408973 ps
CPU time 375.78 seconds
Started Jun 23 05:56:14 PM PDT 24
Finished Jun 23 06:02:30 PM PDT 24
Peak memory 202172 kb
Host smart-3ce8fd62-7590-4bf1-a59b-c351982cd70d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601867217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2601867217
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.441961086
Short name T245
Test name
Test status
Simulation time 371693952171 ps
CPU time 200.4 seconds
Started Jun 23 05:56:15 PM PDT 24
Finished Jun 23 05:59:36 PM PDT 24
Peak memory 202248 kb
Host smart-9c36b7e3-a4da-419e-b279-f08e8f4c95ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441961086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.441961086
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.455723466
Short name T540
Test name
Test status
Simulation time 585066137711 ps
CPU time 1421.12 seconds
Started Jun 23 05:56:15 PM PDT 24
Finished Jun 23 06:19:56 PM PDT 24
Peak memory 202288 kb
Host smart-00211fa7-0f1c-454b-b2d3-4e5155526f81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455723466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.455723466
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2662929693
Short name T36
Test name
Test status
Simulation time 92026550932 ps
CPU time 331.7 seconds
Started Jun 23 05:56:13 PM PDT 24
Finished Jun 23 06:01:45 PM PDT 24
Peak memory 202480 kb
Host smart-1b8d3334-500e-40ed-9749-d90514974547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662929693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2662929693
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2269777331
Short name T520
Test name
Test status
Simulation time 25559911060 ps
CPU time 22.78 seconds
Started Jun 23 05:56:17 PM PDT 24
Finished Jun 23 05:56:40 PM PDT 24
Peak memory 202032 kb
Host smart-533e5d65-48aa-4dcc-a2b7-5b6dfec7426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269777331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2269777331
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3472867072
Short name T367
Test name
Test status
Simulation time 4217102622 ps
CPU time 2.93 seconds
Started Jun 23 05:56:14 PM PDT 24
Finished Jun 23 05:56:17 PM PDT 24
Peak memory 202028 kb
Host smart-a4f29ef7-1c23-4682-904a-f3e394e6d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472867072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3472867072
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3460170083
Short name T486
Test name
Test status
Simulation time 5860414800 ps
CPU time 4.1 seconds
Started Jun 23 05:56:10 PM PDT 24
Finished Jun 23 05:56:14 PM PDT 24
Peak memory 202048 kb
Host smart-88fd3551-5d85-4830-b27e-4627ec57d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460170083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3460170083
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2443786090
Short name T72
Test name
Test status
Simulation time 358778653970 ps
CPU time 882.76 seconds
Started Jun 23 05:56:16 PM PDT 24
Finished Jun 23 06:10:59 PM PDT 24
Peak memory 202216 kb
Host smart-0f603a6f-18e3-4aab-addf-023248248f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443786090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2443786090
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3165535575
Short name T551
Test name
Test status
Simulation time 234516173452 ps
CPU time 247.55 seconds
Started Jun 23 05:56:23 PM PDT 24
Finished Jun 23 06:00:31 PM PDT 24
Peak memory 210884 kb
Host smart-b35c4f06-2530-4a74-9c2c-ea5c011e7bf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165535575 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3165535575
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3135326535
Short name T429
Test name
Test status
Simulation time 372707582 ps
CPU time 1.44 seconds
Started Jun 23 05:56:22 PM PDT 24
Finished Jun 23 05:56:24 PM PDT 24
Peak memory 201956 kb
Host smart-d85bb410-afe4-4f84-95c0-4ed473715694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135326535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3135326535
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3078810558
Short name T259
Test name
Test status
Simulation time 165436005834 ps
CPU time 168.39 seconds
Started Jun 23 05:56:12 PM PDT 24
Finished Jun 23 05:59:01 PM PDT 24
Peak memory 202140 kb
Host smart-c90ce1d6-e114-462d-88a3-7624513e1910
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078810558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3078810558
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2267399910
Short name T252
Test name
Test status
Simulation time 164344008296 ps
CPU time 389.7 seconds
Started Jun 23 05:56:16 PM PDT 24
Finished Jun 23 06:02:46 PM PDT 24
Peak memory 202256 kb
Host smart-f0018f19-2c19-41d7-8ba2-5e7553be6af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267399910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2267399910
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1157982279
Short name T433
Test name
Test status
Simulation time 166053188357 ps
CPU time 374.29 seconds
Started Jun 23 05:56:18 PM PDT 24
Finished Jun 23 06:02:33 PM PDT 24
Peak memory 202236 kb
Host smart-488349d8-27f1-42b6-a07e-e252069997de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157982279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1157982279
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2171355897
Short name T174
Test name
Test status
Simulation time 489856001623 ps
CPU time 300.18 seconds
Started Jun 23 05:56:18 PM PDT 24
Finished Jun 23 06:01:18 PM PDT 24
Peak memory 202300 kb
Host smart-e2ac54fe-d4ba-43bc-b9aa-73614da0f8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171355897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2171355897
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2721328568
Short name T797
Test name
Test status
Simulation time 327491887313 ps
CPU time 668.35 seconds
Started Jun 23 05:56:14 PM PDT 24
Finished Jun 23 06:07:23 PM PDT 24
Peak memory 202296 kb
Host smart-b9320921-0136-468c-acef-2e52ec1dbd2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721328568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2721328568
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1815744561
Short name T719
Test name
Test status
Simulation time 162720630200 ps
CPU time 187.66 seconds
Started Jun 23 05:56:19 PM PDT 24
Finished Jun 23 05:59:26 PM PDT 24
Peak memory 202272 kb
Host smart-836969f6-04d0-4ade-9ccf-67819910dfb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815744561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1815744561
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3910468215
Short name T523
Test name
Test status
Simulation time 404412512064 ps
CPU time 122.05 seconds
Started Jun 23 05:56:14 PM PDT 24
Finished Jun 23 05:58:16 PM PDT 24
Peak memory 202232 kb
Host smart-3c9ce021-9959-45c1-bfdb-33298caab7c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910468215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3910468215
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2009897436
Short name T185
Test name
Test status
Simulation time 109430940468 ps
CPU time 393.28 seconds
Started Jun 23 05:56:14 PM PDT 24
Finished Jun 23 06:02:47 PM PDT 24
Peak memory 202504 kb
Host smart-f8e7f76b-0a58-4fc6-bcda-26de7bbbff06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009897436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2009897436
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4114335145
Short name T448
Test name
Test status
Simulation time 28390002836 ps
CPU time 15.77 seconds
Started Jun 23 05:56:23 PM PDT 24
Finished Jun 23 05:56:40 PM PDT 24
Peak memory 202088 kb
Host smart-4d1f2bc7-cbc7-4c45-bb43-0dbb0dfa72e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114335145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4114335145
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.4035907908
Short name T773
Test name
Test status
Simulation time 3042366473 ps
CPU time 7.63 seconds
Started Jun 23 05:56:16 PM PDT 24
Finished Jun 23 05:56:24 PM PDT 24
Peak memory 202016 kb
Host smart-39f7b984-2fbf-423a-9a68-fd23857482b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035907908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4035907908
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.512794519
Short name T697
Test name
Test status
Simulation time 5710989121 ps
CPU time 7.24 seconds
Started Jun 23 05:56:23 PM PDT 24
Finished Jun 23 05:56:31 PM PDT 24
Peak memory 202072 kb
Host smart-ed3e3ea6-69a0-43d5-a9a8-8b4d83249e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512794519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.512794519
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1534531414
Short name T648
Test name
Test status
Simulation time 395360497 ps
CPU time 1.47 seconds
Started Jun 23 05:56:22 PM PDT 24
Finished Jun 23 05:56:24 PM PDT 24
Peak memory 201972 kb
Host smart-84a8fbce-dd94-4c29-a9aa-fd3e017eba21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534531414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1534531414
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1884949512
Short name T303
Test name
Test status
Simulation time 181275812696 ps
CPU time 59.59 seconds
Started Jun 23 05:56:22 PM PDT 24
Finished Jun 23 05:57:22 PM PDT 24
Peak memory 202348 kb
Host smart-1b3d8db1-2c44-49c6-9d84-a0e8b3ddb396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884949512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1884949512
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2185215141
Short name T98
Test name
Test status
Simulation time 156059280939 ps
CPU time 325.09 seconds
Started Jun 23 05:56:20 PM PDT 24
Finished Jun 23 06:01:46 PM PDT 24
Peak memory 202268 kb
Host smart-59afa89a-f0a7-4cac-ab8b-e39b84f329fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185215141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2185215141
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2861210958
Short name T686
Test name
Test status
Simulation time 489667396092 ps
CPU time 125.85 seconds
Started Jun 23 05:56:22 PM PDT 24
Finished Jun 23 05:58:28 PM PDT 24
Peak memory 202152 kb
Host smart-8bcbaa59-7358-4e2c-a430-61e7295643fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861210958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2861210958
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.69892396
Short name T207
Test name
Test status
Simulation time 320227020258 ps
CPU time 686.57 seconds
Started Jun 23 05:56:21 PM PDT 24
Finished Jun 23 06:07:48 PM PDT 24
Peak memory 202336 kb
Host smart-2b37f7bb-c52a-4a24-868d-a78a0b0bceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69892396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.69892396
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1004749795
Short name T790
Test name
Test status
Simulation time 321151104138 ps
CPU time 649.01 seconds
Started Jun 23 05:56:22 PM PDT 24
Finished Jun 23 06:07:12 PM PDT 24
Peak memory 202176 kb
Host smart-5907745f-81f2-424d-ad2b-9d75b1517d3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004749795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1004749795
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.883501138
Short name T552
Test name
Test status
Simulation time 200808230029 ps
CPU time 278.25 seconds
Started Jun 23 05:56:20 PM PDT 24
Finished Jun 23 06:00:59 PM PDT 24
Peak memory 202312 kb
Host smart-13be2422-5cb2-4897-8c0d-132e1bc8a3f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883501138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.883501138
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.560205623
Short name T347
Test name
Test status
Simulation time 111391939067 ps
CPU time 628.41 seconds
Started Jun 23 05:56:21 PM PDT 24
Finished Jun 23 06:06:49 PM PDT 24
Peak memory 202584 kb
Host smart-d63cb823-819a-45ed-889c-2d5be543e19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560205623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.560205623
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1483182716
Short name T635
Test name
Test status
Simulation time 36633015869 ps
CPU time 80.2 seconds
Started Jun 23 05:56:20 PM PDT 24
Finished Jun 23 05:57:41 PM PDT 24
Peak memory 202256 kb
Host smart-02c2b5c0-6743-4cdb-b9c5-87b82641ceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483182716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1483182716
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.4054779948
Short name T395
Test name
Test status
Simulation time 2974570701 ps
CPU time 2.53 seconds
Started Jun 23 05:56:19 PM PDT 24
Finished Jun 23 05:56:22 PM PDT 24
Peak memory 202056 kb
Host smart-15d1e53f-bf16-4af8-b701-af8135f95cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054779948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.4054779948
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.618509530
Short name T758
Test name
Test status
Simulation time 6138812245 ps
CPU time 4.51 seconds
Started Jun 23 05:56:15 PM PDT 24
Finished Jun 23 05:56:19 PM PDT 24
Peak memory 202048 kb
Host smart-38d1ff01-2b07-43c6-a8f5-d52c85089857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618509530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.618509530
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2323704336
Short name T723
Test name
Test status
Simulation time 266618412235 ps
CPU time 817.49 seconds
Started Jun 23 05:56:21 PM PDT 24
Finished Jun 23 06:09:59 PM PDT 24
Peak memory 210716 kb
Host smart-dbbbfd18-2c95-4ae4-9715-7aaf84e66eca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323704336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2323704336
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2097924959
Short name T323
Test name
Test status
Simulation time 15315554350 ps
CPU time 45.41 seconds
Started Jun 23 05:56:21 PM PDT 24
Finished Jun 23 05:57:07 PM PDT 24
Peak memory 210716 kb
Host smart-29761a61-0672-471a-b1ef-d43c5003181b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097924959 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2097924959
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2491286528
Short name T404
Test name
Test status
Simulation time 400188570 ps
CPU time 1.58 seconds
Started Jun 23 05:56:28 PM PDT 24
Finished Jun 23 05:56:30 PM PDT 24
Peak memory 202008 kb
Host smart-d36adc6d-fa46-4c9b-aa6e-6eb5aed4240d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491286528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2491286528
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1034620132
Short name T655
Test name
Test status
Simulation time 543889496737 ps
CPU time 649 seconds
Started Jun 23 05:56:24 PM PDT 24
Finished Jun 23 06:07:14 PM PDT 24
Peak memory 202200 kb
Host smart-c015daa3-00e9-4685-926f-5f2390d15d12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034620132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1034620132
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2989270538
Short name T283
Test name
Test status
Simulation time 328717828534 ps
CPU time 353.6 seconds
Started Jun 23 05:56:26 PM PDT 24
Finished Jun 23 06:02:20 PM PDT 24
Peak memory 202256 kb
Host smart-b1ea55e2-2714-4fb6-a5da-9451786575fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989270538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2989270538
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1724918988
Short name T478
Test name
Test status
Simulation time 164649068194 ps
CPU time 389.14 seconds
Started Jun 23 05:56:25 PM PDT 24
Finished Jun 23 06:02:54 PM PDT 24
Peak memory 202152 kb
Host smart-d2d6818d-133b-452b-a50e-734c5fd1e599
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724918988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1724918988
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1425722181
Short name T464
Test name
Test status
Simulation time 327984036965 ps
CPU time 794.26 seconds
Started Jun 23 05:56:21 PM PDT 24
Finished Jun 23 06:09:35 PM PDT 24
Peak memory 202340 kb
Host smart-225fcded-708e-45bf-90e7-ffaeea9e4fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425722181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1425722181
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.54564134
Short name T382
Test name
Test status
Simulation time 487235201809 ps
CPU time 336.27 seconds
Started Jun 23 05:56:21 PM PDT 24
Finished Jun 23 06:01:58 PM PDT 24
Peak memory 202232 kb
Host smart-0bde95a5-9464-4cab-b2ae-0b477fb71140
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=54564134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed
.54564134
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.176163602
Short name T332
Test name
Test status
Simulation time 392077146051 ps
CPU time 878.96 seconds
Started Jun 23 05:56:28 PM PDT 24
Finished Jun 23 06:11:07 PM PDT 24
Peak memory 202360 kb
Host smart-4bbe04fd-38e8-41ac-a8ea-765746193630
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176163602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.176163602
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1823764211
Short name T562
Test name
Test status
Simulation time 603435313732 ps
CPU time 186.73 seconds
Started Jun 23 05:56:25 PM PDT 24
Finished Jun 23 05:59:33 PM PDT 24
Peak memory 202248 kb
Host smart-6e943f30-bea9-4bd1-b319-46be4125ccfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823764211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1823764211
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1202197119
Short name T669
Test name
Test status
Simulation time 103900046895 ps
CPU time 583.12 seconds
Started Jun 23 05:56:27 PM PDT 24
Finished Jun 23 06:06:10 PM PDT 24
Peak memory 202636 kb
Host smart-3b83a87d-4d3b-4ab8-98f7-9f8e6d8aef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202197119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1202197119
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3544273972
Short name T366
Test name
Test status
Simulation time 33336271691 ps
CPU time 18.51 seconds
Started Jun 23 05:56:26 PM PDT 24
Finished Jun 23 05:56:45 PM PDT 24
Peak memory 202044 kb
Host smart-209cc5ae-3d30-4d4f-84ed-3cf1d0bab7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544273972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3544273972
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2441346902
Short name T364
Test name
Test status
Simulation time 4343223725 ps
CPU time 10.72 seconds
Started Jun 23 05:56:23 PM PDT 24
Finished Jun 23 05:56:34 PM PDT 24
Peak memory 201964 kb
Host smart-66298520-fe01-41aa-8e3e-040be89c0b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441346902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2441346902
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.389904856
Short name T482
Test name
Test status
Simulation time 5693567876 ps
CPU time 2.36 seconds
Started Jun 23 05:56:21 PM PDT 24
Finished Jun 23 05:56:24 PM PDT 24
Peak memory 202028 kb
Host smart-89199ff8-6956-4864-8d87-557b874c8928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389904856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.389904856
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1022333492
Short name T181
Test name
Test status
Simulation time 113067223054 ps
CPU time 385.43 seconds
Started Jun 23 05:56:24 PM PDT 24
Finished Jun 23 06:02:50 PM PDT 24
Peak memory 202724 kb
Host smart-278403d5-bfe8-4b52-8f76-ce661495d86a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022333492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1022333492
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4234476782
Short name T501
Test name
Test status
Simulation time 2535394954939 ps
CPU time 202.91 seconds
Started Jun 23 05:56:26 PM PDT 24
Finished Jun 23 05:59:49 PM PDT 24
Peak memory 202348 kb
Host smart-6460ef34-d4eb-4840-b6f5-859dac763718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234476782 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4234476782
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1002627217
Short name T717
Test name
Test status
Simulation time 378957632 ps
CPU time 1.46 seconds
Started Jun 23 05:56:30 PM PDT 24
Finished Jun 23 05:56:32 PM PDT 24
Peak memory 201972 kb
Host smart-096b511e-d8a0-4c2f-9433-5ea1d828933b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002627217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1002627217
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.593754093
Short name T657
Test name
Test status
Simulation time 192253330155 ps
CPU time 448.7 seconds
Started Jun 23 05:56:25 PM PDT 24
Finished Jun 23 06:03:55 PM PDT 24
Peak memory 202248 kb
Host smart-7121480f-b0f8-4a1a-8951-1d717314f7df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593754093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.593754093
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.224380805
Short name T731
Test name
Test status
Simulation time 332239753634 ps
CPU time 654.59 seconds
Started Jun 23 05:56:26 PM PDT 24
Finished Jun 23 06:07:21 PM PDT 24
Peak memory 202328 kb
Host smart-d7b79238-d462-49e2-b037-549b5b489b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224380805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.224380805
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3804428767
Short name T363
Test name
Test status
Simulation time 496988497561 ps
CPU time 517.59 seconds
Started Jun 23 05:56:26 PM PDT 24
Finished Jun 23 06:05:04 PM PDT 24
Peak memory 202212 kb
Host smart-8549b5c3-0171-482f-84ef-e4d125ec6d43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804428767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3804428767
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.379864081
Short name T306
Test name
Test status
Simulation time 322985286656 ps
CPU time 741.38 seconds
Started Jun 23 05:56:24 PM PDT 24
Finished Jun 23 06:08:46 PM PDT 24
Peak memory 202264 kb
Host smart-5813958a-ce97-4033-b109-47fe6eb380a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379864081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.379864081
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2090062510
Short name T516
Test name
Test status
Simulation time 321087324770 ps
CPU time 686.32 seconds
Started Jun 23 05:56:24 PM PDT 24
Finished Jun 23 06:07:51 PM PDT 24
Peak memory 202180 kb
Host smart-f340fb41-b881-44c6-9ddd-5677b1cfc7f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090062510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2090062510
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.4097191651
Short name T345
Test name
Test status
Simulation time 511445107051 ps
CPU time 1183.28 seconds
Started Jun 23 05:56:25 PM PDT 24
Finished Jun 23 06:16:09 PM PDT 24
Peak memory 202328 kb
Host smart-06945e1d-c362-4e4f-af5b-817d69b897bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097191651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.4097191651
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3805689755
Short name T473
Test name
Test status
Simulation time 202941621873 ps
CPU time 233.97 seconds
Started Jun 23 05:56:26 PM PDT 24
Finished Jun 23 06:00:20 PM PDT 24
Peak memory 202236 kb
Host smart-2163c16f-4551-4e38-a4c1-6d5db94011a8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805689755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3805689755
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1566407200
Short name T705
Test name
Test status
Simulation time 79016099537 ps
CPU time 237.54 seconds
Started Jun 23 05:56:31 PM PDT 24
Finished Jun 23 06:00:29 PM PDT 24
Peak memory 202512 kb
Host smart-0f997db5-31af-415d-94ed-c2fc682b0985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566407200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1566407200
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1567459007
Short name T582
Test name
Test status
Simulation time 30445737330 ps
CPU time 62.95 seconds
Started Jun 23 05:56:22 PM PDT 24
Finished Jun 23 05:57:26 PM PDT 24
Peak memory 202092 kb
Host smart-e2e0fac9-b4fa-4fba-8726-05fb94121dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567459007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1567459007
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.573303330
Short name T419
Test name
Test status
Simulation time 3180104820 ps
CPU time 2.45 seconds
Started Jun 23 05:56:27 PM PDT 24
Finished Jun 23 05:56:29 PM PDT 24
Peak memory 202076 kb
Host smart-192697ea-b4da-4318-a082-c85ed26957ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573303330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.573303330
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2038580999
Short name T493
Test name
Test status
Simulation time 5690559316 ps
CPU time 1.66 seconds
Started Jun 23 05:56:30 PM PDT 24
Finished Jun 23 05:56:32 PM PDT 24
Peak memory 202116 kb
Host smart-b5c80704-50fd-4085-98f1-9efba2548259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038580999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2038580999
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3356581569
Short name T535
Test name
Test status
Simulation time 188930511257 ps
CPU time 215.41 seconds
Started Jun 23 05:56:30 PM PDT 24
Finished Jun 23 06:00:06 PM PDT 24
Peak memory 210800 kb
Host smart-fa1406a4-ddfa-4265-a535-cd6ae8f7f344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356581569 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3356581569
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.393732081
Short name T622
Test name
Test status
Simulation time 432016607 ps
CPU time 1 seconds
Started Jun 23 05:56:29 PM PDT 24
Finished Jun 23 05:56:30 PM PDT 24
Peak memory 202120 kb
Host smart-7193f4ab-60e6-426f-b172-6703c28132ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393732081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.393732081
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2061615555
Short name T538
Test name
Test status
Simulation time 175764627995 ps
CPU time 103.81 seconds
Started Jun 23 05:56:34 PM PDT 24
Finished Jun 23 05:58:19 PM PDT 24
Peak memory 202280 kb
Host smart-424c7654-61eb-4c99-8325-42405c4f9627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061615555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2061615555
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1139553747
Short name T164
Test name
Test status
Simulation time 327587477036 ps
CPU time 188.22 seconds
Started Jun 23 05:56:32 PM PDT 24
Finished Jun 23 05:59:41 PM PDT 24
Peak memory 202252 kb
Host smart-bdc87ac0-371d-4768-ab32-48bb7cd3c8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139553747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1139553747
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1862578047
Short name T612
Test name
Test status
Simulation time 328953777019 ps
CPU time 203.35 seconds
Started Jun 23 05:56:31 PM PDT 24
Finished Jun 23 05:59:54 PM PDT 24
Peak memory 202292 kb
Host smart-58c19659-97c7-40fd-affe-81e11c3d99f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862578047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1862578047
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2248055735
Short name T79
Test name
Test status
Simulation time 327006975057 ps
CPU time 747.52 seconds
Started Jun 23 05:56:31 PM PDT 24
Finished Jun 23 06:09:00 PM PDT 24
Peak memory 202312 kb
Host smart-4af69b39-13d7-4a4c-b40a-1e7e127deba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248055735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2248055735
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.4041503458
Short name T417
Test name
Test status
Simulation time 488837331159 ps
CPU time 317.58 seconds
Started Jun 23 05:56:31 PM PDT 24
Finished Jun 23 06:01:49 PM PDT 24
Peak memory 202304 kb
Host smart-016eea07-eb35-489b-a901-651b33517a00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041503458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.4041503458
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3166445630
Short name T206
Test name
Test status
Simulation time 531573780997 ps
CPU time 589.62 seconds
Started Jun 23 05:56:29 PM PDT 24
Finished Jun 23 06:06:19 PM PDT 24
Peak memory 202332 kb
Host smart-573f97e7-cc86-4643-8d73-141f76ef2f0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166445630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3166445630
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1025559654
Short name T733
Test name
Test status
Simulation time 213662172866 ps
CPU time 487.4 seconds
Started Jun 23 05:56:32 PM PDT 24
Finished Jun 23 06:04:40 PM PDT 24
Peak memory 202272 kb
Host smart-ae846c98-0abb-42cd-a2a9-d629cb56afff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025559654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1025559654
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.840497125
Short name T368
Test name
Test status
Simulation time 62164560182 ps
CPU time 342.6 seconds
Started Jun 23 05:56:31 PM PDT 24
Finished Jun 23 06:02:14 PM PDT 24
Peak memory 202488 kb
Host smart-6021b40f-5b2b-4ba6-983a-9bd82724419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840497125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.840497125
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1646497718
Short name T685
Test name
Test status
Simulation time 43943038626 ps
CPU time 22.63 seconds
Started Jun 23 05:56:31 PM PDT 24
Finished Jun 23 05:56:54 PM PDT 24
Peak memory 202048 kb
Host smart-1cfd6f4e-3d11-4722-b986-37b2780e993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646497718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1646497718
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4288769651
Short name T386
Test name
Test status
Simulation time 5201354330 ps
CPU time 12.57 seconds
Started Jun 23 05:56:33 PM PDT 24
Finished Jun 23 05:56:46 PM PDT 24
Peak memory 202076 kb
Host smart-a4d8212f-50a2-4a71-8a73-457c3b0eea9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288769651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4288769651
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3261921621
Short name T444
Test name
Test status
Simulation time 6364603924 ps
CPU time 1.7 seconds
Started Jun 23 05:56:27 PM PDT 24
Finished Jun 23 05:56:29 PM PDT 24
Peak memory 202060 kb
Host smart-6fbb8828-cfb2-42d8-aebb-11fa3f40a238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261921621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3261921621
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.420462636
Short name T645
Test name
Test status
Simulation time 28813104300 ps
CPU time 38.34 seconds
Started Jun 23 05:56:30 PM PDT 24
Finished Jun 23 05:57:08 PM PDT 24
Peak memory 202260 kb
Host smart-984df779-152a-4e18-9556-633174c5bee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420462636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
420462636
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3166005147
Short name T441
Test name
Test status
Simulation time 239496592895 ps
CPU time 141.48 seconds
Started Jun 23 05:56:28 PM PDT 24
Finished Jun 23 05:58:50 PM PDT 24
Peak memory 210888 kb
Host smart-cd22e8ad-2269-41bd-be1b-e2d817a5bcd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166005147 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3166005147
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2716824461
Short name T476
Test name
Test status
Simulation time 305257449 ps
CPU time 1.25 seconds
Started Jun 23 05:56:35 PM PDT 24
Finished Jun 23 05:56:37 PM PDT 24
Peak memory 201960 kb
Host smart-f05fccc8-6efc-4609-b675-4e57da73530d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716824461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2716824461
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3300262311
Short name T610
Test name
Test status
Simulation time 173598153779 ps
CPU time 344.69 seconds
Started Jun 23 05:56:36 PM PDT 24
Finished Jun 23 06:02:21 PM PDT 24
Peak memory 202308 kb
Host smart-3354ec97-6418-4002-8274-9330aa4e1c96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300262311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3300262311
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.851324449
Short name T554
Test name
Test status
Simulation time 163598823342 ps
CPU time 200.46 seconds
Started Jun 23 05:56:39 PM PDT 24
Finished Jun 23 06:00:00 PM PDT 24
Peak memory 202276 kb
Host smart-f8b29194-a7d6-4f39-a3f4-4c4af8055b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851324449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.851324449
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3897264735
Short name T428
Test name
Test status
Simulation time 481418852717 ps
CPU time 1077.84 seconds
Started Jun 23 05:56:39 PM PDT 24
Finished Jun 23 06:14:37 PM PDT 24
Peak memory 202228 kb
Host smart-facb67dd-c21c-41b1-b394-40a3a2cc5103
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897264735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3897264735
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3107316411
Short name T650
Test name
Test status
Simulation time 500704288634 ps
CPU time 1116.3 seconds
Started Jun 23 05:56:35 PM PDT 24
Finished Jun 23 06:15:12 PM PDT 24
Peak memory 202232 kb
Host smart-91d0154a-0fc8-4be1-a372-225f3ba851d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107316411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3107316411
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2154853596
Short name T766
Test name
Test status
Simulation time 326400979215 ps
CPU time 688.38 seconds
Started Jun 23 05:56:43 PM PDT 24
Finished Jun 23 06:08:12 PM PDT 24
Peak memory 202208 kb
Host smart-2e729403-3341-4e89-b8d3-d1f8842c1401
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154853596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2154853596
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.611117435
Short name T312
Test name
Test status
Simulation time 558001671137 ps
CPU time 1201.15 seconds
Started Jun 23 05:56:36 PM PDT 24
Finished Jun 23 06:16:37 PM PDT 24
Peak memory 202232 kb
Host smart-6d2f31af-aae0-4cf1-a05f-24c95ee72e3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611117435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.611117435
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3021989593
Short name T503
Test name
Test status
Simulation time 399859166640 ps
CPU time 983.1 seconds
Started Jun 23 05:56:35 PM PDT 24
Finished Jun 23 06:12:58 PM PDT 24
Peak memory 202180 kb
Host smart-cd017180-b4c9-46a2-b25a-aebbe5b1c3fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021989593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3021989593
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1436348905
Short name T642
Test name
Test status
Simulation time 77926022105 ps
CPU time 388.16 seconds
Started Jun 23 05:56:37 PM PDT 24
Finished Jun 23 06:03:05 PM PDT 24
Peak memory 202556 kb
Host smart-e680d6da-2b42-49e0-a9de-d941af517b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436348905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1436348905
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1804609679
Short name T517
Test name
Test status
Simulation time 35222853291 ps
CPU time 75.48 seconds
Started Jun 23 05:56:35 PM PDT 24
Finished Jun 23 05:57:51 PM PDT 24
Peak memory 202100 kb
Host smart-51c06ef1-37cc-4f06-9e17-25700ec980e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804609679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1804609679
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2810967115
Short name T502
Test name
Test status
Simulation time 3532996642 ps
CPU time 4.74 seconds
Started Jun 23 05:56:44 PM PDT 24
Finished Jun 23 05:56:50 PM PDT 24
Peak memory 202032 kb
Host smart-1df8abb8-7d0a-43d9-877c-bfee3fa9285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810967115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2810967115
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.556787758
Short name T696
Test name
Test status
Simulation time 5731332164 ps
CPU time 13.39 seconds
Started Jun 23 05:56:42 PM PDT 24
Finished Jun 23 05:56:56 PM PDT 24
Peak memory 202068 kb
Host smart-b1f45440-93e9-4161-9c1f-dd4335599260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556787758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.556787758
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.319533506
Short name T242
Test name
Test status
Simulation time 171544120325 ps
CPU time 27.28 seconds
Started Jun 23 05:56:45 PM PDT 24
Finished Jun 23 05:57:12 PM PDT 24
Peak memory 202248 kb
Host smart-36115ec6-78ce-48de-999e-e7f9d1b0dd16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319533506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
319533506
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2888285946
Short name T280
Test name
Test status
Simulation time 91643718129 ps
CPU time 164.92 seconds
Started Jun 23 05:56:35 PM PDT 24
Finished Jun 23 05:59:20 PM PDT 24
Peak memory 218412 kb
Host smart-5a01d32f-783a-4b25-aa63-42d798083826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888285946 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2888285946
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.4037152489
Short name T377
Test name
Test status
Simulation time 421791810 ps
CPU time 1.55 seconds
Started Jun 23 05:55:07 PM PDT 24
Finished Jun 23 05:55:09 PM PDT 24
Peak memory 201952 kb
Host smart-186ddc5b-54be-412c-8b54-462f2682d531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037152489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.4037152489
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3346645503
Short name T205
Test name
Test status
Simulation time 162815630354 ps
CPU time 95.65 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 05:56:39 PM PDT 24
Peak memory 202284 kb
Host smart-0b24cc37-fc2c-40c3-96eb-2ab55147f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346645503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3346645503
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2896010475
Short name T785
Test name
Test status
Simulation time 484434615236 ps
CPU time 1128.62 seconds
Started Jun 23 05:55:05 PM PDT 24
Finished Jun 23 06:13:54 PM PDT 24
Peak memory 202280 kb
Host smart-509ef3dd-6832-40e5-bf73-c5e5a97136dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896010475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2896010475
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.247174106
Short name T156
Test name
Test status
Simulation time 485564131105 ps
CPU time 289.65 seconds
Started Jun 23 05:55:01 PM PDT 24
Finished Jun 23 05:59:51 PM PDT 24
Peak memory 202188 kb
Host smart-39105f6d-9ee0-41cb-809d-3833acb5504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247174106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.247174106
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.4197067184
Short name T640
Test name
Test status
Simulation time 327797072695 ps
CPU time 298.86 seconds
Started Jun 23 05:55:02 PM PDT 24
Finished Jun 23 06:00:01 PM PDT 24
Peak memory 202160 kb
Host smart-c5cd2d2f-db0c-4107-a166-d58e6076d530
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197067184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.4197067184
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1944580026
Short name T608
Test name
Test status
Simulation time 182546952223 ps
CPU time 407.07 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 06:01:51 PM PDT 24
Peak memory 202240 kb
Host smart-43345304-8d49-47cc-a66c-1dff84a326ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944580026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1944580026
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3768560840
Short name T695
Test name
Test status
Simulation time 394923523199 ps
CPU time 903.86 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 06:10:08 PM PDT 24
Peak memory 202176 kb
Host smart-22868954-f3c9-4097-9c7e-6f83a7e82f06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768560840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3768560840
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1525021732
Short name T521
Test name
Test status
Simulation time 120981212664 ps
CPU time 401.6 seconds
Started Jun 23 05:55:03 PM PDT 24
Finished Jun 23 06:01:45 PM PDT 24
Peak memory 202556 kb
Host smart-7c848c9f-4ed8-4347-a14e-27f93385f82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525021732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1525021732
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.630209593
Short name T556
Test name
Test status
Simulation time 23900016205 ps
CPU time 49.65 seconds
Started Jun 23 05:55:05 PM PDT 24
Finished Jun 23 05:55:55 PM PDT 24
Peak memory 202012 kb
Host smart-ea19dc77-51bd-49f7-8e63-78f542130c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630209593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.630209593
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2752273255
Short name T360
Test name
Test status
Simulation time 5268877849 ps
CPU time 3.77 seconds
Started Jun 23 05:55:06 PM PDT 24
Finished Jun 23 05:55:10 PM PDT 24
Peak memory 202128 kb
Host smart-1c235c18-594c-437e-863a-8fa2eb09a943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752273255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2752273255
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1891616278
Short name T67
Test name
Test status
Simulation time 4217627392 ps
CPU time 10.1 seconds
Started Jun 23 05:55:10 PM PDT 24
Finished Jun 23 05:55:21 PM PDT 24
Peak memory 217816 kb
Host smart-06bdfb0b-7f2f-4a60-a2f6-da65c871a9b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891616278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1891616278
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.944031861
Short name T481
Test name
Test status
Simulation time 5807201577 ps
CPU time 4.22 seconds
Started Jun 23 05:55:04 PM PDT 24
Finished Jun 23 05:55:08 PM PDT 24
Peak memory 202092 kb
Host smart-1a2271a5-5589-454e-ab0d-54fe0b98dea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944031861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.944031861
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3120539203
Short name T32
Test name
Test status
Simulation time 838614505502 ps
CPU time 1980.21 seconds
Started Jun 23 05:55:07 PM PDT 24
Finished Jun 23 06:28:07 PM PDT 24
Peak memory 213024 kb
Host smart-3929da04-38dc-4c97-ace3-7956c51c4978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120539203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3120539203
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.615470422
Short name T292
Test name
Test status
Simulation time 127307778626 ps
CPU time 70.54 seconds
Started Jun 23 05:55:02 PM PDT 24
Finished Jun 23 05:56:13 PM PDT 24
Peak memory 210628 kb
Host smart-1a437cf7-3009-4255-84b6-d3e440fb8690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615470422 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.615470422
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1475397968
Short name T406
Test name
Test status
Simulation time 454583462 ps
CPU time 0.86 seconds
Started Jun 23 05:56:44 PM PDT 24
Finished Jun 23 05:56:45 PM PDT 24
Peak memory 201896 kb
Host smart-40efdd6d-b260-4f65-b9d3-2ec30baa1785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475397968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1475397968
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3838710298
Short name T641
Test name
Test status
Simulation time 620269820957 ps
CPU time 1290.7 seconds
Started Jun 23 05:56:45 PM PDT 24
Finished Jun 23 06:18:16 PM PDT 24
Peak memory 202276 kb
Host smart-6289d55f-83ac-40ad-af8c-846a5923a42d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838710298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3838710298
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3031331570
Short name T774
Test name
Test status
Simulation time 165337161977 ps
CPU time 408 seconds
Started Jun 23 05:56:45 PM PDT 24
Finished Jun 23 06:03:33 PM PDT 24
Peak memory 202268 kb
Host smart-22ad47db-aa89-4641-b3c6-c795c86ad6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031331570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3031331570
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2093962846
Short name T474
Test name
Test status
Simulation time 320245850191 ps
CPU time 406.57 seconds
Started Jun 23 05:56:47 PM PDT 24
Finished Jun 23 06:03:34 PM PDT 24
Peak memory 202216 kb
Host smart-fe917889-5465-4bef-9581-a54fb276ec4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093962846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2093962846
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.34838173
Short name T694
Test name
Test status
Simulation time 160501825444 ps
CPU time 79.41 seconds
Started Jun 23 05:56:44 PM PDT 24
Finished Jun 23 05:58:04 PM PDT 24
Peak memory 202280 kb
Host smart-eb8e53f2-d450-4a0f-808c-14845fa96da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34838173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.34838173
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3975964159
Short name T592
Test name
Test status
Simulation time 496542126339 ps
CPU time 1177.32 seconds
Started Jun 23 05:56:46 PM PDT 24
Finished Jun 23 06:16:23 PM PDT 24
Peak memory 202188 kb
Host smart-e0cd7da6-b750-44b1-b274-376cc567f970
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975964159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3975964159
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1473394650
Short name T161
Test name
Test status
Simulation time 380785162708 ps
CPU time 441.48 seconds
Started Jun 23 05:56:42 PM PDT 24
Finished Jun 23 06:04:04 PM PDT 24
Peak memory 202492 kb
Host smart-bb8d6412-0839-46c1-b421-da62b807c9be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473394650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1473394650
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2266501506
Short name T570
Test name
Test status
Simulation time 191360151667 ps
CPU time 469.24 seconds
Started Jun 23 05:56:44 PM PDT 24
Finished Jun 23 06:04:33 PM PDT 24
Peak memory 202280 kb
Host smart-4b15d340-b5df-466b-8d65-c008a38e3770
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266501506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2266501506
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.266612628
Short name T39
Test name
Test status
Simulation time 76359153696 ps
CPU time 268.39 seconds
Started Jun 23 05:56:44 PM PDT 24
Finished Jun 23 06:01:13 PM PDT 24
Peak memory 202600 kb
Host smart-d543a124-1cde-4f13-b32b-6b37d217de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266612628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.266612628
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2240079777
Short name T792
Test name
Test status
Simulation time 26071758741 ps
CPU time 32.47 seconds
Started Jun 23 05:56:45 PM PDT 24
Finished Jun 23 05:57:18 PM PDT 24
Peak memory 202076 kb
Host smart-8096d327-8f3e-4cd2-ac31-2487fc4e5199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240079777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2240079777
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3649165247
Short name T782
Test name
Test status
Simulation time 2936450775 ps
CPU time 3.51 seconds
Started Jun 23 05:56:43 PM PDT 24
Finished Jun 23 05:56:47 PM PDT 24
Peak memory 202068 kb
Host smart-5c566a26-15d9-4732-8419-4ed17fe229e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649165247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3649165247
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1517866488
Short name T374
Test name
Test status
Simulation time 5566084797 ps
CPU time 7.33 seconds
Started Jun 23 05:56:39 PM PDT 24
Finished Jun 23 05:56:47 PM PDT 24
Peak memory 202072 kb
Host smart-0496fdc7-9d2d-4a7c-9638-d129f9d6ce57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517866488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1517866488
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3664376516
Short name T777
Test name
Test status
Simulation time 104436463111 ps
CPU time 50.99 seconds
Started Jun 23 05:56:42 PM PDT 24
Finished Jun 23 05:57:34 PM PDT 24
Peak memory 218996 kb
Host smart-388c64a1-075b-4d38-ae71-127506e1c8bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664376516 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3664376516
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2038026069
Short name T527
Test name
Test status
Simulation time 423162751 ps
CPU time 1.58 seconds
Started Jun 23 05:56:52 PM PDT 24
Finished Jun 23 05:56:54 PM PDT 24
Peak memory 201952 kb
Host smart-d14c8450-4527-4283-83f8-320ec4819185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038026069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2038026069
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.335244929
Short name T256
Test name
Test status
Simulation time 350846497032 ps
CPU time 202.1 seconds
Started Jun 23 05:56:46 PM PDT 24
Finished Jun 23 06:00:09 PM PDT 24
Peak memory 202260 kb
Host smart-1a2979dc-c688-4cdd-8926-f2b110413b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335244929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.335244929
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1366335986
Short name T211
Test name
Test status
Simulation time 333237641058 ps
CPU time 391.31 seconds
Started Jun 23 05:56:46 PM PDT 24
Finished Jun 23 06:03:18 PM PDT 24
Peak memory 202304 kb
Host smart-fa8872df-5499-4be5-9ea9-fef42952ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366335986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1366335986
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2920950492
Short name T568
Test name
Test status
Simulation time 321526425913 ps
CPU time 282.47 seconds
Started Jun 23 05:56:44 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 202216 kb
Host smart-1756f76f-78da-44a6-a492-c4ada4138efb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920950492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2920950492
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3735618804
Short name T297
Test name
Test status
Simulation time 326364039722 ps
CPU time 360.46 seconds
Started Jun 23 05:56:47 PM PDT 24
Finished Jun 23 06:02:47 PM PDT 24
Peak memory 202256 kb
Host smart-59b9de03-f309-43a1-89a9-c3ca3b8ce548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735618804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3735618804
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3628164768
Short name T618
Test name
Test status
Simulation time 164736229942 ps
CPU time 363.31 seconds
Started Jun 23 05:56:49 PM PDT 24
Finished Jun 23 06:02:53 PM PDT 24
Peak memory 202308 kb
Host smart-1ca096c6-1b94-4b77-9f81-fe8e86f8b556
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628164768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3628164768
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3033666144
Short name T467
Test name
Test status
Simulation time 406320359830 ps
CPU time 134.74 seconds
Started Jun 23 05:56:47 PM PDT 24
Finished Jun 23 05:59:02 PM PDT 24
Peak memory 202296 kb
Host smart-1ec9c022-1d7d-41f0-9169-d3250fd6da82
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033666144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3033666144
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3793635304
Short name T192
Test name
Test status
Simulation time 90358224775 ps
CPU time 335.59 seconds
Started Jun 23 05:56:46 PM PDT 24
Finished Jun 23 06:02:22 PM PDT 24
Peak memory 202644 kb
Host smart-c54cf849-247f-4685-8da8-88025e4e8842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793635304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3793635304
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.137285779
Short name T85
Test name
Test status
Simulation time 25068901313 ps
CPU time 50.91 seconds
Started Jun 23 05:56:46 PM PDT 24
Finished Jun 23 05:57:37 PM PDT 24
Peak memory 202024 kb
Host smart-9b514c25-cd76-4803-8591-176b91c10869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137285779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.137285779
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3629390242
Short name T153
Test name
Test status
Simulation time 5438086359 ps
CPU time 3.69 seconds
Started Jun 23 05:56:45 PM PDT 24
Finished Jun 23 05:56:49 PM PDT 24
Peak memory 202076 kb
Host smart-a60622aa-3b05-4677-a6d9-4f6f996bfda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629390242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3629390242
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2997643060
Short name T532
Test name
Test status
Simulation time 5743889800 ps
CPU time 3.57 seconds
Started Jun 23 05:56:44 PM PDT 24
Finished Jun 23 05:56:48 PM PDT 24
Peak memory 202068 kb
Host smart-d18b745d-1897-418c-bcf5-16fa75e589a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997643060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2997643060
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1068253965
Short name T27
Test name
Test status
Simulation time 49563916711 ps
CPU time 30.7 seconds
Started Jun 23 05:56:50 PM PDT 24
Finished Jun 23 05:57:21 PM PDT 24
Peak memory 202056 kb
Host smart-9de711c8-f609-4bf8-97b7-b8d981d87f89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068253965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1068253965
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1993578226
Short name T683
Test name
Test status
Simulation time 14684205054 ps
CPU time 34.81 seconds
Started Jun 23 05:56:50 PM PDT 24
Finished Jun 23 05:57:26 PM PDT 24
Peak memory 202356 kb
Host smart-a2de1afe-0f11-4c9e-9d3d-7bc3ef8adbc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993578226 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1993578226
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2784453023
Short name T721
Test name
Test status
Simulation time 385208110 ps
CPU time 0.74 seconds
Started Jun 23 05:57:00 PM PDT 24
Finished Jun 23 05:57:01 PM PDT 24
Peak memory 201956 kb
Host smart-9001c939-d037-4917-9538-bba19f372b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784453023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2784453023
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1983968304
Short name T202
Test name
Test status
Simulation time 169716900657 ps
CPU time 389.82 seconds
Started Jun 23 05:56:54 PM PDT 24
Finished Jun 23 06:03:25 PM PDT 24
Peak memory 202256 kb
Host smart-1ffd6395-79f3-403d-8a6a-1dcac5a67333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983968304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1983968304
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.251283703
Short name T204
Test name
Test status
Simulation time 490567196322 ps
CPU time 1167.55 seconds
Started Jun 23 05:56:50 PM PDT 24
Finished Jun 23 06:16:18 PM PDT 24
Peak memory 202252 kb
Host smart-3e34326f-0efc-4efe-bf55-39430513a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251283703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.251283703
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4203922096
Short name T424
Test name
Test status
Simulation time 165158367931 ps
CPU time 98.49 seconds
Started Jun 23 05:56:50 PM PDT 24
Finished Jun 23 05:58:29 PM PDT 24
Peak memory 202236 kb
Host smart-42acd23f-1ef0-40f3-9661-59f9d0a59362
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203922096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.4203922096
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2383235987
Short name T83
Test name
Test status
Simulation time 160863891208 ps
CPU time 375.02 seconds
Started Jun 23 05:56:50 PM PDT 24
Finished Jun 23 06:03:06 PM PDT 24
Peak memory 202232 kb
Host smart-ad1f5c5d-6e29-4e9a-922a-b9fe934e6bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383235987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2383235987
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.903302033
Short name T90
Test name
Test status
Simulation time 333383158345 ps
CPU time 184.91 seconds
Started Jun 23 05:56:49 PM PDT 24
Finished Jun 23 05:59:55 PM PDT 24
Peak memory 202212 kb
Host smart-009747ea-bb0c-4eb5-aa72-4e98cb4aa29f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=903302033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.903302033
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.418647960
Short name T229
Test name
Test status
Simulation time 172481559722 ps
CPU time 426.35 seconds
Started Jun 23 05:56:52 PM PDT 24
Finished Jun 23 06:03:58 PM PDT 24
Peak memory 202220 kb
Host smart-02eab9b8-4c86-4c22-b97b-abb27831852c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418647960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.418647960
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3614061438
Short name T409
Test name
Test status
Simulation time 197779727873 ps
CPU time 208.82 seconds
Started Jun 23 05:56:49 PM PDT 24
Finished Jun 23 06:00:18 PM PDT 24
Peak memory 202296 kb
Host smart-644902a8-e016-4045-bf86-aeb56b4987a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614061438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3614061438
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.869034341
Short name T183
Test name
Test status
Simulation time 136674118056 ps
CPU time 578.34 seconds
Started Jun 23 05:56:56 PM PDT 24
Finished Jun 23 06:06:35 PM PDT 24
Peak memory 202572 kb
Host smart-621b90bd-376a-460b-8a3c-42bd3e6d6eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869034341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.869034341
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.363768474
Short name T524
Test name
Test status
Simulation time 29536766304 ps
CPU time 27.48 seconds
Started Jun 23 05:56:55 PM PDT 24
Finished Jun 23 05:57:23 PM PDT 24
Peak memory 202116 kb
Host smart-19cc84d5-0883-4428-9531-c39ff7ccbffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363768474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.363768474
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3935826062
Short name T739
Test name
Test status
Simulation time 3606850017 ps
CPU time 2.62 seconds
Started Jun 23 05:56:55 PM PDT 24
Finished Jun 23 05:56:58 PM PDT 24
Peak memory 202244 kb
Host smart-6126875d-dd5e-4830-80da-4396bc4c08b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935826062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3935826062
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3432732855
Short name T528
Test name
Test status
Simulation time 5731470096 ps
CPU time 6.23 seconds
Started Jun 23 05:56:51 PM PDT 24
Finished Jun 23 05:56:57 PM PDT 24
Peak memory 202012 kb
Host smart-9fbf43a9-d098-4811-b13c-df357ffa6906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432732855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3432732855
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.312209705
Short name T278
Test name
Test status
Simulation time 638934590977 ps
CPU time 912.75 seconds
Started Jun 23 05:56:56 PM PDT 24
Finished Jun 23 06:12:10 PM PDT 24
Peak memory 210740 kb
Host smart-35c024b7-844e-48e1-88c4-a3fa0ea7a705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312209705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
312209705
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.85713731
Short name T765
Test name
Test status
Simulation time 1109803341370 ps
CPU time 623.57 seconds
Started Jun 23 05:56:55 PM PDT 24
Finished Jun 23 06:07:19 PM PDT 24
Peak memory 210860 kb
Host smart-d1fc4c1d-51f4-4b0d-b4c5-d608fdf52c2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85713731 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.85713731
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.120073015
Short name T414
Test name
Test status
Simulation time 366155981 ps
CPU time 0.87 seconds
Started Jun 23 05:57:02 PM PDT 24
Finished Jun 23 05:57:03 PM PDT 24
Peak memory 201900 kb
Host smart-4360ce01-6f36-4c4e-ab04-a8093ff2c9db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120073015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.120073015
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.376614530
Short name T94
Test name
Test status
Simulation time 558585438171 ps
CPU time 343.65 seconds
Started Jun 23 05:57:06 PM PDT 24
Finished Jun 23 06:02:50 PM PDT 24
Peak memory 202256 kb
Host smart-cace99f8-fd11-4c39-82e5-73451417ee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376614530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.376614530
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1347172463
Short name T235
Test name
Test status
Simulation time 494818753675 ps
CPU time 288.43 seconds
Started Jun 23 05:56:59 PM PDT 24
Finished Jun 23 06:01:48 PM PDT 24
Peak memory 202208 kb
Host smart-6683f796-9b60-4e5a-bd37-c500bdd6df9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347172463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1347172463
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2898381013
Short name T490
Test name
Test status
Simulation time 161861021981 ps
CPU time 93.42 seconds
Started Jun 23 05:56:58 PM PDT 24
Finished Jun 23 05:58:31 PM PDT 24
Peak memory 202172 kb
Host smart-6b69ee0d-225c-4732-9ba2-63f30d97a5a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898381013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2898381013
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1529516560
Short name T91
Test name
Test status
Simulation time 327348453191 ps
CPU time 762.4 seconds
Started Jun 23 05:56:59 PM PDT 24
Finished Jun 23 06:09:41 PM PDT 24
Peak memory 202340 kb
Host smart-6f780783-97ce-4348-b816-11b7b7d92a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529516560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1529516560
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.859614448
Short name T451
Test name
Test status
Simulation time 160697921894 ps
CPU time 101.55 seconds
Started Jun 23 05:56:59 PM PDT 24
Finished Jun 23 05:58:41 PM PDT 24
Peak memory 202176 kb
Host smart-4cf575b5-cf38-4254-9133-4634d8b977ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=859614448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.859614448
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.33769849
Short name T301
Test name
Test status
Simulation time 193985518366 ps
CPU time 233.45 seconds
Started Jun 23 05:57:00 PM PDT 24
Finished Jun 23 06:00:53 PM PDT 24
Peak memory 202224 kb
Host smart-c2608e3d-8986-4b6b-99bf-798ce038e89f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_w
akeup.33769849
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.958560962
Short name T399
Test name
Test status
Simulation time 196333533405 ps
CPU time 112.01 seconds
Started Jun 23 05:57:03 PM PDT 24
Finished Jun 23 05:58:55 PM PDT 24
Peak memory 202288 kb
Host smart-d215b9ef-d518-4af8-b792-34d4cf12b15b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958560962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.958560962
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.472775182
Short name T662
Test name
Test status
Simulation time 117128977737 ps
CPU time 371.49 seconds
Started Jun 23 05:57:10 PM PDT 24
Finished Jun 23 06:03:22 PM PDT 24
Peak memory 202548 kb
Host smart-e151b852-70c6-4bc2-a749-1e44176e51f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472775182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.472775182
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3829087208
Short name T371
Test name
Test status
Simulation time 39197970558 ps
CPU time 46.2 seconds
Started Jun 23 05:57:05 PM PDT 24
Finished Jun 23 05:57:52 PM PDT 24
Peak memory 202100 kb
Host smart-009a438c-0db5-452e-95bf-3cd8f5ef35fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829087208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3829087208
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.750386545
Short name T745
Test name
Test status
Simulation time 4290212841 ps
CPU time 5.35 seconds
Started Jun 23 05:57:11 PM PDT 24
Finished Jun 23 05:57:17 PM PDT 24
Peak memory 202068 kb
Host smart-3ea86635-753f-49a7-9b07-054c4473d2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750386545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.750386545
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2816437147
Short name T714
Test name
Test status
Simulation time 5862888116 ps
CPU time 13.49 seconds
Started Jun 23 05:57:03 PM PDT 24
Finished Jun 23 05:57:17 PM PDT 24
Peak memory 202060 kb
Host smart-b13b76ed-a0e0-49df-af4f-4331b4a95147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816437147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2816437147
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1850378998
Short name T226
Test name
Test status
Simulation time 270791040216 ps
CPU time 99.07 seconds
Started Jun 23 05:57:11 PM PDT 24
Finished Jun 23 05:58:50 PM PDT 24
Peak memory 202232 kb
Host smart-b14e7fba-abbc-42d5-9959-2ccbdc9dffc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850378998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1850378998
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3020815528
Short name T92
Test name
Test status
Simulation time 354600599 ps
CPU time 0.82 seconds
Started Jun 23 05:57:16 PM PDT 24
Finished Jun 23 05:57:17 PM PDT 24
Peak memory 201904 kb
Host smart-05480a20-2efc-472b-bb11-5beeb3b70fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020815528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3020815528
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.228693040
Short name T334
Test name
Test status
Simulation time 183345381592 ps
CPU time 416.84 seconds
Started Jun 23 05:57:10 PM PDT 24
Finished Jun 23 06:04:07 PM PDT 24
Peak memory 202248 kb
Host smart-2cdaa5d0-c697-437d-aa77-72c75522e2e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228693040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.228693040
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2528946635
Short name T70
Test name
Test status
Simulation time 165666757764 ps
CPU time 91.86 seconds
Started Jun 23 05:57:08 PM PDT 24
Finished Jun 23 05:58:40 PM PDT 24
Peak memory 202228 kb
Host smart-b00ead1b-960f-49c8-8e1a-69d71f69bf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528946635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2528946635
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2812374976
Short name T505
Test name
Test status
Simulation time 496661940772 ps
CPU time 299.33 seconds
Started Jun 23 05:57:07 PM PDT 24
Finished Jun 23 06:02:07 PM PDT 24
Peak memory 202236 kb
Host smart-f4ace2da-f529-4e1a-96d0-1d9041208dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812374976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2812374976
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1485100877
Short name T742
Test name
Test status
Simulation time 160825079382 ps
CPU time 85.08 seconds
Started Jun 23 05:57:08 PM PDT 24
Finished Jun 23 05:58:33 PM PDT 24
Peak memory 202200 kb
Host smart-65ef0a17-7a17-4adf-bfd3-89dcfa3953b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485100877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1485100877
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3390258640
Short name T749
Test name
Test status
Simulation time 329489939370 ps
CPU time 757.02 seconds
Started Jun 23 05:57:05 PM PDT 24
Finished Jun 23 06:09:42 PM PDT 24
Peak memory 202336 kb
Host smart-0d96a44d-b6c8-4add-b4bd-eb80246b5074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390258640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3390258640
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.4066981968
Short name T422
Test name
Test status
Simulation time 486970820337 ps
CPU time 509.75 seconds
Started Jun 23 05:57:07 PM PDT 24
Finished Jun 23 06:05:37 PM PDT 24
Peak memory 202140 kb
Host smart-1f6f54cc-4d38-4dff-ad45-5583c328f3ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066981968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.4066981968
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3203341423
Short name T295
Test name
Test status
Simulation time 418062314508 ps
CPU time 892.53 seconds
Started Jun 23 05:57:03 PM PDT 24
Finished Jun 23 06:11:56 PM PDT 24
Peak memory 202196 kb
Host smart-052fdaec-9f82-42a5-bd79-ce10b6fda5ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203341423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3203341423
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3208617350
Short name T437
Test name
Test status
Simulation time 608374875619 ps
CPU time 722.5 seconds
Started Jun 23 05:57:05 PM PDT 24
Finished Jun 23 06:09:08 PM PDT 24
Peak memory 202308 kb
Host smart-e45a1651-6f4c-4861-99d1-146bcfee4a20
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208617350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3208617350
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1286816744
Short name T740
Test name
Test status
Simulation time 73974178411 ps
CPU time 364.01 seconds
Started Jun 23 05:57:12 PM PDT 24
Finished Jun 23 06:03:16 PM PDT 24
Peak memory 202508 kb
Host smart-ea67a052-111f-4070-9aed-5765d949c20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286816744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1286816744
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.4261735931
Short name T594
Test name
Test status
Simulation time 35672336496 ps
CPU time 76.29 seconds
Started Jun 23 05:57:10 PM PDT 24
Finished Jun 23 05:58:27 PM PDT 24
Peak memory 202100 kb
Host smart-e98fba39-d454-413a-86c4-8be8d3ee2dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261735931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.4261735931
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.4230914675
Short name T101
Test name
Test status
Simulation time 4014601962 ps
CPU time 3.38 seconds
Started Jun 23 05:57:10 PM PDT 24
Finished Jun 23 05:57:14 PM PDT 24
Peak memory 202016 kb
Host smart-97beabe8-6ab8-400f-ac56-1e772a64aac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230914675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.4230914675
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1057868413
Short name T701
Test name
Test status
Simulation time 5941534110 ps
CPU time 7.97 seconds
Started Jun 23 05:57:04 PM PDT 24
Finished Jun 23 05:57:12 PM PDT 24
Peak memory 202240 kb
Host smart-79f86571-ae93-47bd-9a39-54c22ce22091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057868413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1057868413
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.4057040591
Short name T761
Test name
Test status
Simulation time 199197851723 ps
CPU time 415.63 seconds
Started Jun 23 05:57:13 PM PDT 24
Finished Jun 23 06:04:09 PM PDT 24
Peak memory 202260 kb
Host smart-bc2df653-4b16-40fa-bddb-c05e51dc9470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057040591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.4057040591
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1141293519
Short name T343
Test name
Test status
Simulation time 109892187236 ps
CPU time 147.39 seconds
Started Jun 23 05:57:14 PM PDT 24
Finished Jun 23 05:59:42 PM PDT 24
Peak memory 219036 kb
Host smart-0c703c67-e13f-40c1-8c21-26d8810eba50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141293519 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1141293519
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.661217312
Short name T484
Test name
Test status
Simulation time 360727920 ps
CPU time 0.71 seconds
Started Jun 23 05:57:24 PM PDT 24
Finished Jun 23 05:57:25 PM PDT 24
Peak memory 201964 kb
Host smart-bcf06bbe-598a-4876-b66e-5c3a8946b91a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661217312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.661217312
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1808288089
Short name T584
Test name
Test status
Simulation time 164262213340 ps
CPU time 99.8 seconds
Started Jun 23 05:57:20 PM PDT 24
Finished Jun 23 05:59:00 PM PDT 24
Peak memory 202236 kb
Host smart-ea601f5f-6bd3-41c2-b933-1c21be2cdef3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808288089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1808288089
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3805643133
Short name T203
Test name
Test status
Simulation time 165931701744 ps
CPU time 408.41 seconds
Started Jun 23 05:57:18 PM PDT 24
Finished Jun 23 06:04:06 PM PDT 24
Peak memory 202196 kb
Host smart-15773f3a-32c8-4c1a-bc26-ea6711f4acb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805643133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3805643133
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.786038576
Short name T673
Test name
Test status
Simulation time 339185046045 ps
CPU time 783.79 seconds
Started Jun 23 05:57:14 PM PDT 24
Finished Jun 23 06:10:19 PM PDT 24
Peak memory 202244 kb
Host smart-6225b166-6c64-4d39-b191-d886dfd33b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786038576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.786038576
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.177088449
Short name T7
Test name
Test status
Simulation time 492680801142 ps
CPU time 566.17 seconds
Started Jun 23 05:57:19 PM PDT 24
Finished Jun 23 06:06:46 PM PDT 24
Peak memory 202224 kb
Host smart-49925eff-4804-4ffb-a0ec-7c898943c501
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=177088449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.177088449
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2637271533
Short name T786
Test name
Test status
Simulation time 487174983389 ps
CPU time 550.58 seconds
Started Jun 23 05:57:20 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 202296 kb
Host smart-8b6e51af-7ce9-406c-8b36-e7b79855ba1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637271533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2637271533
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.314398981
Short name T258
Test name
Test status
Simulation time 176623678538 ps
CPU time 99.35 seconds
Started Jun 23 05:57:20 PM PDT 24
Finished Jun 23 05:58:59 PM PDT 24
Peak memory 202324 kb
Host smart-cf1d47c6-aaa6-4523-aac6-10502245ea2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314398981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.314398981
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2595936294
Short name T647
Test name
Test status
Simulation time 397292796456 ps
CPU time 113.5 seconds
Started Jun 23 05:57:17 PM PDT 24
Finished Jun 23 05:59:10 PM PDT 24
Peak memory 202224 kb
Host smart-b429ae7d-d923-4dba-b2da-73061c27c6fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595936294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2595936294
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.351250478
Short name T349
Test name
Test status
Simulation time 109542911652 ps
CPU time 364.88 seconds
Started Jun 23 05:57:24 PM PDT 24
Finished Jun 23 06:03:29 PM PDT 24
Peak memory 202644 kb
Host smart-a49b92d9-c563-4aab-910a-c893009e7fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351250478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.351250478
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2340706334
Short name T751
Test name
Test status
Simulation time 31006510613 ps
CPU time 13.37 seconds
Started Jun 23 05:57:25 PM PDT 24
Finished Jun 23 05:57:39 PM PDT 24
Peak memory 202052 kb
Host smart-acf69031-959f-4580-85d8-573eac75d35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340706334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2340706334
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2792587498
Short name T172
Test name
Test status
Simulation time 3561284842 ps
CPU time 9.32 seconds
Started Jun 23 05:57:21 PM PDT 24
Finished Jun 23 05:57:31 PM PDT 24
Peak memory 202076 kb
Host smart-e382b438-e4a3-4c72-8d6a-4b252cd3bcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792587498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2792587498
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1216959506
Short name T354
Test name
Test status
Simulation time 5904670223 ps
CPU time 4.3 seconds
Started Jun 23 05:57:15 PM PDT 24
Finished Jun 23 05:57:20 PM PDT 24
Peak memory 202000 kb
Host smart-baa28a00-a69a-4eed-be73-137a56026231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216959506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1216959506
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1773957931
Short name T718
Test name
Test status
Simulation time 6410679956 ps
CPU time 8.08 seconds
Started Jun 23 05:57:24 PM PDT 24
Finished Jun 23 05:57:32 PM PDT 24
Peak memory 202020 kb
Host smart-828666d4-98f7-406a-9d07-f710f2791179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773957931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1773957931
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2788222536
Short name T691
Test name
Test status
Simulation time 89931838010 ps
CPU time 112.75 seconds
Started Jun 23 05:57:25 PM PDT 24
Finished Jun 23 05:59:18 PM PDT 24
Peak memory 210880 kb
Host smart-436f0176-ebb7-4a90-b993-f7153455606f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788222536 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2788222536
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3756883966
Short name T393
Test name
Test status
Simulation time 466322717 ps
CPU time 1.81 seconds
Started Jun 23 05:57:34 PM PDT 24
Finished Jun 23 05:57:36 PM PDT 24
Peak memory 201884 kb
Host smart-17c6e49a-62ff-4f43-8c83-9e58f6c05eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756883966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3756883966
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1997041460
Short name T595
Test name
Test status
Simulation time 166994810260 ps
CPU time 67.4 seconds
Started Jun 23 05:57:28 PM PDT 24
Finished Jun 23 05:58:36 PM PDT 24
Peak memory 202216 kb
Host smart-881c94a4-769d-406a-b6fa-961722482fe4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997041460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1997041460
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2390221216
Short name T600
Test name
Test status
Simulation time 322874636029 ps
CPU time 172.33 seconds
Started Jun 23 05:57:29 PM PDT 24
Finished Jun 23 06:00:21 PM PDT 24
Peak memory 202204 kb
Host smart-18c61687-3e6f-4ade-8cd4-8311fa3a5a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390221216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2390221216
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2508754473
Short name T513
Test name
Test status
Simulation time 160702640996 ps
CPU time 104.87 seconds
Started Jun 23 05:57:30 PM PDT 24
Finished Jun 23 05:59:16 PM PDT 24
Peak memory 202204 kb
Host smart-e9a62fed-ff26-4075-9857-c8366fdb33ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508754473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2508754473
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1271636571
Short name T545
Test name
Test status
Simulation time 164398813567 ps
CPU time 195.05 seconds
Started Jun 23 05:57:31 PM PDT 24
Finished Jun 23 06:00:47 PM PDT 24
Peak memory 202280 kb
Host smart-3420f152-941e-4805-9895-2c5774d11ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271636571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1271636571
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1505456885
Short name T480
Test name
Test status
Simulation time 327740190498 ps
CPU time 356.46 seconds
Started Jun 23 05:57:30 PM PDT 24
Finished Jun 23 06:03:27 PM PDT 24
Peak memory 202240 kb
Host smart-493cf35c-1ebd-4ef7-9f22-fddf42319782
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505456885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1505456885
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2615738953
Short name T573
Test name
Test status
Simulation time 202543216553 ps
CPU time 67.03 seconds
Started Jun 23 05:57:27 PM PDT 24
Finished Jun 23 05:58:35 PM PDT 24
Peak memory 202224 kb
Host smart-57413d02-1ebc-47f2-be1c-76fbef1a59ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615738953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2615738953
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1824467651
Short name T593
Test name
Test status
Simulation time 77751606898 ps
CPU time 341.64 seconds
Started Jun 23 05:57:34 PM PDT 24
Finished Jun 23 06:03:16 PM PDT 24
Peak memory 202508 kb
Host smart-02405049-42a4-4267-acd8-1c0e899a14c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824467651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1824467651
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.824696764
Short name T423
Test name
Test status
Simulation time 40053541061 ps
CPU time 92.74 seconds
Started Jun 23 05:57:35 PM PDT 24
Finished Jun 23 05:59:08 PM PDT 24
Peak memory 202020 kb
Host smart-42894909-c5e6-48fb-8126-434cb84987d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824696764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.824696764
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1334942890
Short name T466
Test name
Test status
Simulation time 3079439533 ps
CPU time 7.34 seconds
Started Jun 23 05:57:31 PM PDT 24
Finished Jun 23 05:57:39 PM PDT 24
Peak memory 202064 kb
Host smart-2c56e5a1-52c4-4ba9-b6ed-2b3caf6c7bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334942890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1334942890
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3785989060
Short name T365
Test name
Test status
Simulation time 5900985223 ps
CPU time 15.29 seconds
Started Jun 23 05:57:23 PM PDT 24
Finished Jun 23 05:57:38 PM PDT 24
Peak memory 202064 kb
Host smart-588f1a41-2601-4f09-b655-345ed492b119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785989060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3785989060
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1568726835
Short name T575
Test name
Test status
Simulation time 352696086423 ps
CPU time 362.54 seconds
Started Jun 23 05:57:33 PM PDT 24
Finished Jun 23 06:03:36 PM PDT 24
Peak memory 202488 kb
Host smart-75f9bfe4-4276-4977-a598-1a6aa620f23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568726835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1568726835
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2212892529
Short name T288
Test name
Test status
Simulation time 72431360126 ps
CPU time 76.11 seconds
Started Jun 23 05:57:35 PM PDT 24
Finished Jun 23 05:58:51 PM PDT 24
Peak memory 202332 kb
Host smart-8d571921-0aa2-4d2c-bee5-881e060050bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212892529 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2212892529
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2893627710
Short name T793
Test name
Test status
Simulation time 295437778 ps
CPU time 0.88 seconds
Started Jun 23 05:57:48 PM PDT 24
Finished Jun 23 05:57:49 PM PDT 24
Peak memory 202116 kb
Host smart-806a9765-7321-425d-b641-8b130ca03338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893627710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2893627710
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1144083384
Short name T230
Test name
Test status
Simulation time 495147682899 ps
CPU time 1030.48 seconds
Started Jun 23 05:57:43 PM PDT 24
Finished Jun 23 06:14:54 PM PDT 24
Peak memory 202252 kb
Host smart-73c3ce98-57fb-4a56-bceb-3e87fb88ec2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144083384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1144083384
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.4282234320
Short name T68
Test name
Test status
Simulation time 326514566477 ps
CPU time 215.41 seconds
Started Jun 23 05:57:39 PM PDT 24
Finished Jun 23 06:01:15 PM PDT 24
Peak memory 202264 kb
Host smart-70288f7a-1a04-4399-a2c1-c80b7d80ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282234320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.4282234320
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3343672289
Short name T465
Test name
Test status
Simulation time 166084996399 ps
CPU time 99.09 seconds
Started Jun 23 05:57:44 PM PDT 24
Finished Jun 23 05:59:24 PM PDT 24
Peak memory 202212 kb
Host smart-2ef17a5b-40d8-4209-946b-74a90dba5c6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343672289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3343672289
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1042310920
Short name T534
Test name
Test status
Simulation time 328189577591 ps
CPU time 186.3 seconds
Started Jun 23 05:57:39 PM PDT 24
Finished Jun 23 06:00:46 PM PDT 24
Peak memory 202304 kb
Host smart-432d48a7-627b-4973-b894-842ecb0b98f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042310920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1042310920
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.618998653
Short name T572
Test name
Test status
Simulation time 487427881834 ps
CPU time 1117.22 seconds
Started Jun 23 05:57:38 PM PDT 24
Finished Jun 23 06:16:16 PM PDT 24
Peak memory 202196 kb
Host smart-693d775e-675c-4998-bf40-91261ec85702
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=618998653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.618998653
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.60674979
Short name T287
Test name
Test status
Simulation time 607765049518 ps
CPU time 362.17 seconds
Started Jun 23 05:57:47 PM PDT 24
Finished Jun 23 06:03:50 PM PDT 24
Peak memory 202308 kb
Host smart-cd748132-76b8-4d43-b3be-18d68f6dc8fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60674979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_w
akeup.60674979
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3027967896
Short name T492
Test name
Test status
Simulation time 601394225241 ps
CPU time 113.78 seconds
Started Jun 23 05:57:44 PM PDT 24
Finished Jun 23 05:59:38 PM PDT 24
Peak memory 202184 kb
Host smart-77de1fb7-7b14-45ab-84c6-b17f39ebbbd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027967896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3027967896
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2989437880
Short name T196
Test name
Test status
Simulation time 137163784240 ps
CPU time 479.58 seconds
Started Jun 23 05:57:43 PM PDT 24
Finished Jun 23 06:05:43 PM PDT 24
Peak memory 202556 kb
Host smart-4ea72cfe-dace-45a9-8328-e80fc50902f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989437880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2989437880
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1936798302
Short name T617
Test name
Test status
Simulation time 31201120984 ps
CPU time 19.42 seconds
Started Jun 23 05:57:47 PM PDT 24
Finished Jun 23 05:58:07 PM PDT 24
Peak memory 202092 kb
Host smart-4dae3926-5469-42ec-936b-b78954be4f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936798302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1936798302
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.532293228
Short name T665
Test name
Test status
Simulation time 3820193542 ps
CPU time 1.71 seconds
Started Jun 23 05:57:44 PM PDT 24
Finished Jun 23 05:57:46 PM PDT 24
Peak memory 202016 kb
Host smart-ef25f22e-cd4a-4b76-8956-2abccffbcffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532293228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.532293228
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1124364300
Short name T555
Test name
Test status
Simulation time 6033022195 ps
CPU time 7.51 seconds
Started Jun 23 05:57:40 PM PDT 24
Finished Jun 23 05:57:48 PM PDT 24
Peak memory 202060 kb
Host smart-edb63b64-de93-4600-bbed-381081995f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124364300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1124364300
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.136835033
Short name T20
Test name
Test status
Simulation time 103818103574 ps
CPU time 99.82 seconds
Started Jun 23 05:57:50 PM PDT 24
Finished Jun 23 05:59:30 PM PDT 24
Peak memory 210808 kb
Host smart-d932f6bf-7c9d-426b-8b8c-9a08446329f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136835033 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.136835033
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3046382763
Short name T373
Test name
Test status
Simulation time 495038076 ps
CPU time 1.26 seconds
Started Jun 23 05:58:00 PM PDT 24
Finished Jun 23 05:58:02 PM PDT 24
Peak memory 201972 kb
Host smart-85c307f4-9fca-4b7c-87cc-ade9944263b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046382763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3046382763
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.909584582
Short name T221
Test name
Test status
Simulation time 159854433081 ps
CPU time 90.91 seconds
Started Jun 23 05:57:55 PM PDT 24
Finished Jun 23 05:59:26 PM PDT 24
Peak memory 202200 kb
Host smart-9a509605-65c7-4901-bacf-338a05813208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909584582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.909584582
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.132878627
Short name T132
Test name
Test status
Simulation time 167303913359 ps
CPU time 390.53 seconds
Started Jun 23 05:57:51 PM PDT 24
Finished Jun 23 06:04:22 PM PDT 24
Peak memory 202264 kb
Host smart-eaa6622d-ed30-4278-bcf6-bc19993852bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132878627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.132878627
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.729444440
Short name T652
Test name
Test status
Simulation time 498229560399 ps
CPU time 1195.99 seconds
Started Jun 23 05:57:50 PM PDT 24
Finished Jun 23 06:17:47 PM PDT 24
Peak memory 202284 kb
Host smart-a6a9f84a-f0eb-4de8-9db5-6c4e3639cb76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=729444440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.729444440
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.743886298
Short name T586
Test name
Test status
Simulation time 163739022532 ps
CPU time 79.63 seconds
Started Jun 23 05:57:50 PM PDT 24
Finished Jun 23 05:59:11 PM PDT 24
Peak memory 202280 kb
Host smart-f009242c-2cce-4d14-8083-2fe0cd949a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743886298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.743886298
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3056598996
Short name T796
Test name
Test status
Simulation time 323976505190 ps
CPU time 790.29 seconds
Started Jun 23 05:57:51 PM PDT 24
Finished Jun 23 06:11:01 PM PDT 24
Peak memory 202224 kb
Host smart-d44b242c-0d2b-4ade-a2c1-4d13d93380ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056598996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3056598996
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1300166557
Short name T134
Test name
Test status
Simulation time 170953563598 ps
CPU time 28.8 seconds
Started Jun 23 05:57:56 PM PDT 24
Finished Jun 23 05:58:25 PM PDT 24
Peak memory 202244 kb
Host smart-06b76a5f-57cf-4c3e-b49c-8bb49ac9f43f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300166557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1300166557
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3608659960
Short name T432
Test name
Test status
Simulation time 406536080981 ps
CPU time 244.82 seconds
Started Jun 23 05:57:54 PM PDT 24
Finished Jun 23 06:02:00 PM PDT 24
Peak memory 202168 kb
Host smart-661e3a0d-35e1-4d45-8266-18085c2b8cf3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608659960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3608659960
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2549907541
Short name T658
Test name
Test status
Simulation time 127197481966 ps
CPU time 450.51 seconds
Started Jun 23 05:57:54 PM PDT 24
Finished Jun 23 06:05:25 PM PDT 24
Peak memory 202572 kb
Host smart-c2be515d-e756-4122-bd6e-4f6815392957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549907541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2549907541
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3885667701
Short name T180
Test name
Test status
Simulation time 43787568089 ps
CPU time 74.99 seconds
Started Jun 23 05:57:57 PM PDT 24
Finished Jun 23 05:59:12 PM PDT 24
Peak memory 202092 kb
Host smart-7f3af73a-cd31-40ee-90e6-d9d7ef2206cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885667701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3885667701
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.139455481
Short name T418
Test name
Test status
Simulation time 5477602726 ps
CPU time 7.14 seconds
Started Jun 23 05:57:54 PM PDT 24
Finished Jun 23 05:58:01 PM PDT 24
Peak memory 202056 kb
Host smart-81b886c1-e752-4703-800b-deabc7cd1943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139455481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.139455481
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.266237944
Short name T99
Test name
Test status
Simulation time 5656874948 ps
CPU time 14.93 seconds
Started Jun 23 05:57:48 PM PDT 24
Finished Jun 23 05:58:03 PM PDT 24
Peak memory 202068 kb
Host smart-7e640927-ba80-4307-955a-1b9836ba02dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266237944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.266237944
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1523771141
Short name T182
Test name
Test status
Simulation time 309737779995 ps
CPU time 565.59 seconds
Started Jun 23 05:57:54 PM PDT 24
Finished Jun 23 06:07:20 PM PDT 24
Peak memory 212556 kb
Host smart-3a587381-0a47-454f-ae36-b2fe6645ef7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523771141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1523771141
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1757521031
Short name T6
Test name
Test status
Simulation time 73230595455 ps
CPU time 67.11 seconds
Started Jun 23 05:57:54 PM PDT 24
Finished Jun 23 05:59:01 PM PDT 24
Peak memory 210884 kb
Host smart-113403cc-fd1b-408d-830b-b43138da7823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757521031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1757521031
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3245370934
Short name T636
Test name
Test status
Simulation time 530412481 ps
CPU time 0.82 seconds
Started Jun 23 05:58:09 PM PDT 24
Finished Jun 23 05:58:10 PM PDT 24
Peak memory 201960 kb
Host smart-92e24b17-2b4c-42d6-8c33-7cdcd90fc716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245370934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3245370934
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3741395747
Short name T663
Test name
Test status
Simulation time 505697464537 ps
CPU time 305.48 seconds
Started Jun 23 05:58:02 PM PDT 24
Finished Jun 23 06:03:08 PM PDT 24
Peak memory 202492 kb
Host smart-dd8681ee-e9b9-4e3c-bf80-c215c7ed13f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741395747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3741395747
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1550421290
Short name T291
Test name
Test status
Simulation time 490677120349 ps
CPU time 1137.98 seconds
Started Jun 23 05:58:00 PM PDT 24
Finished Jun 23 06:16:59 PM PDT 24
Peak memory 202204 kb
Host smart-e83564c4-20bf-4602-98ee-60ef992a94d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550421290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1550421290
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2959987551
Short name T596
Test name
Test status
Simulation time 510090475483 ps
CPU time 572.11 seconds
Started Jun 23 05:58:00 PM PDT 24
Finished Jun 23 06:07:33 PM PDT 24
Peak memory 202236 kb
Host smart-4d28f4ea-7da3-4757-a29b-cbcb44bca986
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959987551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2959987551
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.70653818
Short name T587
Test name
Test status
Simulation time 161147504191 ps
CPU time 69.68 seconds
Started Jun 23 05:58:00 PM PDT 24
Finished Jun 23 05:59:10 PM PDT 24
Peak memory 202292 kb
Host smart-f83cc8ce-66f0-4b76-ada1-8b1431100000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70653818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.70653818
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.350091858
Short name T420
Test name
Test status
Simulation time 335387050602 ps
CPU time 64.35 seconds
Started Jun 23 05:57:58 PM PDT 24
Finished Jun 23 05:59:02 PM PDT 24
Peak memory 202292 kb
Host smart-3816b0e9-f853-4e4a-9123-60a390402017
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=350091858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.350091858
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3389631151
Short name T141
Test name
Test status
Simulation time 516076804648 ps
CPU time 84.06 seconds
Started Jun 23 05:58:02 PM PDT 24
Finished Jun 23 05:59:26 PM PDT 24
Peak memory 202324 kb
Host smart-fac2cc8a-03b7-4d1c-b285-8ee9f36c91ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389631151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3389631151
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2378737439
Short name T168
Test name
Test status
Simulation time 407002684591 ps
CPU time 221.7 seconds
Started Jun 23 05:58:03 PM PDT 24
Finished Jun 23 06:01:45 PM PDT 24
Peak memory 202316 kb
Host smart-c65b53ca-0d77-419c-b130-78ed4d3ce97e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378737439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2378737439
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.4235457751
Short name T626
Test name
Test status
Simulation time 119328516562 ps
CPU time 656.1 seconds
Started Jun 23 05:58:07 PM PDT 24
Finished Jun 23 06:09:04 PM PDT 24
Peak memory 202780 kb
Host smart-e4be5259-535f-4bc5-b706-258c7c8bab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235457751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.4235457751
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1723362764
Short name T415
Test name
Test status
Simulation time 23340224953 ps
CPU time 9.06 seconds
Started Jun 23 05:58:09 PM PDT 24
Finished Jun 23 05:58:18 PM PDT 24
Peak memory 202024 kb
Host smart-189f483e-9271-4d95-8dd2-77c1709029b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723362764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1723362764
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1144411877
Short name T169
Test name
Test status
Simulation time 3733503563 ps
CPU time 2.67 seconds
Started Jun 23 05:58:07 PM PDT 24
Finished Jun 23 05:58:10 PM PDT 24
Peak memory 202028 kb
Host smart-38113a81-580f-4cf0-b774-013234404098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144411877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1144411877
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.673231312
Short name T526
Test name
Test status
Simulation time 5941932760 ps
CPU time 5.13 seconds
Started Jun 23 05:57:59 PM PDT 24
Finished Jun 23 05:58:04 PM PDT 24
Peak memory 202048 kb
Host smart-47610059-3713-4256-8c53-df1a6c41b03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673231312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.673231312
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.4283288667
Short name T350
Test name
Test status
Simulation time 294169187487 ps
CPU time 447.71 seconds
Started Jun 23 05:58:10 PM PDT 24
Finished Jun 23 06:05:38 PM PDT 24
Peak memory 202548 kb
Host smart-43279c3f-2d07-4eac-aac6-9a58f5a61047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283288667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.4283288667
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3162387415
Short name T569
Test name
Test status
Simulation time 463317519 ps
CPU time 0.79 seconds
Started Jun 23 05:55:08 PM PDT 24
Finished Jun 23 05:55:09 PM PDT 24
Peak memory 202120 kb
Host smart-4b0a053a-a382-4919-9693-579078400c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162387415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3162387415
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2386434883
Short name T144
Test name
Test status
Simulation time 332996562127 ps
CPU time 784.5 seconds
Started Jun 23 05:55:08 PM PDT 24
Finished Jun 23 06:08:13 PM PDT 24
Peak memory 202172 kb
Host smart-cf2608ca-8432-4716-839a-8698408f8f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386434883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2386434883
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3317712241
Short name T102
Test name
Test status
Simulation time 331898278502 ps
CPU time 171.02 seconds
Started Jun 23 05:55:09 PM PDT 24
Finished Jun 23 05:58:01 PM PDT 24
Peak memory 202264 kb
Host smart-60945f14-c2db-406d-9dd6-129f3aacf66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317712241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3317712241
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2894748600
Short name T446
Test name
Test status
Simulation time 497325073104 ps
CPU time 1124.12 seconds
Started Jun 23 05:55:10 PM PDT 24
Finished Jun 23 06:13:54 PM PDT 24
Peak memory 202248 kb
Host smart-40bb0224-a56e-4762-aa1d-6dac29ece87e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894748600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2894748600
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4179881870
Short name T11
Test name
Test status
Simulation time 324544055514 ps
CPU time 712.93 seconds
Started Jun 23 05:55:09 PM PDT 24
Finished Jun 23 06:07:02 PM PDT 24
Peak memory 202256 kb
Host smart-46f653f1-b432-4956-9317-2c64cf45490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179881870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4179881870
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2124736884
Short name T392
Test name
Test status
Simulation time 166646105622 ps
CPU time 363.83 seconds
Started Jun 23 05:55:10 PM PDT 24
Finished Jun 23 06:01:15 PM PDT 24
Peak memory 202228 kb
Host smart-bebe362d-d846-4c4d-9c43-17cfe85f21ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124736884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2124736884
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2237555849
Short name T227
Test name
Test status
Simulation time 533755235710 ps
CPU time 1281.4 seconds
Started Jun 23 05:55:11 PM PDT 24
Finished Jun 23 06:16:33 PM PDT 24
Peak memory 202232 kb
Host smart-32405b2f-88a3-469c-a5f1-7694ef4b505d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237555849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2237555849
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3607052095
Short name T391
Test name
Test status
Simulation time 600587407646 ps
CPU time 451.01 seconds
Started Jun 23 05:55:08 PM PDT 24
Finished Jun 23 06:02:39 PM PDT 24
Peak memory 202296 kb
Host smart-a81c5f19-a209-4f47-95ef-a3b82d265831
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607052095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3607052095
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.377177535
Short name T37
Test name
Test status
Simulation time 108293377702 ps
CPU time 589.77 seconds
Started Jun 23 05:55:10 PM PDT 24
Finished Jun 23 06:05:01 PM PDT 24
Peak memory 202612 kb
Host smart-f679e127-6bf5-402e-b54a-b8c7962cc043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377177535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.377177535
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.260014414
Short name T710
Test name
Test status
Simulation time 29988725777 ps
CPU time 7.38 seconds
Started Jun 23 05:55:11 PM PDT 24
Finished Jun 23 05:55:19 PM PDT 24
Peak memory 202076 kb
Host smart-7d8e46b5-f20e-4458-9b4c-826b9aafc0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260014414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.260014414
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1078701092
Short name T95
Test name
Test status
Simulation time 3076707633 ps
CPU time 7.6 seconds
Started Jun 23 05:55:10 PM PDT 24
Finished Jun 23 05:55:18 PM PDT 24
Peak memory 202076 kb
Host smart-f0eba9d2-7fed-4c47-91f0-20ae25390f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078701092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1078701092
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.890614151
Short name T66
Test name
Test status
Simulation time 4096196199 ps
CPU time 10.33 seconds
Started Jun 23 05:55:09 PM PDT 24
Finished Jun 23 05:55:20 PM PDT 24
Peak memory 217900 kb
Host smart-f3329663-f39c-4a82-9592-be86a13fe3d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890614151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.890614151
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3151419187
Short name T375
Test name
Test status
Simulation time 5980346908 ps
CPU time 9.41 seconds
Started Jun 23 05:55:14 PM PDT 24
Finished Jun 23 05:55:24 PM PDT 24
Peak memory 202072 kb
Host smart-4c5fc497-c0ba-480b-bd0f-c7d0a1eac72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151419187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3151419187
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4095605604
Short name T282
Test name
Test status
Simulation time 329100103982 ps
CPU time 702.03 seconds
Started Jun 23 05:55:12 PM PDT 24
Finished Jun 23 06:06:54 PM PDT 24
Peak memory 202216 kb
Host smart-078cd83f-c4b3-439c-94e7-509db36acd29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095605604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4095605604
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.418077023
Short name T728
Test name
Test status
Simulation time 454561167 ps
CPU time 1.64 seconds
Started Jun 23 05:58:22 PM PDT 24
Finished Jun 23 05:58:24 PM PDT 24
Peak memory 201924 kb
Host smart-7dc3b248-245b-4c7e-b45f-b348133ec427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418077023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.418077023
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1575269707
Short name T337
Test name
Test status
Simulation time 491588205686 ps
CPU time 1201.31 seconds
Started Jun 23 05:58:13 PM PDT 24
Finished Jun 23 06:18:15 PM PDT 24
Peak memory 202212 kb
Host smart-92f4f648-ec54-4eb7-87ff-43ceed1939a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575269707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1575269707
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3519462546
Short name T614
Test name
Test status
Simulation time 492164550387 ps
CPU time 977.99 seconds
Started Jun 23 05:58:11 PM PDT 24
Finished Jun 23 06:14:30 PM PDT 24
Peak memory 202144 kb
Host smart-1667592c-83f6-44e0-a2eb-cf5f95da2834
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519462546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3519462546
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.4141125314
Short name T273
Test name
Test status
Simulation time 334243448159 ps
CPU time 197.05 seconds
Started Jun 23 05:58:09 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 202328 kb
Host smart-bd8aa3bf-7ac7-48e0-8a93-f9534a1b376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141125314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.4141125314
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2059468345
Short name T507
Test name
Test status
Simulation time 490835143591 ps
CPU time 282.26 seconds
Started Jun 23 05:58:12 PM PDT 24
Finished Jun 23 06:02:55 PM PDT 24
Peak memory 202312 kb
Host smart-29c9b708-6547-4fc4-81e5-958d8a12a413
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059468345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2059468345
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2986369971
Short name T768
Test name
Test status
Simulation time 202600144012 ps
CPU time 122.69 seconds
Started Jun 23 05:58:13 PM PDT 24
Finished Jun 23 06:00:15 PM PDT 24
Peak memory 202312 kb
Host smart-f0444c12-d070-410e-b8ad-7bf7e0cbab1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986369971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2986369971
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2252940306
Short name T743
Test name
Test status
Simulation time 626876177305 ps
CPU time 195.07 seconds
Started Jun 23 05:58:13 PM PDT 24
Finished Jun 23 06:01:29 PM PDT 24
Peak memory 202140 kb
Host smart-abcd900b-75b6-4e41-8b42-5fd7074db43d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252940306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2252940306
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.446220418
Short name T353
Test name
Test status
Simulation time 104887182499 ps
CPU time 349.62 seconds
Started Jun 23 05:58:15 PM PDT 24
Finished Jun 23 06:04:04 PM PDT 24
Peak memory 202708 kb
Host smart-3e602e2f-6e0d-4fb5-b7bf-36ddd7862dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446220418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.446220418
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.265437484
Short name T609
Test name
Test status
Simulation time 27014285142 ps
CPU time 63.01 seconds
Started Jun 23 05:58:17 PM PDT 24
Finished Jun 23 05:59:21 PM PDT 24
Peak memory 202076 kb
Host smart-09eabe36-c9ac-4c6d-8ae6-bdbb3df8598b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265437484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.265437484
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2040060279
Short name T359
Test name
Test status
Simulation time 3562023609 ps
CPU time 9.76 seconds
Started Jun 23 05:58:14 PM PDT 24
Finished Jun 23 05:58:24 PM PDT 24
Peak memory 202016 kb
Host smart-93c8f6cb-81a2-4727-91ed-d42e378d3ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040060279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2040060279
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3000624283
Short name T514
Test name
Test status
Simulation time 5909296433 ps
CPU time 7.1 seconds
Started Jun 23 05:58:09 PM PDT 24
Finished Jun 23 05:58:16 PM PDT 24
Peak memory 202028 kb
Host smart-03028793-4ee6-4d36-8b96-82174a70bf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000624283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3000624283
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.4167965132
Short name T129
Test name
Test status
Simulation time 506219172750 ps
CPU time 1072.31 seconds
Started Jun 23 05:58:23 PM PDT 24
Finished Jun 23 06:16:16 PM PDT 24
Peak memory 202240 kb
Host smart-7062eb1c-6bb7-4991-8146-23ffdfd110e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167965132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.4167965132
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2355696568
Short name T19
Test name
Test status
Simulation time 240929631326 ps
CPU time 213.63 seconds
Started Jun 23 05:58:23 PM PDT 24
Finished Jun 23 06:01:57 PM PDT 24
Peak memory 210964 kb
Host smart-347da5f1-eb75-47da-80d8-40ce66c0d9e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355696568 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2355696568
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1247410901
Short name T732
Test name
Test status
Simulation time 319940078 ps
CPU time 1.32 seconds
Started Jun 23 05:58:35 PM PDT 24
Finished Jun 23 05:58:37 PM PDT 24
Peak memory 201948 kb
Host smart-f27cfe62-336e-4317-a5db-de2728c371b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247410901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1247410901
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2209374552
Short name T160
Test name
Test status
Simulation time 508583728999 ps
CPU time 160.76 seconds
Started Jun 23 05:58:28 PM PDT 24
Finished Jun 23 06:01:09 PM PDT 24
Peak memory 202252 kb
Host smart-0f22178f-0d8f-4198-84d0-e87a2eb4417f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209374552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2209374552
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3921274401
Short name T471
Test name
Test status
Simulation time 333989865031 ps
CPU time 786.82 seconds
Started Jun 23 05:58:29 PM PDT 24
Finished Jun 23 06:11:37 PM PDT 24
Peak memory 202292 kb
Host smart-0656b8c7-aba5-477f-a55b-5632ac721f0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921274401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3921274401
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3043609354
Short name T438
Test name
Test status
Simulation time 166290320074 ps
CPU time 100.6 seconds
Started Jun 23 05:58:23 PM PDT 24
Finished Jun 23 06:00:04 PM PDT 24
Peak memory 202152 kb
Host smart-ff75f16c-761c-4fc8-ae52-f4b32069cb6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043609354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3043609354
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2160312459
Short name T591
Test name
Test status
Simulation time 615198212545 ps
CPU time 739.56 seconds
Started Jun 23 05:58:31 PM PDT 24
Finished Jun 23 06:10:51 PM PDT 24
Peak memory 202312 kb
Host smart-1969ddb6-3657-4eda-b53a-a03ea2e3734b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160312459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2160312459
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1481287842
Short name T41
Test name
Test status
Simulation time 99919315147 ps
CPU time 538.7 seconds
Started Jun 23 05:58:32 PM PDT 24
Finished Jun 23 06:07:31 PM PDT 24
Peak memory 202600 kb
Host smart-bdaf36c6-e60b-4232-b82a-69b2be081224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481287842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1481287842
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2065581272
Short name T557
Test name
Test status
Simulation time 31322975049 ps
CPU time 18.24 seconds
Started Jun 23 05:58:34 PM PDT 24
Finished Jun 23 05:58:53 PM PDT 24
Peak memory 202100 kb
Host smart-eba8c7db-a8cf-47c8-ab1b-2e926f556e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065581272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2065581272
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3775819873
Short name T700
Test name
Test status
Simulation time 4740072838 ps
CPU time 11.78 seconds
Started Jun 23 05:58:32 PM PDT 24
Finished Jun 23 05:58:44 PM PDT 24
Peak memory 202020 kb
Host smart-6fd4f1f5-362e-467b-a434-266912e02285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775819873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3775819873
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1865498995
Short name T454
Test name
Test status
Simulation time 5721143638 ps
CPU time 3.92 seconds
Started Jun 23 05:58:20 PM PDT 24
Finished Jun 23 05:58:25 PM PDT 24
Peak memory 202004 kb
Host smart-a8ce46c4-e8a9-40dd-a031-81e79f6230a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865498995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1865498995
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2487036674
Short name T509
Test name
Test status
Simulation time 168204092603 ps
CPU time 573.13 seconds
Started Jun 23 05:58:39 PM PDT 24
Finished Jun 23 06:08:12 PM PDT 24
Peak memory 210972 kb
Host smart-77d20a17-0795-42f0-aedd-0972b2f2c141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487036674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2487036674
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1086944774
Short name T772
Test name
Test status
Simulation time 265928922218 ps
CPU time 683.04 seconds
Started Jun 23 05:58:31 PM PDT 24
Finished Jun 23 06:09:54 PM PDT 24
Peak memory 210952 kb
Host smart-8a081c28-0ca3-43a8-8cb9-7a631e33c133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086944774 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1086944774
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1070636838
Short name T681
Test name
Test status
Simulation time 459790704 ps
CPU time 0.74 seconds
Started Jun 23 05:58:47 PM PDT 24
Finished Jun 23 05:58:48 PM PDT 24
Peak memory 201956 kb
Host smart-87a46ae9-8aac-436a-8be5-177ab270539c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070636838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1070636838
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1942084967
Short name T779
Test name
Test status
Simulation time 176444712075 ps
CPU time 417.63 seconds
Started Jun 23 05:58:42 PM PDT 24
Finished Jun 23 06:05:40 PM PDT 24
Peak memory 202272 kb
Host smart-3be7e9d4-02f3-4cbb-a918-d51bc9f873a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942084967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1942084967
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.498604537
Short name T738
Test name
Test status
Simulation time 335410771271 ps
CPU time 733.91 seconds
Started Jun 23 05:58:37 PM PDT 24
Finished Jun 23 06:10:51 PM PDT 24
Peak memory 202264 kb
Host smart-c2118b3d-761a-4de6-be29-07bab5c71002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498604537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.498604537
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3452458872
Short name T421
Test name
Test status
Simulation time 336109311799 ps
CPU time 194.71 seconds
Started Jun 23 05:58:37 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 202216 kb
Host smart-31a84824-fd64-43c4-ad42-eedbc141be3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452458872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3452458872
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1150888480
Short name T754
Test name
Test status
Simulation time 163384806783 ps
CPU time 99.44 seconds
Started Jun 23 05:58:38 PM PDT 24
Finished Jun 23 06:00:17 PM PDT 24
Peak memory 202340 kb
Host smart-b6eea3ac-416e-46c2-bc3f-fbbee5b3781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150888480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1150888480
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2994724473
Short name T639
Test name
Test status
Simulation time 322452924925 ps
CPU time 764.38 seconds
Started Jun 23 05:58:39 PM PDT 24
Finished Jun 23 06:11:24 PM PDT 24
Peak memory 202312 kb
Host smart-db4f609a-f04a-4567-b8a8-ccaee92a1cf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994724473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2994724473
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3860816339
Short name T690
Test name
Test status
Simulation time 415875321807 ps
CPU time 167.2 seconds
Started Jun 23 05:58:39 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 202204 kb
Host smart-5bcfce51-2a7f-463c-a2aa-3e3f641a118e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860816339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3860816339
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3163531947
Short name T434
Test name
Test status
Simulation time 629938708229 ps
CPU time 375.66 seconds
Started Jun 23 05:58:42 PM PDT 24
Finished Jun 23 06:04:58 PM PDT 24
Peak memory 202252 kb
Host smart-d7de9cec-76c5-4d41-b763-195fa97361b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163531947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3163531947
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2878093465
Short name T677
Test name
Test status
Simulation time 114513939417 ps
CPU time 589.41 seconds
Started Jun 23 05:58:46 PM PDT 24
Finished Jun 23 06:08:36 PM PDT 24
Peak memory 202604 kb
Host smart-46df9f63-b5a1-4987-afdb-27e9049fe087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878093465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2878093465
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3104463358
Short name T450
Test name
Test status
Simulation time 26194194107 ps
CPU time 16.71 seconds
Started Jun 23 05:58:40 PM PDT 24
Finished Jun 23 05:58:57 PM PDT 24
Peak memory 202080 kb
Host smart-93e033fb-c8ac-4d91-b177-4a8dd5824e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104463358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3104463358
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3592466749
Short name T667
Test name
Test status
Simulation time 4518517583 ps
CPU time 10.1 seconds
Started Jun 23 05:58:41 PM PDT 24
Finished Jun 23 05:58:52 PM PDT 24
Peak memory 202228 kb
Host smart-a2650fa7-9bd4-4c3d-a9fb-cc9a5d5e3be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592466749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3592466749
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.302155284
Short name T529
Test name
Test status
Simulation time 5788364316 ps
CPU time 13.88 seconds
Started Jun 23 05:58:36 PM PDT 24
Finished Jun 23 05:58:50 PM PDT 24
Peak memory 201996 kb
Host smart-d7ca1483-6e5b-45f2-8f97-268232e94530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302155284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.302155284
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.603475680
Short name T145
Test name
Test status
Simulation time 408857133032 ps
CPU time 822.01 seconds
Started Jun 23 05:58:45 PM PDT 24
Finished Jun 23 06:12:27 PM PDT 24
Peak memory 210840 kb
Host smart-57865b33-6aa0-45ed-928a-5be9c85915bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603475680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
603475680
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3762020594
Short name T624
Test name
Test status
Simulation time 410183800 ps
CPU time 1.4 seconds
Started Jun 23 05:58:55 PM PDT 24
Finished Jun 23 05:58:56 PM PDT 24
Peak memory 201940 kb
Host smart-e3f98b88-29bc-4269-afa8-00fdbfcdda6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762020594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3762020594
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2564923809
Short name T217
Test name
Test status
Simulation time 327943455115 ps
CPU time 374.66 seconds
Started Jun 23 05:58:49 PM PDT 24
Finished Jun 23 06:05:04 PM PDT 24
Peak memory 202200 kb
Host smart-342973a4-e425-4102-bcb5-e956095205ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564923809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2564923809
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1860674002
Short name T209
Test name
Test status
Simulation time 180546535459 ps
CPU time 50.48 seconds
Started Jun 23 05:58:51 PM PDT 24
Finished Jun 23 05:59:42 PM PDT 24
Peak memory 202252 kb
Host smart-17ac89cb-14b1-44c6-9940-804107c9b0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860674002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1860674002
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3095503375
Short name T781
Test name
Test status
Simulation time 165600292114 ps
CPU time 406.39 seconds
Started Jun 23 05:58:51 PM PDT 24
Finished Jun 23 06:05:38 PM PDT 24
Peak memory 202260 kb
Host smart-aeea0bd5-0de8-49ef-af5a-8e12118537ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095503375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3095503375
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2787808681
Short name T504
Test name
Test status
Simulation time 330745546511 ps
CPU time 106.17 seconds
Started Jun 23 05:58:52 PM PDT 24
Finished Jun 23 06:00:38 PM PDT 24
Peak memory 202148 kb
Host smart-86fe2397-4976-43df-ab7e-f91ce1331aef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787808681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2787808681
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1271341311
Short name T249
Test name
Test status
Simulation time 167917231202 ps
CPU time 96.52 seconds
Started Jun 23 05:58:51 PM PDT 24
Finished Jun 23 06:00:28 PM PDT 24
Peak memory 202252 kb
Host smart-4f30337f-158e-49bd-a587-5d23b9d3c28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271341311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1271341311
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.499829865
Short name T631
Test name
Test status
Simulation time 160907828965 ps
CPU time 98.61 seconds
Started Jun 23 05:58:52 PM PDT 24
Finished Jun 23 06:00:30 PM PDT 24
Peak memory 202172 kb
Host smart-a925e696-4449-449f-8a22-371670b5ecdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=499829865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.499829865
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2937907446
Short name T159
Test name
Test status
Simulation time 580239298407 ps
CPU time 237.96 seconds
Started Jun 23 05:58:54 PM PDT 24
Finished Jun 23 06:02:52 PM PDT 24
Peak memory 202200 kb
Host smart-3d4a9c0e-3613-4872-9538-dca6388dc561
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937907446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2937907446
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3016411666
Short name T598
Test name
Test status
Simulation time 395560236291 ps
CPU time 877.41 seconds
Started Jun 23 05:58:54 PM PDT 24
Finished Jun 23 06:13:32 PM PDT 24
Peak memory 202208 kb
Host smart-709a60c5-162a-4ad4-9308-2c14c69df57d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016411666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3016411666
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1190433256
Short name T518
Test name
Test status
Simulation time 23936305961 ps
CPU time 24.8 seconds
Started Jun 23 05:58:56 PM PDT 24
Finished Jun 23 05:59:22 PM PDT 24
Peak memory 202068 kb
Host smart-3043a661-1147-43bc-8f3b-2ea16f65d562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190433256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1190433256
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.787240912
Short name T771
Test name
Test status
Simulation time 5121926560 ps
CPU time 12.41 seconds
Started Jun 23 05:58:55 PM PDT 24
Finished Jun 23 05:59:08 PM PDT 24
Peak memory 202020 kb
Host smart-72630764-4d66-4318-b7ab-b3266807afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787240912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.787240912
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1024492878
Short name T361
Test name
Test status
Simulation time 5607197130 ps
CPU time 3.98 seconds
Started Jun 23 05:58:43 PM PDT 24
Finished Jun 23 05:58:48 PM PDT 24
Peak memory 202068 kb
Host smart-b5198dd5-ba44-42dc-8cc5-fbad67d7e32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024492878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1024492878
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.4222228137
Short name T762
Test name
Test status
Simulation time 466686776429 ps
CPU time 1469.66 seconds
Started Jun 23 05:58:53 PM PDT 24
Finished Jun 23 06:23:23 PM PDT 24
Peak memory 210816 kb
Host smart-98230e6d-cbab-4c90-9148-35641c4d296f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222228137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.4222228137
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1427640644
Short name T430
Test name
Test status
Simulation time 539866312 ps
CPU time 0.9 seconds
Started Jun 23 05:59:10 PM PDT 24
Finished Jun 23 05:59:12 PM PDT 24
Peak memory 201960 kb
Host smart-c01439c6-6e00-45ac-8601-75a544ae2616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427640644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1427640644
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2851250919
Short name T318
Test name
Test status
Simulation time 527145147782 ps
CPU time 134.48 seconds
Started Jun 23 05:59:04 PM PDT 24
Finished Jun 23 06:01:19 PM PDT 24
Peak memory 202292 kb
Host smart-b886fa2e-aab3-411c-a78b-8922b6e072fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851250919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2851250919
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2443794693
Short name T307
Test name
Test status
Simulation time 321694594526 ps
CPU time 767.56 seconds
Started Jun 23 05:59:04 PM PDT 24
Finished Jun 23 06:11:52 PM PDT 24
Peak memory 202248 kb
Host smart-c2759764-baeb-48ac-889f-f6a4c78b1166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443794693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2443794693
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.486999194
Short name T780
Test name
Test status
Simulation time 161095209926 ps
CPU time 169.32 seconds
Started Jun 23 05:59:01 PM PDT 24
Finished Jun 23 06:01:50 PM PDT 24
Peak memory 202160 kb
Host smart-bd859137-0956-420b-95de-c59ff6bcb6d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=486999194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.486999194
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3800562603
Short name T241
Test name
Test status
Simulation time 491324706597 ps
CPU time 1074.22 seconds
Started Jun 23 05:58:58 PM PDT 24
Finished Jun 23 06:16:53 PM PDT 24
Peak memory 202228 kb
Host smart-ba9e45d2-c700-4b90-befb-a5d00164b5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800562603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3800562603
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4259149590
Short name T661
Test name
Test status
Simulation time 167597525404 ps
CPU time 112.08 seconds
Started Jun 23 05:59:00 PM PDT 24
Finished Jun 23 06:00:52 PM PDT 24
Peak memory 202192 kb
Host smart-711a35dc-9f60-42f7-98c5-1a0b439d71ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259149590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4259149590
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.986306380
Short name T163
Test name
Test status
Simulation time 173308065029 ps
CPU time 418.79 seconds
Started Jun 23 05:58:57 PM PDT 24
Finished Jun 23 06:05:56 PM PDT 24
Peak memory 202248 kb
Host smart-54742fd1-b76f-4ec1-9745-0803438e2c62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986306380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.986306380
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1993480988
Short name T479
Test name
Test status
Simulation time 385811078249 ps
CPU time 920.86 seconds
Started Jun 23 05:58:59 PM PDT 24
Finished Jun 23 06:14:20 PM PDT 24
Peak memory 202232 kb
Host smart-c50ad325-5e40-4e95-8264-320542b403b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993480988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1993480988
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1617583585
Short name T634
Test name
Test status
Simulation time 110618496780 ps
CPU time 388.53 seconds
Started Jun 23 05:59:10 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 202592 kb
Host smart-fadaae39-e54d-4fd8-ab4c-442289c96d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617583585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1617583585
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1347212489
Short name T405
Test name
Test status
Simulation time 35383142300 ps
CPU time 82.16 seconds
Started Jun 23 05:59:05 PM PDT 24
Finished Jun 23 06:00:27 PM PDT 24
Peak memory 202092 kb
Host smart-763a3e91-c25c-408c-acdd-2b38ce22b983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347212489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1347212489
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2399014977
Short name T453
Test name
Test status
Simulation time 4843102260 ps
CPU time 3.46 seconds
Started Jun 23 05:59:05 PM PDT 24
Finished Jun 23 05:59:09 PM PDT 24
Peak memory 202060 kb
Host smart-d6c7e091-af4c-4e91-bc53-8cf4c510be44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399014977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2399014977
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3380111898
Short name T666
Test name
Test status
Simulation time 5776256211 ps
CPU time 14.17 seconds
Started Jun 23 05:59:02 PM PDT 24
Finished Jun 23 05:59:17 PM PDT 24
Peak memory 202036 kb
Host smart-c40813d3-8d93-418a-99a9-cc7376a8f7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380111898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3380111898
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3892192546
Short name T272
Test name
Test status
Simulation time 211894187806 ps
CPU time 113.45 seconds
Started Jun 23 05:59:11 PM PDT 24
Finished Jun 23 06:01:04 PM PDT 24
Peak memory 202320 kb
Host smart-1915431d-85ea-4b21-bbe8-3149634f3891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892192546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3892192546
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.46384676
Short name T730
Test name
Test status
Simulation time 603281444147 ps
CPU time 721.01 seconds
Started Jun 23 05:59:10 PM PDT 24
Finished Jun 23 06:11:12 PM PDT 24
Peak memory 210912 kb
Host smart-5073e81e-b0bb-45dd-89cc-140578c8d15c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46384676 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.46384676
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1363147468
Short name T497
Test name
Test status
Simulation time 360067536 ps
CPU time 1.56 seconds
Started Jun 23 05:59:18 PM PDT 24
Finished Jun 23 05:59:20 PM PDT 24
Peak memory 201940 kb
Host smart-caf8b2a2-7f0d-4b57-92c3-cbfd940dc39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363147468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1363147468
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3151318926
Short name T162
Test name
Test status
Simulation time 401799719658 ps
CPU time 219.87 seconds
Started Jun 23 05:59:19 PM PDT 24
Finished Jun 23 06:02:59 PM PDT 24
Peak memory 202276 kb
Host smart-4be76e8b-cca1-4576-a819-3b828bfe7b59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151318926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3151318926
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.410906617
Short name T257
Test name
Test status
Simulation time 492957905200 ps
CPU time 367.8 seconds
Started Jun 23 05:59:19 PM PDT 24
Finished Jun 23 06:05:27 PM PDT 24
Peak memory 202208 kb
Host smart-a5bdda2d-e166-49e2-a049-50e736712b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410906617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.410906617
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3787319081
Short name T590
Test name
Test status
Simulation time 166790688033 ps
CPU time 67.58 seconds
Started Jun 23 05:59:12 PM PDT 24
Finished Jun 23 06:00:20 PM PDT 24
Peak memory 202156 kb
Host smart-1dd79370-7b1b-418a-8023-a1f044b89295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787319081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3787319081
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1485144263
Short name T649
Test name
Test status
Simulation time 162314481575 ps
CPU time 380.6 seconds
Started Jun 23 05:59:14 PM PDT 24
Finished Jun 23 06:05:35 PM PDT 24
Peak memory 202232 kb
Host smart-acac7e41-c8f7-4570-a43d-ed781f01c8a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485144263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1485144263
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4139940139
Short name T149
Test name
Test status
Simulation time 329748246445 ps
CPU time 55 seconds
Started Jun 23 05:59:12 PM PDT 24
Finished Jun 23 06:00:08 PM PDT 24
Peak memory 202256 kb
Host smart-463f7ef2-e2ec-46a1-8478-16abc3ea2fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139940139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4139940139
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.253335540
Short name T760
Test name
Test status
Simulation time 493851797447 ps
CPU time 537.64 seconds
Started Jun 23 05:59:12 PM PDT 24
Finished Jun 23 06:08:10 PM PDT 24
Peak memory 202212 kb
Host smart-58055322-3687-4e31-a350-37e92e37e5bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=253335540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.253335540
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2078220432
Short name T179
Test name
Test status
Simulation time 189150582162 ps
CPU time 68.12 seconds
Started Jun 23 05:59:12 PM PDT 24
Finished Jun 23 06:00:21 PM PDT 24
Peak memory 202244 kb
Host smart-0d8a7483-61a2-429f-b670-3f0e947ee8e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078220432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2078220432
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2586447694
Short name T401
Test name
Test status
Simulation time 216781593868 ps
CPU time 262.91 seconds
Started Jun 23 05:59:16 PM PDT 24
Finished Jun 23 06:03:39 PM PDT 24
Peak memory 202232 kb
Host smart-8d9046b1-3a7b-4478-bba8-81fd4f177bfe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586447694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2586447694
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1666085976
Short name T769
Test name
Test status
Simulation time 118271100548 ps
CPU time 451.92 seconds
Started Jun 23 05:59:19 PM PDT 24
Finished Jun 23 06:06:51 PM PDT 24
Peak memory 202612 kb
Host smart-9313160e-e716-44c7-b1e1-3507d0830e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666085976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1666085976
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.4211165081
Short name T425
Test name
Test status
Simulation time 32749134342 ps
CPU time 39.12 seconds
Started Jun 23 05:59:20 PM PDT 24
Finished Jun 23 05:59:59 PM PDT 24
Peak memory 202088 kb
Host smart-77918df3-5d10-4e60-89b0-1090cdb78840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211165081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.4211165081
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3266496775
Short name T378
Test name
Test status
Simulation time 3502262313 ps
CPU time 8.58 seconds
Started Jun 23 05:59:19 PM PDT 24
Finished Jun 23 05:59:27 PM PDT 24
Peak memory 202080 kb
Host smart-74624db6-5f53-4583-8555-15d285b386dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266496775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3266496775
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4124006457
Short name T470
Test name
Test status
Simulation time 6008471696 ps
CPU time 6.08 seconds
Started Jun 23 05:59:14 PM PDT 24
Finished Jun 23 05:59:21 PM PDT 24
Peak memory 202012 kb
Host smart-a99c6745-6b5a-4b6c-85b2-a00afa2c8238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124006457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4124006457
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2898862841
Short name T187
Test name
Test status
Simulation time 305116747877 ps
CPU time 181.03 seconds
Started Jun 23 05:59:19 PM PDT 24
Finished Jun 23 06:02:20 PM PDT 24
Peak memory 210888 kb
Host smart-012efc87-2e07-4824-98d0-42be2af6044c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898862841 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2898862841
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2478673652
Short name T12
Test name
Test status
Simulation time 462114636 ps
CPU time 0.96 seconds
Started Jun 23 05:59:28 PM PDT 24
Finished Jun 23 05:59:29 PM PDT 24
Peak memory 202116 kb
Host smart-ceca3b28-f513-4881-9383-1d4555a665eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478673652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2478673652
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.346548039
Short name T279
Test name
Test status
Simulation time 511269134719 ps
CPU time 200.65 seconds
Started Jun 23 05:59:25 PM PDT 24
Finished Jun 23 06:02:46 PM PDT 24
Peak memory 202328 kb
Host smart-4577e29f-16bc-4929-9f88-12cdb939f4ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346548039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.346548039
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1474030195
Short name T305
Test name
Test status
Simulation time 496216198884 ps
CPU time 553.21 seconds
Started Jun 23 05:59:21 PM PDT 24
Finished Jun 23 06:08:35 PM PDT 24
Peak memory 202156 kb
Host smart-fc4585ed-2335-4043-bbce-b8cadb394c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474030195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1474030195
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3039222643
Short name T416
Test name
Test status
Simulation time 327681224800 ps
CPU time 719.46 seconds
Started Jun 23 05:59:24 PM PDT 24
Finished Jun 23 06:11:24 PM PDT 24
Peak memory 202196 kb
Host smart-f23bf929-72c5-44b8-94c5-068174b5a844
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039222643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3039222643
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2601403908
Short name T578
Test name
Test status
Simulation time 493024069762 ps
CPU time 1090.85 seconds
Started Jun 23 05:59:18 PM PDT 24
Finished Jun 23 06:17:30 PM PDT 24
Peak memory 202232 kb
Host smart-5cae5403-ee35-4930-ac91-7037a0b16e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601403908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2601403908
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3384208069
Short name T510
Test name
Test status
Simulation time 492317459881 ps
CPU time 847.14 seconds
Started Jun 23 05:59:24 PM PDT 24
Finished Jun 23 06:13:32 PM PDT 24
Peak memory 202148 kb
Host smart-de99ee90-48f5-47b0-b13c-5d954f77a388
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384208069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3384208069
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2616193439
Short name T286
Test name
Test status
Simulation time 526815622648 ps
CPU time 407.87 seconds
Started Jun 23 05:59:21 PM PDT 24
Finished Jun 23 06:06:09 PM PDT 24
Peak memory 202332 kb
Host smart-b593e4d7-fcbe-4abb-ac1d-f624a8dbb387
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616193439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2616193439
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1952044084
Short name T607
Test name
Test status
Simulation time 194273932202 ps
CPU time 424 seconds
Started Jun 23 05:59:21 PM PDT 24
Finished Jun 23 06:06:25 PM PDT 24
Peak memory 202276 kb
Host smart-0580e6e2-b9ae-468b-ae72-64a7f12c6fb1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952044084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1952044084
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3125882412
Short name T531
Test name
Test status
Simulation time 101685362593 ps
CPU time 578.63 seconds
Started Jun 23 05:59:29 PM PDT 24
Finished Jun 23 06:09:08 PM PDT 24
Peak memory 202636 kb
Host smart-d4f41eaf-b51e-43e4-b21d-ab923e55724e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125882412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3125882412
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2578130438
Short name T370
Test name
Test status
Simulation time 41413855142 ps
CPU time 48.49 seconds
Started Jun 23 05:59:25 PM PDT 24
Finished Jun 23 06:00:14 PM PDT 24
Peak memory 202056 kb
Host smart-fdf65a9e-3360-4c18-b401-c654e2182d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578130438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2578130438
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.472215406
Short name T722
Test name
Test status
Simulation time 3818376896 ps
CPU time 9.64 seconds
Started Jun 23 05:59:21 PM PDT 24
Finished Jun 23 05:59:31 PM PDT 24
Peak memory 202080 kb
Host smart-f7dfabce-4922-45c4-9cb0-ae0d8cb4436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472215406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.472215406
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2966076756
Short name T588
Test name
Test status
Simulation time 6100218935 ps
CPU time 13.39 seconds
Started Jun 23 05:59:16 PM PDT 24
Finished Jun 23 05:59:30 PM PDT 24
Peak memory 202060 kb
Host smart-fd098ac3-c450-4380-b802-ffecb192422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966076756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2966076756
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3781211344
Short name T317
Test name
Test status
Simulation time 59030435651 ps
CPU time 128.52 seconds
Started Jun 23 05:59:30 PM PDT 24
Finished Jun 23 06:01:39 PM PDT 24
Peak memory 202412 kb
Host smart-304cba09-037e-47d3-abe8-91d4dbf9a8ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781211344 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3781211344
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2590417435
Short name T684
Test name
Test status
Simulation time 521714906 ps
CPU time 1.78 seconds
Started Jun 23 05:59:38 PM PDT 24
Finished Jun 23 05:59:40 PM PDT 24
Peak memory 201960 kb
Host smart-881d6646-34ae-464e-8ce6-bcdde376587f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590417435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2590417435
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.705404303
Short name T583
Test name
Test status
Simulation time 190330668751 ps
CPU time 121.27 seconds
Started Jun 23 05:59:32 PM PDT 24
Finished Jun 23 06:01:33 PM PDT 24
Peak memory 202264 kb
Host smart-36cfdba7-64df-4595-8f20-4b45cb55bd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705404303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.705404303
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4191889851
Short name T546
Test name
Test status
Simulation time 165535622298 ps
CPU time 104.03 seconds
Started Jun 23 05:59:29 PM PDT 24
Finished Jun 23 06:01:14 PM PDT 24
Peak memory 202168 kb
Host smart-6bbc030b-c222-4cc6-9c4b-1a2ecc1c4325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191889851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4191889851
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1580988375
Short name T396
Test name
Test status
Simulation time 485753012087 ps
CPU time 226.92 seconds
Started Jun 23 05:59:33 PM PDT 24
Finished Jun 23 06:03:20 PM PDT 24
Peak memory 202216 kb
Host smart-23f19d7c-5466-4d10-9680-6837b216d400
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580988375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1580988375
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3259484570
Short name T427
Test name
Test status
Simulation time 325829169570 ps
CPU time 813.6 seconds
Started Jun 23 05:59:30 PM PDT 24
Finished Jun 23 06:13:04 PM PDT 24
Peak memory 202340 kb
Host smart-97975bbd-5d35-4f8f-8215-43ada016ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259484570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3259484570
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.271791184
Short name T512
Test name
Test status
Simulation time 164054740622 ps
CPU time 36.92 seconds
Started Jun 23 05:59:28 PM PDT 24
Finished Jun 23 06:00:05 PM PDT 24
Peak memory 202176 kb
Host smart-33fc906a-c70d-47d3-86db-0a837ec8b104
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=271791184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.271791184
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.574409951
Short name T133
Test name
Test status
Simulation time 164931956060 ps
CPU time 172.14 seconds
Started Jun 23 05:59:33 PM PDT 24
Finished Jun 23 06:02:26 PM PDT 24
Peak memory 202204 kb
Host smart-3e155dcc-fe5e-4190-9172-950a2935af52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574409951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.574409951
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.746525752
Short name T574
Test name
Test status
Simulation time 208202850339 ps
CPU time 94.34 seconds
Started Jun 23 05:59:34 PM PDT 24
Finished Jun 23 06:01:08 PM PDT 24
Peak memory 202240 kb
Host smart-5791549d-7db0-48c2-baa1-56c2e072009a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746525752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.746525752
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2282913824
Short name T603
Test name
Test status
Simulation time 118527835636 ps
CPU time 423.19 seconds
Started Jun 23 05:59:40 PM PDT 24
Finished Jun 23 06:06:43 PM PDT 24
Peak memory 202524 kb
Host smart-8e031b59-8d0d-41c2-a3c4-0acc63dba13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282913824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2282913824
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1607381344
Short name T97
Test name
Test status
Simulation time 46995120629 ps
CPU time 27.76 seconds
Started Jun 23 05:59:39 PM PDT 24
Finished Jun 23 06:00:07 PM PDT 24
Peak memory 202092 kb
Host smart-d9abea49-76e9-4977-b24c-f8884123f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607381344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1607381344
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1613119751
Short name T746
Test name
Test status
Simulation time 5471992154 ps
CPU time 7.58 seconds
Started Jun 23 05:59:33 PM PDT 24
Finished Jun 23 05:59:41 PM PDT 24
Peak memory 202056 kb
Host smart-3b38e693-ce39-4456-a1ab-3af851be18bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613119751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1613119751
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2978621451
Short name T632
Test name
Test status
Simulation time 6004291839 ps
CPU time 4.49 seconds
Started Jun 23 05:59:27 PM PDT 24
Finished Jun 23 05:59:32 PM PDT 24
Peak memory 201992 kb
Host smart-51573aa3-5742-49a1-b34a-f756b8b6f90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978621451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2978621451
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3407304724
Short name T269
Test name
Test status
Simulation time 430400788067 ps
CPU time 362.86 seconds
Started Jun 23 05:59:37 PM PDT 24
Finished Jun 23 06:05:40 PM PDT 24
Peak memory 211004 kb
Host smart-c0081f42-b9cb-4634-8b9b-c4a4008e7cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407304724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3407304724
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2067680559
Short name T13
Test name
Test status
Simulation time 270121257821 ps
CPU time 172.35 seconds
Started Jun 23 05:59:36 PM PDT 24
Finished Jun 23 06:02:29 PM PDT 24
Peak memory 202352 kb
Host smart-de0dd00c-d6ff-4d6d-895b-9a1e36a88fad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067680559 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2067680559
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2072409635
Short name T533
Test name
Test status
Simulation time 358787563 ps
CPU time 0.8 seconds
Started Jun 23 05:59:50 PM PDT 24
Finished Jun 23 05:59:52 PM PDT 24
Peak memory 201876 kb
Host smart-57ecf24e-fb21-47f5-b981-6a20c17acf6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072409635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2072409635
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.431478245
Short name T324
Test name
Test status
Simulation time 326172430697 ps
CPU time 683.51 seconds
Started Jun 23 05:59:43 PM PDT 24
Finished Jun 23 06:11:07 PM PDT 24
Peak memory 202268 kb
Host smart-4ba3e5d3-0e85-4103-96a7-b508390d0999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431478245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.431478245
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.63007116
Short name T506
Test name
Test status
Simulation time 329379384387 ps
CPU time 696.91 seconds
Started Jun 23 05:59:42 PM PDT 24
Finished Jun 23 06:11:19 PM PDT 24
Peak memory 202284 kb
Host smart-47e34f5c-def6-442c-bba2-c7edd081243d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=63007116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt
_fixed.63007116
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1928281110
Short name T281
Test name
Test status
Simulation time 164817316763 ps
CPU time 157.37 seconds
Started Jun 23 05:59:44 PM PDT 24
Finished Jun 23 06:02:22 PM PDT 24
Peak memory 202260 kb
Host smart-7669fd2f-0b13-4195-a8d1-214139dccc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928281110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1928281110
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1486333369
Short name T483
Test name
Test status
Simulation time 325168947998 ps
CPU time 195.36 seconds
Started Jun 23 05:59:44 PM PDT 24
Finished Jun 23 06:03:00 PM PDT 24
Peak memory 202308 kb
Host smart-1a1e9401-b3ec-4563-8e69-7ac31bc6dc62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486333369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1486333369
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.4012699762
Short name T659
Test name
Test status
Simulation time 197283633563 ps
CPU time 106.44 seconds
Started Jun 23 05:59:43 PM PDT 24
Finished Jun 23 06:01:30 PM PDT 24
Peak memory 202260 kb
Host smart-8e3976ae-ca1a-4bdd-8cf0-89de23c5835d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012699762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.4012699762
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1744215696
Short name T387
Test name
Test status
Simulation time 399689382580 ps
CPU time 88.69 seconds
Started Jun 23 05:59:47 PM PDT 24
Finished Jun 23 06:01:15 PM PDT 24
Peak memory 202264 kb
Host smart-660d76f8-c156-485c-9526-b2b6ef10f3eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744215696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1744215696
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4169729352
Short name T188
Test name
Test status
Simulation time 122526500487 ps
CPU time 354.13 seconds
Started Jun 23 05:59:44 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 202516 kb
Host smart-5bde9f86-72a9-42dd-82d6-3f5baa3a9964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169729352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4169729352
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.604430551
Short name T408
Test name
Test status
Simulation time 42266509185 ps
CPU time 20.17 seconds
Started Jun 23 05:59:43 PM PDT 24
Finished Jun 23 06:00:04 PM PDT 24
Peak memory 201964 kb
Host smart-4a30e290-6e4b-4b7b-a3c6-c22bc1881059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604430551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.604430551
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2051728801
Short name T488
Test name
Test status
Simulation time 2739899182 ps
CPU time 7.18 seconds
Started Jun 23 05:59:44 PM PDT 24
Finished Jun 23 05:59:52 PM PDT 24
Peak memory 201976 kb
Host smart-622b0ddc-12c1-4f8a-82af-c7bd743ef268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051728801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2051728801
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2314188697
Short name T455
Test name
Test status
Simulation time 5796054435 ps
CPU time 7.64 seconds
Started Jun 23 05:59:44 PM PDT 24
Finished Jun 23 05:59:52 PM PDT 24
Peak memory 202012 kb
Host smart-99c9d076-8765-4cf0-aa54-b7bc6d47e760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314188697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2314188697
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1811416649
Short name T753
Test name
Test status
Simulation time 245206164903 ps
CPU time 534.94 seconds
Started Jun 23 05:59:50 PM PDT 24
Finished Jun 23 06:08:46 PM PDT 24
Peak memory 202232 kb
Host smart-1294204e-c82d-41b3-935a-39ce768f7e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811416649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1811416649
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3434538185
Short name T17
Test name
Test status
Simulation time 23645562165 ps
CPU time 51.84 seconds
Started Jun 23 05:59:44 PM PDT 24
Finished Jun 23 06:00:36 PM PDT 24
Peak memory 202456 kb
Host smart-de1344e3-45d1-43b3-bae6-2849e934f79a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434538185 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3434538185
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3533406381
Short name T678
Test name
Test status
Simulation time 539571369 ps
CPU time 0.87 seconds
Started Jun 23 05:59:58 PM PDT 24
Finished Jun 23 05:59:59 PM PDT 24
Peak memory 201912 kb
Host smart-b8249b35-2b59-4faf-bee4-0ba36115e264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533406381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3533406381
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2709634380
Short name T128
Test name
Test status
Simulation time 359099594436 ps
CPU time 798.97 seconds
Started Jun 23 05:59:54 PM PDT 24
Finished Jun 23 06:13:14 PM PDT 24
Peak memory 202284 kb
Host smart-3ad9504b-26ff-4dce-a59e-26524bd52105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709634380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2709634380
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3364939968
Short name T2
Test name
Test status
Simulation time 327444608340 ps
CPU time 109.12 seconds
Started Jun 23 05:59:52 PM PDT 24
Finished Jun 23 06:01:41 PM PDT 24
Peak memory 202208 kb
Host smart-75d16f6a-a5b2-4183-9554-7613bdf8937a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364939968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3364939968
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.205389049
Short name T716
Test name
Test status
Simulation time 329136311467 ps
CPU time 718.86 seconds
Started Jun 23 05:59:50 PM PDT 24
Finished Jun 23 06:11:49 PM PDT 24
Peak memory 202344 kb
Host smart-87d5cac8-78db-4657-ab8f-0b598b2f1d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205389049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.205389049
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2724211119
Short name T682
Test name
Test status
Simulation time 331233822090 ps
CPU time 756.64 seconds
Started Jun 23 05:59:53 PM PDT 24
Finished Jun 23 06:12:30 PM PDT 24
Peak memory 202232 kb
Host smart-f0440b72-43ea-4be3-9cbb-1d4d3703d5ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724211119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2724211119
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1863908696
Short name T23
Test name
Test status
Simulation time 341353494922 ps
CPU time 214.28 seconds
Started Jun 23 05:59:53 PM PDT 24
Finished Jun 23 06:03:28 PM PDT 24
Peak memory 202316 kb
Host smart-d73ffdde-16b0-4aa4-909c-b123d592e7b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863908696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1863908696
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2450187142
Short name T461
Test name
Test status
Simulation time 413979016404 ps
CPU time 619.32 seconds
Started Jun 23 05:59:54 PM PDT 24
Finished Jun 23 06:10:13 PM PDT 24
Peak memory 202232 kb
Host smart-718acc7e-623f-46e3-9509-3f79cc04e427
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450187142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2450187142
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2418254586
Short name T704
Test name
Test status
Simulation time 109074675094 ps
CPU time 388.45 seconds
Started Jun 23 05:59:59 PM PDT 24
Finished Jun 23 06:06:28 PM PDT 24
Peak memory 202556 kb
Host smart-d0ed3fe0-df45-4fca-a0b2-2fb2c3e22b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418254586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2418254586
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3493120461
Short name T616
Test name
Test status
Simulation time 44953862399 ps
CPU time 95.03 seconds
Started Jun 23 05:59:53 PM PDT 24
Finished Jun 23 06:01:28 PM PDT 24
Peak memory 202040 kb
Host smart-e4a035fc-10df-4a40-8f08-ab209a374ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493120461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3493120461
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1085455628
Short name T472
Test name
Test status
Simulation time 3977066970 ps
CPU time 3.21 seconds
Started Jun 23 05:59:51 PM PDT 24
Finished Jun 23 05:59:55 PM PDT 24
Peak memory 202076 kb
Host smart-daa70f42-fb86-4f39-b0d6-7a4e454e9ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085455628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1085455628
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2697323215
Short name T100
Test name
Test status
Simulation time 5581741930 ps
CPU time 14.11 seconds
Started Jun 23 05:59:47 PM PDT 24
Finished Jun 23 06:00:01 PM PDT 24
Peak memory 202240 kb
Host smart-7b2b0f64-5451-4ea0-a162-a31d7d0e237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697323215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2697323215
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.689459368
Short name T775
Test name
Test status
Simulation time 193693775251 ps
CPU time 490.35 seconds
Started Jun 23 05:59:59 PM PDT 24
Finished Jun 23 06:08:09 PM PDT 24
Peak memory 202200 kb
Host smart-c12e99a8-4a29-4b71-b0b5-8cd54d5c7fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689459368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
689459368
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3712305436
Short name T407
Test name
Test status
Simulation time 325290717 ps
CPU time 0.8 seconds
Started Jun 23 05:55:13 PM PDT 24
Finished Jun 23 05:55:15 PM PDT 24
Peak memory 201932 kb
Host smart-b824c549-d438-4dac-b461-43857d063c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712305436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3712305436
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3592982292
Short name T628
Test name
Test status
Simulation time 338818435033 ps
CPU time 763.99 seconds
Started Jun 23 05:55:08 PM PDT 24
Finished Jun 23 06:07:53 PM PDT 24
Peak memory 202252 kb
Host smart-97851c90-7925-4aa3-a618-54c11276d242
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592982292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3592982292
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3326743322
Short name T720
Test name
Test status
Simulation time 166544514007 ps
CPU time 48.58 seconds
Started Jun 23 05:55:10 PM PDT 24
Finished Jun 23 05:55:59 PM PDT 24
Peak memory 202268 kb
Host smart-a05ced23-0cf7-48a4-8453-0364aa850a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326743322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3326743322
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3820535086
Short name T410
Test name
Test status
Simulation time 166895620011 ps
CPU time 106.52 seconds
Started Jun 23 05:55:09 PM PDT 24
Finished Jun 23 05:56:56 PM PDT 24
Peak memory 202224 kb
Host smart-bb784f98-dd22-4b5d-add8-af80316b133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820535086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3820535086
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1808962700
Short name T362
Test name
Test status
Simulation time 327161146541 ps
CPU time 696 seconds
Started Jun 23 05:55:09 PM PDT 24
Finished Jun 23 06:06:45 PM PDT 24
Peak memory 202132 kb
Host smart-168ac1a4-63f9-4c35-a9ef-542a5ea34377
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808962700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1808962700
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1233329837
Short name T698
Test name
Test status
Simulation time 161562983824 ps
CPU time 353.6 seconds
Started Jun 23 05:55:11 PM PDT 24
Finished Jun 23 06:01:05 PM PDT 24
Peak memory 202280 kb
Host smart-37022f9d-81ed-4f15-ae7c-2337719f1d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233329837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1233329837
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.267424740
Short name T629
Test name
Test status
Simulation time 164137777765 ps
CPU time 53.29 seconds
Started Jun 23 05:55:13 PM PDT 24
Finished Jun 23 05:56:07 PM PDT 24
Peak memory 202176 kb
Host smart-77a24be2-dcdf-419d-91bb-e291a251bed1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=267424740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.267424740
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3241147431
Short name T687
Test name
Test status
Simulation time 582083524209 ps
CPU time 1383.55 seconds
Started Jun 23 05:55:14 PM PDT 24
Finished Jun 23 06:18:18 PM PDT 24
Peak memory 202300 kb
Host smart-bdc0f6a1-a07f-49d6-a593-3b556aa44fef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241147431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3241147431
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.471915764
Short name T619
Test name
Test status
Simulation time 118916414373 ps
CPU time 416.58 seconds
Started Jun 23 05:55:13 PM PDT 24
Finished Jun 23 06:02:10 PM PDT 24
Peak memory 202512 kb
Host smart-071f4dcf-ba21-4cdd-b9b9-d5bf7bfe1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471915764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.471915764
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1995571323
Short name T543
Test name
Test status
Simulation time 34144372879 ps
CPU time 60.74 seconds
Started Jun 23 05:55:14 PM PDT 24
Finished Jun 23 05:56:15 PM PDT 24
Peak memory 202072 kb
Host smart-dd935b77-f0e7-47c8-b219-2c4030cef35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995571323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1995571323
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2421920732
Short name T767
Test name
Test status
Simulation time 3630769925 ps
CPU time 2.75 seconds
Started Jun 23 05:55:16 PM PDT 24
Finished Jun 23 05:55:19 PM PDT 24
Peak memory 202060 kb
Host smart-5485cec3-1d1b-408d-93f4-eb9757c64231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421920732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2421920732
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3838238277
Short name T671
Test name
Test status
Simulation time 5755397029 ps
CPU time 7.69 seconds
Started Jun 23 05:55:08 PM PDT 24
Finished Jun 23 05:55:16 PM PDT 24
Peak memory 202248 kb
Host smart-44f18e84-4ba6-4f47-9453-9d3973e20b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838238277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3838238277
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1288694908
Short name T577
Test name
Test status
Simulation time 58620526704 ps
CPU time 124.55 seconds
Started Jun 23 05:55:12 PM PDT 24
Finished Jun 23 05:57:17 PM PDT 24
Peak memory 218656 kb
Host smart-feaeae81-bad2-47cf-b31b-9c414c0e1a1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288694908 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1288694908
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2916726262
Short name T21
Test name
Test status
Simulation time 428108889 ps
CPU time 0.77 seconds
Started Jun 23 05:55:12 PM PDT 24
Finished Jun 23 05:55:13 PM PDT 24
Peak memory 201948 kb
Host smart-494fa819-c1f0-44df-8005-1aaf9ec62a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916726262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2916726262
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1186500128
Short name T271
Test name
Test status
Simulation time 363119154361 ps
CPU time 205.83 seconds
Started Jun 23 05:55:12 PM PDT 24
Finished Jun 23 05:58:39 PM PDT 24
Peak memory 202252 kb
Host smart-b3cb4777-d251-48a4-b726-8b51cdf99d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186500128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1186500128
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.4263353978
Short name T340
Test name
Test status
Simulation time 159800230310 ps
CPU time 42.87 seconds
Started Jun 23 05:55:14 PM PDT 24
Finished Jun 23 05:55:57 PM PDT 24
Peak memory 202296 kb
Host smart-b97ae782-8a94-47e1-ba98-601ae72878cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263353978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.4263353978
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2103504479
Short name T748
Test name
Test status
Simulation time 164493352750 ps
CPU time 381.29 seconds
Started Jun 23 05:55:16 PM PDT 24
Finished Jun 23 06:01:37 PM PDT 24
Peak memory 202292 kb
Host smart-32e14519-4ae9-435e-bea0-33a0209913fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103504479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2103504479
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2312891524
Short name T139
Test name
Test status
Simulation time 492255516708 ps
CPU time 271.97 seconds
Started Jun 23 05:55:16 PM PDT 24
Finished Jun 23 05:59:48 PM PDT 24
Peak memory 202256 kb
Host smart-e59c339e-f95a-41e1-8a6a-f4e14090c7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312891524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2312891524
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.4202306511
Short name T452
Test name
Test status
Simulation time 492588056386 ps
CPU time 1231.24 seconds
Started Jun 23 05:55:14 PM PDT 24
Finished Jun 23 06:15:46 PM PDT 24
Peak memory 202160 kb
Host smart-ea716e43-9035-4033-8238-403e204188f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202306511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.4202306511
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2768500765
Short name T660
Test name
Test status
Simulation time 399846062705 ps
CPU time 446.96 seconds
Started Jun 23 05:55:13 PM PDT 24
Finished Jun 23 06:02:41 PM PDT 24
Peak memory 202192 kb
Host smart-51f8127b-57c9-4f4d-a007-4206568d3127
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768500765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2768500765
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3376599449
Short name T191
Test name
Test status
Simulation time 99922676244 ps
CPU time 400.58 seconds
Started Jun 23 05:55:14 PM PDT 24
Finished Jun 23 06:01:55 PM PDT 24
Peak memory 202492 kb
Host smart-e93828ff-b57f-4bb2-9959-c82ff209d154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376599449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3376599449
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3740735571
Short name T559
Test name
Test status
Simulation time 34047078043 ps
CPU time 7.45 seconds
Started Jun 23 05:55:15 PM PDT 24
Finished Jun 23 05:55:22 PM PDT 24
Peak memory 202076 kb
Host smart-c02b4c3f-1f85-4149-995f-7c6f6abd5e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740735571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3740735571
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2840299280
Short name T558
Test name
Test status
Simulation time 3253057357 ps
CPU time 8.65 seconds
Started Jun 23 05:55:15 PM PDT 24
Finished Jun 23 05:55:24 PM PDT 24
Peak memory 202076 kb
Host smart-a7f214f8-241c-472f-9406-662e99e1d90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840299280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2840299280
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3935175118
Short name T369
Test name
Test status
Simulation time 5766738196 ps
CPU time 14.55 seconds
Started Jun 23 05:55:15 PM PDT 24
Finished Jun 23 05:55:30 PM PDT 24
Peak memory 202024 kb
Host smart-19778356-2c20-48c6-87c5-59b2d1c211cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935175118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3935175118
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1587988217
Short name T693
Test name
Test status
Simulation time 458858945719 ps
CPU time 361.16 seconds
Started Jun 23 05:55:14 PM PDT 24
Finished Jun 23 06:01:16 PM PDT 24
Peak memory 210852 kb
Host smart-d6e32565-eb08-4798-8188-2783cc76c915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587988217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1587988217
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2102412889
Short name T321
Test name
Test status
Simulation time 336313677790 ps
CPU time 177.95 seconds
Started Jun 23 05:55:14 PM PDT 24
Finished Jun 23 05:58:12 PM PDT 24
Peak memory 210596 kb
Host smart-b5bcc58e-ff64-4ab1-b50c-1a5555a141e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102412889 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2102412889
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2281640626
Short name T384
Test name
Test status
Simulation time 314179005 ps
CPU time 1.31 seconds
Started Jun 23 05:55:20 PM PDT 24
Finished Jun 23 05:55:22 PM PDT 24
Peak memory 201956 kb
Host smart-e62b76d7-2a36-4bef-a744-ec7bc9c9fbfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281640626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2281640626
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2981734903
Short name T630
Test name
Test status
Simulation time 332228878483 ps
CPU time 179.51 seconds
Started Jun 23 05:55:20 PM PDT 24
Finished Jun 23 05:58:20 PM PDT 24
Peak memory 202212 kb
Host smart-08d3b03f-604f-409c-9991-1e8bfce57c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981734903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2981734903
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3869041555
Short name T597
Test name
Test status
Simulation time 488784223743 ps
CPU time 1048.94 seconds
Started Jun 23 05:55:23 PM PDT 24
Finished Jun 23 06:12:53 PM PDT 24
Peak memory 202288 kb
Host smart-ccd9b6c1-95de-47b1-b665-72bae0c9d2c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869041555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3869041555
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3892639486
Short name T322
Test name
Test status
Simulation time 500428925124 ps
CPU time 1187.41 seconds
Started Jun 23 05:55:18 PM PDT 24
Finished Jun 23 06:15:06 PM PDT 24
Peak memory 202144 kb
Host smart-9b48c796-63db-44d5-a3c3-c91760f377c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892639486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3892639486
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.616458280
Short name T355
Test name
Test status
Simulation time 332972510965 ps
CPU time 404.94 seconds
Started Jun 23 05:55:19 PM PDT 24
Finished Jun 23 06:02:04 PM PDT 24
Peak memory 202312 kb
Host smart-7f069e7a-1f2a-40ad-8d60-f2a89e4f29ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=616458280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.616458280
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1266606855
Short name T223
Test name
Test status
Simulation time 549852237074 ps
CPU time 251.85 seconds
Started Jun 23 05:55:19 PM PDT 24
Finished Jun 23 05:59:31 PM PDT 24
Peak memory 202248 kb
Host smart-ef0658d8-e0d4-4df7-ac0d-2640a9a0644f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266606855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1266606855
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1542843820
Short name T688
Test name
Test status
Simulation time 202348784493 ps
CPU time 433.87 seconds
Started Jun 23 05:55:17 PM PDT 24
Finished Jun 23 06:02:32 PM PDT 24
Peak memory 202236 kb
Host smart-6b25a384-20b2-48c5-97ea-ec41ab5ea0c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542843820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1542843820
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3194712423
Short name T491
Test name
Test status
Simulation time 114548416106 ps
CPU time 433.89 seconds
Started Jun 23 05:55:17 PM PDT 24
Finished Jun 23 06:02:32 PM PDT 24
Peak memory 202564 kb
Host smart-4633999d-cafa-4f1f-96d4-1dd95408b4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194712423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3194712423
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2446748174
Short name T74
Test name
Test status
Simulation time 33750798690 ps
CPU time 71.48 seconds
Started Jun 23 05:55:19 PM PDT 24
Finished Jun 23 05:56:31 PM PDT 24
Peak memory 202076 kb
Host smart-6299cba0-111d-45e4-a126-87ffbbd1edee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446748174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2446748174
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2969573696
Short name T565
Test name
Test status
Simulation time 4511049617 ps
CPU time 11.35 seconds
Started Jun 23 05:55:20 PM PDT 24
Finished Jun 23 05:55:32 PM PDT 24
Peak memory 202056 kb
Host smart-7a56e783-d79f-4ecc-845e-e95a7462e29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969573696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2969573696
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3228528281
Short name T747
Test name
Test status
Simulation time 5627890892 ps
CPU time 13.72 seconds
Started Jun 23 05:55:11 PM PDT 24
Finished Jun 23 05:55:26 PM PDT 24
Peak memory 202076 kb
Host smart-dcc90e17-d559-4624-8d0d-10610d42b20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228528281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3228528281
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.582829872
Short name T189
Test name
Test status
Simulation time 166978737286 ps
CPU time 618.89 seconds
Started Jun 23 05:55:19 PM PDT 24
Finished Jun 23 06:05:38 PM PDT 24
Peak memory 202616 kb
Host smart-ddf3772f-70cf-4f73-8ed6-1fd5ee495d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582829872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.582829872
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3806864993
Short name T329
Test name
Test status
Simulation time 33880395946 ps
CPU time 20.43 seconds
Started Jun 23 05:55:20 PM PDT 24
Finished Jun 23 05:55:41 PM PDT 24
Peak memory 202312 kb
Host smart-7bab823f-099c-4e11-8780-309fb61cf766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806864993 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3806864993
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2345459233
Short name T22
Test name
Test status
Simulation time 376537363 ps
CPU time 0.81 seconds
Started Jun 23 05:55:25 PM PDT 24
Finished Jun 23 05:55:26 PM PDT 24
Peak memory 201948 kb
Host smart-84b1bf13-1783-46f3-89ef-337b3603c74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345459233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2345459233
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1507808658
Short name T275
Test name
Test status
Simulation time 327844535210 ps
CPU time 212.6 seconds
Started Jun 23 05:55:24 PM PDT 24
Finished Jun 23 05:58:57 PM PDT 24
Peak memory 202344 kb
Host smart-406998ed-418f-4b3c-92fe-ea73345eb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507808658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1507808658
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3635913746
Short name T137
Test name
Test status
Simulation time 169976370874 ps
CPU time 43.31 seconds
Started Jun 23 05:55:22 PM PDT 24
Finished Jun 23 05:56:06 PM PDT 24
Peak memory 202284 kb
Host smart-9c62a876-f7ce-4225-a926-3521c681b59b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635913746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3635913746
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1478987386
Short name T338
Test name
Test status
Simulation time 164589548590 ps
CPU time 199.81 seconds
Started Jun 23 05:55:24 PM PDT 24
Finished Jun 23 05:58:45 PM PDT 24
Peak memory 202236 kb
Host smart-15ff9a5f-f3bd-4931-99f3-560ab3484090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478987386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1478987386
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3482452742
Short name T442
Test name
Test status
Simulation time 166661596742 ps
CPU time 65.45 seconds
Started Jun 23 05:55:23 PM PDT 24
Finished Jun 23 05:56:28 PM PDT 24
Peak memory 202160 kb
Host smart-a3e1ac06-01a8-4793-a179-529a70620429
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482452742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3482452742
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2396949731
Short name T403
Test name
Test status
Simulation time 608012034047 ps
CPU time 331.17 seconds
Started Jun 23 05:55:22 PM PDT 24
Finished Jun 23 06:00:54 PM PDT 24
Peak memory 202188 kb
Host smart-eea1bc60-5bee-462e-b7e4-a483cf8d988e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396949731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2396949731
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.329535006
Short name T571
Test name
Test status
Simulation time 109972030512 ps
CPU time 520.44 seconds
Started Jun 23 05:55:27 PM PDT 24
Finished Jun 23 06:04:07 PM PDT 24
Peak memory 202496 kb
Host smart-7b06080f-f552-447c-84ae-80e7d7312eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329535006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.329535006
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3524601538
Short name T167
Test name
Test status
Simulation time 33612676856 ps
CPU time 5.98 seconds
Started Jun 23 05:55:23 PM PDT 24
Finished Jun 23 05:55:30 PM PDT 24
Peak memory 202040 kb
Host smart-e06a32a6-92af-4d5e-bd65-dccf20e5b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524601538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3524601538
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.4090317403
Short name T380
Test name
Test status
Simulation time 4633699531 ps
CPU time 3.06 seconds
Started Jun 23 05:55:28 PM PDT 24
Finished Jun 23 05:55:31 PM PDT 24
Peak memory 202036 kb
Host smart-f52bc54f-5f25-4442-8986-eba2f4678cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090317403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4090317403
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.4029788180
Short name T462
Test name
Test status
Simulation time 5669045947 ps
CPU time 13.9 seconds
Started Jun 23 05:55:26 PM PDT 24
Finished Jun 23 05:55:40 PM PDT 24
Peak memory 201996 kb
Host smart-46d6b810-c911-4f2e-af80-b123793bc3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029788180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.4029788180
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1970677599
Short name T676
Test name
Test status
Simulation time 173770548898 ps
CPU time 413.68 seconds
Started Jun 23 05:55:27 PM PDT 24
Finished Jun 23 06:02:21 PM PDT 24
Peak memory 202308 kb
Host smart-cc430127-8b9e-4d2e-9401-4a874a93733c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970677599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1970677599
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3189085189
Short name T15
Test name
Test status
Simulation time 121589348303 ps
CPU time 26.42 seconds
Started Jun 23 05:55:26 PM PDT 24
Finished Jun 23 05:55:52 PM PDT 24
Peak memory 202740 kb
Host smart-7a7cb63e-24eb-48c0-ba71-5244c73a9e4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189085189 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3189085189
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.60050953
Short name T426
Test name
Test status
Simulation time 378248384 ps
CPU time 0.95 seconds
Started Jun 23 05:55:32 PM PDT 24
Finished Jun 23 05:55:33 PM PDT 24
Peak memory 201948 kb
Host smart-4a60fc53-2c89-48c4-bc28-0b444c56b777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60050953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.60050953
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.747571130
Short name T299
Test name
Test status
Simulation time 183691539466 ps
CPU time 221.57 seconds
Started Jun 23 05:55:27 PM PDT 24
Finished Jun 23 05:59:09 PM PDT 24
Peak memory 202252 kb
Host smart-dbd05cc6-4cbb-44c2-8855-179986070042
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747571130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.747571130
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2930743273
Short name T175
Test name
Test status
Simulation time 499079579466 ps
CPU time 296.77 seconds
Started Jun 23 05:55:26 PM PDT 24
Finished Jun 23 06:00:23 PM PDT 24
Peak memory 202480 kb
Host smart-bd7d67cc-d230-4975-8b78-65e99e39c061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930743273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2930743273
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1644080402
Short name T672
Test name
Test status
Simulation time 489308438316 ps
CPU time 277.11 seconds
Started Jun 23 05:55:23 PM PDT 24
Finished Jun 23 06:00:00 PM PDT 24
Peak memory 202188 kb
Host smart-73b072a3-c5cf-4d81-8445-27b4d655c071
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644080402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1644080402
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2684699792
Short name T489
Test name
Test status
Simulation time 487827435349 ps
CPU time 870.06 seconds
Started Jun 23 05:55:24 PM PDT 24
Finished Jun 23 06:09:54 PM PDT 24
Peak memory 202304 kb
Host smart-2a3eccb6-724b-452d-aa43-18fbb48cf704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684699792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2684699792
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4123238612
Short name T750
Test name
Test status
Simulation time 499484431761 ps
CPU time 118.64 seconds
Started Jun 23 05:55:22 PM PDT 24
Finished Jun 23 05:57:21 PM PDT 24
Peak memory 202172 kb
Host smart-1342189c-f070-4b0d-8814-04cbfa425f1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123238612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.4123238612
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.31788477
Short name T615
Test name
Test status
Simulation time 199553183604 ps
CPU time 450.62 seconds
Started Jun 23 05:55:24 PM PDT 24
Finished Jun 23 06:02:55 PM PDT 24
Peak memory 202296 kb
Host smart-32cc8725-2cca-4ba6-bfb3-d73d6dce29cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31788477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wa
keup.31788477
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4154677867
Short name T214
Test name
Test status
Simulation time 194697213440 ps
CPU time 455.57 seconds
Started Jun 23 05:55:27 PM PDT 24
Finished Jun 23 06:03:03 PM PDT 24
Peak memory 202304 kb
Host smart-d0533266-8854-49c7-98a6-6967372a733a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154677867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.4154677867
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2031884976
Short name T348
Test name
Test status
Simulation time 93193357633 ps
CPU time 305.07 seconds
Started Jun 23 05:55:30 PM PDT 24
Finished Jun 23 06:00:35 PM PDT 24
Peak memory 202596 kb
Host smart-9ec90c12-2287-448c-a15e-3a8003794e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031884976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2031884976
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3532381045
Short name T576
Test name
Test status
Simulation time 32606825829 ps
CPU time 39.72 seconds
Started Jun 23 05:55:28 PM PDT 24
Finished Jun 23 05:56:08 PM PDT 24
Peak memory 202064 kb
Host smart-f5b608bc-6e94-4781-a8e4-eb40bddc297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532381045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3532381045
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.276948487
Short name T770
Test name
Test status
Simulation time 3146142207 ps
CPU time 3.9 seconds
Started Jun 23 05:55:31 PM PDT 24
Finished Jun 23 05:55:35 PM PDT 24
Peak memory 202032 kb
Host smart-1df4d658-5658-4d24-8a6e-7127d506bdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276948487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.276948487
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1977428107
Short name T388
Test name
Test status
Simulation time 5646361621 ps
CPU time 4.47 seconds
Started Jun 23 05:55:23 PM PDT 24
Finished Jun 23 05:55:28 PM PDT 24
Peak memory 202128 kb
Host smart-c34de5d5-9e3e-4749-b966-0b36ba9725e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977428107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1977428107
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2023796416
Short name T741
Test name
Test status
Simulation time 327458253257 ps
CPU time 345.38 seconds
Started Jun 23 05:55:31 PM PDT 24
Finished Jun 23 06:01:17 PM PDT 24
Peak memory 202244 kb
Host smart-d46b26a1-718c-467e-a05c-dbbbc82638e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023796416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2023796416
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.38470992
Short name T210
Test name
Test status
Simulation time 46421739912 ps
CPU time 98.56 seconds
Started Jun 23 05:55:27 PM PDT 24
Finished Jun 23 05:57:06 PM PDT 24
Peak memory 210560 kb
Host smart-463a8c4d-6bf3-43f5-a945-d03dd5253e33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38470992 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.38470992
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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