Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7213	1			T8	7		T9	20		T12	57
testmodes[AdcCtrlTestmodeNormal]	5665	1			T1	3		T3	1		T4	1
testmodes[AdcCtrlTestmodeLowpower]	5821	1			T2	14		T5	3		T7	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3940	1			T8	3		T9	19		T12	21
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1814	1			T8	4		T12	18		T40	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1346	1			T12	18		T40	3		T13	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1803	1			T8	3		T12	24		T40	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2096	1			T1	2		T6	1		T8	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1435	1			T12	14		T40	2		T13	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1356	1			T8	1		T12	11		T40	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1418	1			T12	21		T37	1		T40	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2791	1			T2	13		T5	2		T12	15