Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22954

1

T1

3

T2

14

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3408

1

T3

12

T5

22

T6

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20792

1

T2

14

T5

22

T6

17

auto[1]

5570

1

T1

3

T3

12

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T222	1		T223	1		-	-
values[0]	91	1			T6	22		T224	29		T167	1
values[1]	736	1			T5	41		T12	10		T13	4
values[2]	568	1			T3	12		T29	8		T30	2
values[3]	658	1			T7	19		T8	23		T156	11
values[4]	582	1			T38	4		T156	12		T27	1
values[5]	2952	1			T1	3		T4	1		T6	17
values[6]	536	1			T37	16		T27	1		T149	13
values[7]	676	1			T31	9		T154	1		T42	7
values[8]	529	1			T13	2		T151	3		T225	1
values[9]	1229	1			T5	22		T10	5		T38	23
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1030	1			T3	12		T5	41		T6	22
values[1]	589	1			T7	19		T8	11		T29	8
values[2]	488	1			T8	12		T38	4		T156	11
values[3]	2859	1			T1	3		T4	1		T6	17
values[4]	778	1			T37	16		T40	3		T26	1
values[5]	538	1			T27	1		T31	9		T149	13
values[6]	709	1			T154	1		T42	6		T226	15
values[7]	491	1			T39	1		T13	2		T63	31
values[8]	854	1			T5	22		T10	5		T38	23
values[9]	223	1			T157	14		T150	13		T162	3
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T5	18		T13	3		T227	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	1		T6	11		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T150	1		T228	6		T46	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	9		T8	1		T29	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	10		T63	9		T153	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T38	4		T156	1		T152	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T1	3		T4	1		T6	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T37	16		T156	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T37	7		T40	3		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T159	10		T33	1		T228	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	1		T31	1		T149	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T194	2		T158	1		T164	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T42	4		T226	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T154	1		T226	14		T89	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	1		T63	15		T151	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	1		T225	1		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T10	2		T41	4		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T5	14		T38	12		T227	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T157	1		T162	3		T229	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T150	7		T230	3		T231	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	23		T13	1		T227	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	11		T6	11		T12	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T150	11		T46	1		T224	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	10		T8	10		T227	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T8	2		T63	10		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T156	10		T198	2		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T6	8		T232	28		T192	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T37	13		T156	11		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	9		T150	13		T151	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T159	10		T179	9		T206	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T31	8		T86	13		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T164	16		T234	6		T235	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T42	2		T44	6		T236	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T89	12		T176	1		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	1		T63	16		T159	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T229	11		T180	14		T124	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	3		T41	2		T237	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T5	8		T38	11		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T157	13		T229	16		T238	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T150	6		T239	2		T240	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T223	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T222	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T224	15		T241	6		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T6	11		T167	1		T243	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	18		T13	3		T227	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T27	1		T244	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T226	1		T244	11		T228	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T29	8		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	10		T63	9		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	9		T8	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T157	1		T245	1		T246	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T38	4		T156	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T1	3		T4	1		T6	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T37	16		T163	16		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	7		T27	1		T149	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T194	2		T33	1		T206	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T31	1		T42	5		T236	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T154	1		T89	14		T164	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T151	3		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T225	1		T226	14		T247	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	2		T157	1		T63	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T5	14		T38	12		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T224	14		T242	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T6	11		T248	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	23		T13	1		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	9		T244	11		T176	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T244	3		T46	1		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	11		T227	5		T63	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	2		T63	10		T150	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	10		T8	10		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T246	9		T249	3		T250	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T156	11		T84	9		T198	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T6	8		T232	28		T150	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T37	13		T163	11		T159	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T37	9		T86	13		T159	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T206	9		T148	1		T234	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T31	8		T42	2		T236	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T89	12		T164	16		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	1		T44	6		T159	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T176	1		T180	14		T224	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	3		T157	13		T63	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T5	8		T38	11		T227	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T5	25		T13	4		T227	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T3	12		T6	12		T12	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T150	12		T228	1		T46	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	11		T8	11		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	3		T63	11		T153	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T38	1		T156	11		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T1	3		T4	1		T6	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T37	14		T156	12		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T37	10		T40	2		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T159	11		T33	1		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T27	1		T31	9		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T194	1		T158	1		T164	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T42	4		T226	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T154	1		T226	1		T89	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	2		T63	17		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T39	1		T225	1		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	4		T41	4		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T5	9		T38	12		T227	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T157	14		T162	1		T229	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T150	7		T230	1		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	16		T227	11		T152	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	10		T89	2		T244	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T228	5		T46	1		T224	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	8		T29	7		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	9		T63	8		T153	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T38	3		T152	13		T177	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T6	8		T24	26		T25	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T37	15		T163	15		T84	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T37	6		T40	1		T150	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T159	9		T228	12		T206	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T149	12		T233	10		T251	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T194	1		T164	14		T252	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T236	12		T239	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T226	13		T89	13		T181	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T63	14		T151	2		T159	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T247	10		T229	11		T253	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T10	1		T41	2		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	13		T38	11		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T162	2		T229	12		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T150	6		T230	2		T231	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T223	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T222	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T224	15		T241	1		T242	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T6	12		T167	1		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	25		T13	4		T227	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	10		T27	1		T244	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T226	1		T244	4		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	12		T29	1		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	3		T63	11		T150	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	11		T8	11		T156	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T157	1		T245	1		T246	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	1		T156	12		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T1	3		T4	1		T6	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T37	14		T163	12		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T37	10		T27	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T194	1		T33	1		T206	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T31	9		T42	5		T236	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T154	1		T89	13		T164	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	2		T151	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T225	1		T226	1		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T10	4		T157	14		T63	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T5	9		T38	12		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T224	14		T241	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T6	10		T243	8		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	16		T227	11		T152	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T244	9		T176	6		T251	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T244	10		T228	5		T46	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	7		T227	7		T63	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	9		T63	8		T153	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	8		T152	13		T163	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T246	14		T250	17		T104	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T38	3		T84	9		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T6	8		T40	1		T24	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T37	15		T163	15		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	6		T149	12		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T194	1		T206	7		T235	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T42	2		T236	12		T239	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T89	13		T164	14		T252	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T151	2		T159	11		T254	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T226	13		T247	10		T255	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	1		T63	14		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T5	13		T38	11		T227	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23200

1

T1

3

T2

14

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3162

1

T5

26

T6

17

T10

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20544

1

T2

14

T3

12

T5

37

auto[1]

5818

1

T1

3

T4

1

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	385	1			T12	1		T40	3		T13	2
values[0]	55	1			T12	10		T27	1		T256	11
values[1]	890	1			T5	26		T6	17		T8	12
values[2]	2645	1			T1	3		T4	1		T11	3
values[3]	794	1			T3	12		T7	19		T37	29
values[4]	643	1			T156	12		T13	4		T27	1
values[5]	649	1			T37	16		T149	1		T227	13
values[6]	673	1			T5	15		T6	22		T38	4
values[7]	550	1			T8	11		T39	1		T27	1
values[8]	699	1			T150	12		T226	1		T86	14
values[9]	948	1			T5	22		T10	5		T40	3
minimum	17431	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1058	1			T5	26		T6	17		T8	12
values[1]	2806	1			T1	3		T4	1		T7	19
values[2]	700	1			T156	12		T149	13		T157	1
values[3]	540	1			T3	12		T37	16		T13	4
values[4]	769	1			T6	22		T38	4		T150	27
values[5]	708	1			T5	15		T29	8		T30	1
values[6]	417	1			T8	11		T39	1		T27	1
values[7]	757	1			T227	21		T42	6		T225	1
values[8]	709	1			T5	22		T10	5		T40	3
values[9]	89	1			T30	1		T43	3		T89	26
minimum	17809	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T8	10		T27	1		T150	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	14		T6	9		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T1	3		T4	1		T7	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	16		T163	16		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T156	1		T63	12		T244	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T149	13		T157	1		T257	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	1		T37	7		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	3		T149	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	11		T38	4		T150	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T225	1		T158	1		T89	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	4		T29	8		T153	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T30	1		T227	8		T152	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T8	1		T178	1		T258	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	1		T27	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T226	1		T245	1		T236	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T227	12		T42	4		T225	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	14		T40	3		T162	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	2		T31	1		T227	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T259	1		T170	10		T260	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T30	1		T43	3		T89	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17688	1			T2	14		T8	14		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	2		T150	6		T161	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	12		T6	8		T12	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	884	1			T7	10		T232	28		T192	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	13		T163	11		T159	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T156	11		T63	14		T244	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T176	1		T46	22		T261	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	11		T37	9		T180	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	1		T157	13		T84	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	11		T150	13		T195	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T89	10		T229	16		T210	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	11		T153	8		T163	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T227	5		T262	2		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T8	10		T99	7		T263	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T150	11		T86	13		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T236	10		T176	9		T160	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T227	9		T42	2		T163	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	8		T182	17		T264	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	3		T31	8		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T259	6		T170	11		T260	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T89	12		T14	3		T265	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	3		T13	2		T43	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	373	1			T12	1		T40	3		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T226	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T27	1		T266	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T12	1		T256	1		T186	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T8	10		T150	7		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	14		T6	9		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T1	3		T4	1		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T38	12		T163	16		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	1		T7	9		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T37	16		T149	13		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T156	1		T27	1		T63	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	3		T157	1		T194	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T37	7		T153	4		T195	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T149	1		T227	8		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	4		T6	11		T38	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	1		T45	4		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	1		T29	8		T84	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	1		T27	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T226	1		T236	13		T176	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T150	1		T86	1		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	14		T40	3		T162	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	2		T30	1		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17312	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T234	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T266	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T12	9		T256	10		T186	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	2		T150	6		T268	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	12		T6	8		T156	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	849	1			T232	28		T192	20		T269	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T38	11		T163	11		T180	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	11		T7	10		T63	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	13		T159	10		T176	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T156	11		T63	4		T244	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T157	13		T84	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T37	9		T153	8		T195	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T227	5		T89	10		T229	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	11		T6	11		T150	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T45	3		T270	2		T46	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T8	10		T84	9		T224	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T244	11		T262	2		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T236	10		T176	9		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T150	11		T86	13		T159	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	8		T224	14		T182	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T10	3		T31	8		T227	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1