Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22969

1

T1

3

T2

14

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3393

1

T3

12

T5

26

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20890

1

T2

14

T5

63

T6

17

auto[1]

5472

1

T1

3

T3

12

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T7	19		T10	5		T63	7
values[0]	22	1			T227	21		T305	1		-	-
values[1]	762	1			T5	26		T6	17		T37	16
values[2]	655	1			T38	4		T153	12		T162	11
values[3]	742	1			T12	10		T227	21		T157	14
values[4]	586	1			T38	23		T156	12		T26	1
values[5]	576	1			T39	1		T63	19		T150	1
values[6]	673	1			T6	22		T8	23		T30	1
values[7]	687	1			T5	37		T37	29		T157	1
values[8]	2798	1			T1	3		T3	12		T4	1
values[9]	787	1			T40	3		T13	6		T30	1
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	720	1			T37	16		T227	21		T162	3
values[1]	694	1			T5	26		T38	4		T157	14
values[2]	718	1			T12	10		T156	12		T29	8
values[3]	493	1			T38	23		T39	1		T26	1
values[4]	605	1			T227	13		T63	19		T150	1
values[5]	747	1			T5	22		T6	22		T8	23
values[6]	2667	1			T1	3		T3	12		T4	1
values[7]	787	1			T5	15		T156	11		T13	6
values[8]	724	1			T7	19		T10	5		T40	3
values[9]	142	1			T150	27		T163	29		T165	3
minimum	18065	1			T2	14		T6	17		T8	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T162	3		T163	16		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	7		T227	12		T89	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T42	1		T247	11		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	14		T38	4		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T227	11		T150	7		T151	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T156	1		T29	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T38	12		T39	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T26	1		T27	2		T226	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T227	8		T43	3		T277	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T63	9		T150	1		T41	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	14		T6	11		T8	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	1		T194	2		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T1	3		T4	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T152	16		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	4		T156	1		T152	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T13	4		T63	15		T151	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	2		T63	3		T151	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	9		T40	3		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T165	3		T17	2		T286	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T150	14		T163	15		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T2	14		T6	9		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T176	7		T148	1		T299	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T163	11		T176	7		T46	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	9		T227	9		T89	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T289	8		T124	7		T306	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	12		T157	13		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T227	10		T150	6		T89	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	9		T156	11		T237	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T38	11		T84	12		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T262	2		T46	4		T183	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T227	5		T45	3		T251	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T63	10		T41	2		T163	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	8		T6	11		T8	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T244	11		T159	10		T290	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	843	1			T37	13		T31	8		T232	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	11		T195	6		T233	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	11		T156	10		T86	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	2		T63	16		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	3		T63	4		T151	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	10		T44	6		T219	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T286	2		T287	3		T291	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T150	13		T163	14		T256	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	8		T8	3		T13	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T176	9		T148	1		T299	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T10	2		T63	3		T258	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T7	9		T163	15		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T227	12		T305	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	9		T149	13		T162	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	14		T37	7		T89	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T163	16		T158	1		T247	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T38	4		T153	4		T162	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T227	11		T151	3		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	1		T157	1		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T38	12		T27	1		T150	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T156	1		T26	1		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	1		T43	3		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T63	9		T150	1		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	11		T8	11		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	1		T194	2		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	18		T37	16		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T152	16		T195	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T1	3		T4	1		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	1		T63	15		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T151	8		T152	14		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T40	3		T13	4		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T10	3		T63	4		T183	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T7	10		T163	14		T272	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T227	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	8		T268	13		T46	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	12		T37	9		T89	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T163	11		T176	7		T289	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T153	8		T42	2		T229	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T227	10		T159	10		T206	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	9		T157	13		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T38	11		T150	6		T84	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T156	11		T262	2		T210	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T45	3		T251	10		T184	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T63	10		T41	2		T163	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	11		T8	12		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T244	11		T159	10		T268	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	19		T37	13		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T195	6		T182	31		T249	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T156	10		T232	28		T192	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	11		T63	16		T84	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T151	8		T176	1		T180	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	2		T150	13		T151	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T162	1		T163	12		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T37	10		T227	10		T89	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T42	1		T247	1		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	13		T38	1		T157	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T227	11		T150	7		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	10		T156	12		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T38	12		T39	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T26	1		T27	2		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T227	6		T43	2		T277	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T63	11		T150	1		T41	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	9		T6	12		T8	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T30	1		T194	1		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T1	3		T4	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	12		T152	1		T195	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	12		T156	11		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	6		T63	17		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	4		T63	5		T151	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	11		T40	2		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T165	1		T17	1		T286	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T150	14		T163	15		T256	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17838	1			T2	14		T6	9		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T176	10		T148	2		T299	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T162	2		T163	15		T176	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T37	6		T227	11		T89	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T247	10		T289	6		T124	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	13		T38	3		T153	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T227	10		T150	6		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T29	7		T89	11		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T38	11		T84	9		T224	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T226	13		T228	12		T46	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T227	7		T43	1		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T63	8		T41	2		T163	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	13		T6	10		T8	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T194	1		T244	9		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1136	1			T37	15		T24	26		T25	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T152	15		T84	2		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	3		T152	13		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T63	14		T151	3		T84	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	1		T63	2		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	8		T40	1		T219	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T165	2		T17	1		T286	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T150	13		T163	14		T213	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T6	8		T149	12		T268	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T176	6		T299	9		T308	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T10	4		T63	5		T258	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T7	11		T163	15		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T227	10		T305	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	9		T149	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T5	13		T37	10		T89	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T163	12		T158	1		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T38	1		T153	9		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T227	11		T151	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	10		T157	14		T237	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T38	12		T27	1		T150	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T156	12		T26	1		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	1		T43	2		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T63	11		T150	1		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	12		T8	14		T31	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	1		T194	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	21		T37	14		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T152	1		T195	7		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T1	3		T4	1		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	12		T63	17		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T151	9		T152	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T40	2		T13	6		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T10	1		T63	2		T183	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T7	8		T163	14		T253	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T227	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	8		T149	12		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	13		T37	6		T89	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T163	15		T247	10		T176	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T38	3		T153	3		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T227	10		T151	2		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T89	11		T236	12		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T38	11		T150	6		T84	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T29	7		T226	13		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T43	1		T45	1		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T63	8		T41	2		T163	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	10		T8	9		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T194	1		T244	9		T159	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	16		T37	15		T206	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T152	15		T84	2		T228	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T24	26		T25	16		T28	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T63	14		T84	9		T233	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T151	7		T152	13		T252	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	1		T150	13		T151	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8