Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23041

1

T1

3

T2

14

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3321

1

T3

12

T5

15

T6

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20531

1

T2

14

T3

12

T5

37

auto[1]

5831

1

T1

3

T4

1

T5

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T228	13		T98	1		-	-
values[0]	71	1			T89	22		T219	18		T238	12
values[1]	539	1			T12	10		T39	1		T156	12
values[2]	720	1			T5	26		T6	17		T38	4
values[3]	628	1			T3	12		T8	11		T156	11
values[4]	2688	1			T1	3		T4	1		T11	3
values[5]	694	1			T6	22		T37	16		T13	2
values[6]	781	1			T37	29		T27	1		T30	1
values[7]	569	1			T38	23		T40	3		T31	9
values[8]	631	1			T227	21		T157	14		T151	16
values[9]	1224	1			T5	37		T7	19		T8	12
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	809	1			T12	10		T38	4		T156	12
values[1]	628	1			T3	12		T5	26		T6	17
values[2]	633	1			T156	11		T13	4		T149	1
values[3]	2665	1			T1	3		T4	1		T11	3
values[4]	846	1			T6	22		T37	16		T27	1
values[5]	522	1			T37	29		T31	9		T152	14
values[6]	634	1			T38	23		T40	3		T63	7
values[7]	758	1			T227	21		T157	14		T151	16
values[8]	805	1			T8	12		T227	13		T157	1
values[9]	209	1			T5	37		T7	19		T10	5
minimum	17853	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T156	1		T149	13		T150	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	1		T38	4		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	14		T247	1		T246	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	1		T6	9		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T156	1		T149	1		T162	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	3		T63	9		T150	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T1	3		T4	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T30	1		T159	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	11		T37	7		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T27	1		T30	1		T42	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	16		T31	1		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T152	14		T159	10		T289	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T38	12		T40	3		T63	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T162	11		T84	3		T244	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T157	1		T226	14		T262	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T227	12		T151	8		T163	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	10		T227	8		T63	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T157	1		T195	1		T176	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T5	14		T7	9		T10	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T5	4		T43	1		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17685	1			T2	14		T8	14		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T219	10		T310	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T156	11		T150	6		T151	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	9		T89	10		T160	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	12		T246	9		T268	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	11		T6	8		T8	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T156	10		T84	12		T176	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	1		T63	10		T150	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	819	1			T232	28		T192	20		T237	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	1		T159	21		T249	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	11		T37	9		T46	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T42	2		T84	9		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T37	13		T31	8		T163	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T159	10		T289	8		T293	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T38	11		T63	4		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T244	11		T176	9		T285	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T157	13		T262	2		T251	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T227	9		T151	8		T163	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	2		T227	5		T63	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T195	6		T176	7		T268	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T5	8		T7	10		T10	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T5	11		T311	8		T201	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	3		T13	2		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T219	8		T310	13		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T228	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T98	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T272	8		T240	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T89	12		T219	10		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T156	1		T150	7		T152	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T39	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	14		T149	13		T151	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	9		T38	4		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T156	1		T162	3		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	1		T8	1		T13	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1476	1			T1	3		T4	1		T11	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T30	1		T151	3		T84	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	11		T37	7		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T159	10		T233	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	16		T225	1		T163	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T27	1		T30	1		T162	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T38	12		T40	3		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T152	14		T270	1		T271	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T157	1		T262	1		T177	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T227	12		T151	8		T163	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T5	14		T7	9		T8	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T5	4		T157	1		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T272	7		T240	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T89	10		T219	8		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T156	11		T150	6		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T12	9		T160	2		T268	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	12		T151	12		T89	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	8		T150	13		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T156	10		T84	12		T176	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	11		T8	10		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	807	1			T232	28		T192	20		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T84	9		T159	11		T164	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	11		T37	9		T86	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	1		T159	10		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T37	13		T163	9		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T42	2		T244	11		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T38	11		T31	8		T63	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T293	5		T239	10		T280	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T157	13		T262	2		T251	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T227	9		T151	8		T163	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T5	8		T7	10		T8	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T5	11		T195	6		T229	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T156	12		T149	1		T150	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	10		T38	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	13		T247	1		T246	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	12		T6	9		T8	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T156	11		T149	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	4		T63	11		T150	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T1	3		T4	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	2		T30	1		T159	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T6	12		T37	10		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T27	1		T30	1		T42	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	14		T31	9		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T152	1		T159	11		T289	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T38	12		T40	2		T63	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T162	1		T84	1		T244	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T157	14		T226	1		T262	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T227	10		T151	9		T163	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	3		T227	6		T63	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T157	1		T195	7		T176	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T5	9		T7	11		T10	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T5	12		T43	1		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17806	1			T2	14		T8	17		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T219	9		T310	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T149	12		T150	6		T151	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T38	3		T89	11		T160	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	13		T246	14		T268	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	8		T29	7		T153	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T162	2		T194	1		T84	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T63	8		T150	13		T151	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T24	26		T25	16		T28	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T159	20		T258	8		T272	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	10		T37	6		T160	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T42	2		T84	9		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T37	15		T163	4		T224	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T152	13		T159	9		T289	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	11		T40	1		T63	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T162	10		T84	2		T244	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T226	13		T251	6		T183	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T227	11		T151	7		T163	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	9		T227	7		T63	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T176	10		T268	9		T224	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T5	13		T7	8		T10	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T5	3		T311	12		T201	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T219	9		T310	15		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T228	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T98	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T272	8		T240	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T89	11		T219	9		T238	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T156	12		T150	7		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	10		T39	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	13		T149	1		T151	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	9		T38	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T156	11		T162	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	12		T8	11		T13	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1129	1			T1	3		T4	1		T11	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T30	1		T151	1		T84	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	12		T37	10		T86	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	2		T159	11		T233	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T37	14		T225	1		T163	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T27	1		T30	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T38	12		T40	2		T31	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T152	1		T270	1		T271	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T157	14		T262	3		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T227	10		T151	9		T163	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T5	9		T7	11		T8	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T5	12		T157	1		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T228	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T272	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T89	11		T219	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T150	6		T152	15		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T160	11		T268	14		T253	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	13		T149	12		T151	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	8		T38	3		T29	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T162	2		T194	1		T84	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T63	8		T196	6		T244	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T24	26		T25	16		T28	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T151	2		T84	9		T159	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	10		T37	6		T160	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T159	9		T233	10		T164	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T37	15		T163	4		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T162	10		T42	2		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T38	11		T40	1		T63	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T152	13		T271	15		T293	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T177	3		T251	6		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T227	11		T151	7		T163	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T5	13		T7	8		T8	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	3		T229	12		T176	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8