Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22999

1

T1

3

T2

14

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3363

1

T5

41

T6

17

T8

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20777

1

T2

14

T5

63

T6

17

auto[1]

5585

1

T1

3

T3

12

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	309	1			T3	12		T12	10		T227	13
values[0]	29	1			T272	17		T284	12		-	-
values[1]	733	1			T6	22		T227	21		T157	14
values[2]	495	1			T6	17		T8	12		T13	4
values[3]	661	1			T10	5		T40	3		T150	12
values[4]	534	1			T5	15		T156	11		T27	1
values[5]	807	1			T38	23		T156	12		T13	2
values[6]	564	1			T27	1		T227	21		T86	14
values[7]	649	1			T8	11		T157	1		T63	26
values[8]	785	1			T5	26		T7	19		T150	13
values[9]	2993	1			T1	3		T4	1		T5	22
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	527	1			T13	4		T153	12		T151	16
values[1]	482	1			T6	17		T8	12		T26	1
values[2]	737	1			T10	5		T40	3		T150	12
values[3]	631	1			T5	15		T156	11		T27	1
values[4]	745	1			T38	23		T156	12		T13	2
values[5]	550	1			T27	1		T227	21		T157	1
values[6]	2759	1			T1	3		T4	1		T8	11
values[7]	811	1			T5	48		T7	19		T27	1
values[8]	867	1			T12	10		T37	45		T39	1
values[9]	150	1			T3	12		T38	4		T63	31
minimum	18103	1			T2	14		T6	22		T8	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	3		T153	4		T151	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T84	10		T45	4		T251	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T26	1		T150	14		T44	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	9		T8	10		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T10	2		T150	1		T226	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	3		T163	16		T257	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T156	1		T27	1		T29	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	4		T149	1		T194	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T38	12		T156	1		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T31	1		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T42	1		T262	1		T233	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T27	1		T227	11		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T1	3		T4	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	1		T150	7		T163	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	14		T7	9		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	14		T149	13		T163	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T37	7		T39	1		T227	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T37	16		T151	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T3	1		T38	4		T314	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T63	15		T255	8		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17773	1			T2	14		T6	11		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T183	11		T235	20		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T13	1		T153	8		T151	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T84	9		T45	3		T251	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T150	13		T44	6		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T6	8		T8	2		T89	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	3		T150	11		T268	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T163	11		T229	16		T246	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T156	10		T176	1		T272	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	11		T195	6		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	11		T156	11		T89	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T31	8		T159	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T262	2		T233	8		T264	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T227	10		T63	10		T86	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	860	1			T232	28		T63	4		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	10		T150	6		T163	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	8		T7	10		T151	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	12		T163	9		T237	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	9		T227	5		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	9		T37	13		T268	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T3	11		T315	11		T119	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T63	16		T148	1		T316	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	11		T8	3		T13	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T183	11		T235	12		T283	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T3	1		T227	8		T150	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T12	1		T268	15		T255	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T272	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T284	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	11		T227	12		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T84	10		T45	4		T251	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	3		T26	1		T150	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	9		T8	10		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	2		T150	1		T226	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	3		T152	16		T43	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T156	1		T27	1		T29	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	4		T194	2		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T38	12		T156	1		T152	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	1		T31	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T262	1		T253	9		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T27	1		T227	11		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T63	3		T41	4		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	1		T157	1		T63	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	9		T43	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	14		T150	7		T163	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T1	3		T4	1		T5	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T37	16		T149	13		T63	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T3	11		T227	5		T183	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T12	9		T268	8		T148	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T272	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T284	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	11		T227	9		T157	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T84	9		T45	3		T251	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T13	1		T150	13		T44	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	8		T8	2		T89	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	3		T150	11		T268	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T163	11		T244	11		T246	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T156	10		T176	1		T46	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T5	11		T270	2		T46	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T38	11		T156	11		T89	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	1		T31	8		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T262	2		T234	11		T97	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T227	10		T86	13		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T63	4		T41	2		T89	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T8	10		T63	10		T163	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	10		T84	12		T236	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	12		T150	6		T163	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T5	8		T37	9		T232	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T37	13		T63	16		T237	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	4		T153	9		T151	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T84	10		T45	6		T251	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	1		T150	14		T44	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T6	9		T8	3		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	4		T150	12		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	2		T163	12		T257	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T156	11		T27	1		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	12		T149	1		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T38	12		T156	12		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	2		T31	9		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T42	1		T262	3		T233	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T27	1		T227	11		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T1	3		T4	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	11		T150	7		T163	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	9		T7	11		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	13		T149	1		T163	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T37	10		T39	1		T227	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	10		T37	14		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T3	12		T38	1		T314	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T63	17		T255	1		T148	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17908	1			T2	14		T6	12		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T183	12		T235	13		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T153	3		T151	3		T293	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T84	9		T45	1		T251	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T150	13		T160	4		T228	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T6	8		T8	9		T152	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	1		T226	13		T268	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	1		T163	15		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T29	7		T126	3		T272	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	3		T194	1		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T38	11		T152	13		T89	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T159	20		T164	14		T251	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T233	10		T253	8		T264	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T227	10		T63	8		T161	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T24	26		T25	16		T28	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T150	6		T163	14		T84	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	13		T7	8		T151	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	13		T149	12		T163	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	6		T227	7		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T37	15		T151	2		T196	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T38	3		T314	21		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T63	14		T255	7		T295	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T6	10		T227	11		T162	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T183	10		T235	19		T283	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T3	12		T227	6		T150	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T12	10		T268	9		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T272	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T284	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	12		T227	10		T157	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T84	10		T45	6		T251	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	4		T26	1		T150	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	9		T8	3		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	4		T150	12		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	2		T152	1		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T156	11		T27	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	12		T194	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T38	12		T156	12		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	2		T31	9		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T262	3		T253	1		T234	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T27	1		T227	11		T86	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T63	5		T41	4		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	11		T157	1		T63	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	11		T43	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	13		T150	7		T163	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T1	3		T4	1		T5	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T37	14		T149	1		T63	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T227	7		T162	10		T183	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T268	14		T255	7		T185	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T272	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T284	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	10		T227	11		T153	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T84	9		T45	1		T251	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T150	13		T160	4		T228	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T6	8		T8	9		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	1		T226	13		T268	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	1		T152	15		T43	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T29	7		T46	1		T182	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	3		T194	1		T165	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T38	11		T152	13		T89	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T159	20		T164	14		T228	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T253	8		T97	2		T170	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T227	10		T159	9		T161	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T63	2		T41	2		T89	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T63	8		T163	14		T224	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	8		T84	9		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	13		T150	6		T163	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T5	13		T37	6		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	15		T149	12		T63	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8