Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23165

1

T1

3

T2

14

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3197

1

T5

22

T6

17

T10

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20830

1

T2

14

T7

19

T8

28

auto[1]

5532

1

T1

3

T3

12

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	292	1			T244	21		T46	2		T253	3
values[0]	43	1			T84	3		T176	16		T126	4
values[1]	523	1			T5	15		T8	12		T27	1
values[2]	672	1			T5	26		T13	4		T63	50
values[3]	915	1			T7	19		T37	29		T38	23
values[4]	654	1			T5	22		T27	1		T29	8
values[5]	2537	1			T1	3		T4	1		T11	3
values[6]	749	1			T3	12		T40	3		T226	1
values[7]	529	1			T6	22		T8	11		T156	12
values[8]	523	1			T157	1		T150	13		T41	6
values[9]	1122	1			T6	17		T10	5		T39	1
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	546	1			T5	15		T8	12		T13	4
values[1]	656	1			T5	26		T30	1		T227	21
values[2]	960	1			T5	22		T7	19		T37	29
values[3]	2650	1			T1	3		T4	1		T11	3
values[4]	515	1			T38	4		T40	3		T151	3
values[5]	654	1			T3	12		T6	22		T27	1
values[6]	569	1			T8	11		T156	12		T13	2
values[7]	551	1			T39	1		T149	13		T157	1
values[8]	1070	1			T6	17		T10	5		T149	1
values[9]	156	1			T253	3		T51	3		T271	16
minimum	18035	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	4		T8	10		T13	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T63	9		T225	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	14		T227	11		T63	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T30	1		T162	11		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	9		T37	16		T38	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	14		T156	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T1	3		T4	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	1		T37	7		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T38	4		T40	3		T151	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T246	1		T176	11		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T6	11		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T27	1		T267	1		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	1		T156	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T41	4		T194	2		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	1		T157	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T149	13		T150	1		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T149	1		T151	4		T226	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T6	9		T10	2		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T185	14		T317	1		T318	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T253	3		T51	2		T271	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17725	1			T2	14		T8	14		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T163	16		T176	7		T275	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	11		T8	2		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T63	10		T159	11		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	12		T227	10		T63	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T42	2		T262	2		T45	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	10		T37	13		T38	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	8		T156	10		T31	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	867	1			T232	28		T157	13		T192	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	9		T37	9		T227	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T244	3		T176	1		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T176	7		T302	13		T166	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	11		T6	11		T89	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T198	2		T229	11		T164	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	10		T156	11		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T41	2		T161	2		T46	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T151	8		T229	16		T182	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T150	11		T237	1		T270	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T151	12		T86	13		T244	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	8		T10	3		T44	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T185	3		T318	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T51	1		T256	6		T185	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	3		T13	2		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T163	11		T176	9		T275	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T244	10		T46	1		T148	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T253	3		T51	2		T271	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T126	4		T309	15		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T84	3		T176	7		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	4		T8	10		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T163	16		T158	1		T165	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	14		T13	3		T63	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T63	9		T162	11		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T7	9		T37	16		T38	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T156	1		T30	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T157	1		T226	1		T84	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	14		T27	1		T29	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1470	1			T1	3		T4	1		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T37	7		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T40	3		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T267	1		T229	12		T176	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	11		T8	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T27	1		T194	2		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T157	1		T150	1		T151	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T150	1		T41	4		T228	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T39	1		T149	1		T151	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T6	9		T10	2		T149	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T244	11		T46	1		T184	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T51	1		T256	6		T185	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T242	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T176	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	11		T8	2		T163	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T163	11		T46	1		T275	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	12		T13	1		T63	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T63	10		T42	2		T159	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	10		T37	13		T38	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T156	10		T31	8		T63	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T157	13		T84	12		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	8		T227	5		T84	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	835	1			T232	28		T192	20		T269	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T12	9		T37	9		T268	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	11		T89	12		T238	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T229	11		T176	7		T164	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	11		T8	10		T156	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T198	2		T161	2		T251	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T151	8		T182	14		T249	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T150	11		T41	2		T270	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T151	12		T86	13		T159	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	8		T10	3		T237	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	12		T8	3		T13	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T63	11		T225	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	13		T227	11		T63	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	1		T162	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T7	11		T37	14		T38	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T5	9		T156	11		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T1	3		T4	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	10		T37	10		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T38	1		T40	2		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T246	1		T176	8		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	12		T6	12		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T27	1		T267	1		T198	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	11		T156	12		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T41	4		T194	1		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	1		T157	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T149	1		T150	12		T237	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T149	1		T151	13		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T6	9		T10	4		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T185	4		T317	1		T318	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T253	1		T51	2		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17828	1			T2	14		T8	17		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T163	12		T176	10		T275	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	3		T8	9		T150	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T63	8		T84	2		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	13		T227	10		T63	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T162	10		T42	2		T45	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	8		T37	15		T38	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	13		T63	2		T84	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T24	26		T25	16		T28	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	6		T29	7		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T38	3		T40	1		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T176	10		T160	4		T302	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	10		T89	13		T177	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T229	11		T164	14		T251	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T247	10		T258	8		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T41	2		T194	1		T196	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T151	7		T229	12		T182	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T149	12		T228	17		T270	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T151	3		T226	13		T244	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T6	8		T10	1		T251	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T185	13		T318	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T253	2		T51	1		T271	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T246	14		T242	13		T320	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T163	15		T176	6		T275	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T244	12		T46	2		T148	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T253	1		T51	2		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T126	1		T309	1		T242	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T84	1		T176	10		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	12		T8	3		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T163	12		T158	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	13		T13	4		T63	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T63	11		T162	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T7	11		T37	14		T38	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T156	11		T30	1		T31	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T157	14		T226	1		T84	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	9		T27	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1155	1			T1	3		T4	1		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	10		T37	10		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	12		T40	2		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T267	1		T229	12		T176	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	12		T8	11		T156	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T27	1		T194	1		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T157	1		T150	1		T151	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T150	12		T41	4		T228	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T39	1		T149	1		T151	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	9		T10	4		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T244	9		T184	10		T185	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T253	2		T51	1		T271	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T126	3		T309	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T84	2		T176	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	3		T8	9		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T163	15		T165	2		T46	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	13		T63	14		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T63	8		T162	10		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	8		T37	15		T38	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T63	2		T45	1		T251	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T84	9		T252	4		T160	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	13		T29	7		T227	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T38	3		T24	26		T25	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T37	6		T160	4		T268	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T40	1		T89	13		T177	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T229	11		T176	10		T164	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	10		T258	8		T224	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T194	1		T196	6		T161	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T151	7		T247	10		T182	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T41	2		T228	17		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T151	3		T226	13		T159	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	8		T10	1		T149	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8