Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21027

1

T2

14

T3

12

T5

37

auto[ADC_CTRL_FILTER_COND_OUT]

5335

1

T1

3

T4

1

T5

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20691

1

T2

14

T3

12

T6

22

auto[1]

5671

1

T1

3

T4

1

T5

63

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	285	1			T156	12		T157	1		T321	1
values[0]	37	1			T228	13		T322	3		T296	21
values[1]	496	1			T8	12		T38	4		T30	1
values[2]	641	1			T6	22		T38	23		T156	11
values[3]	617	1			T5	22		T6	17		T37	29
values[4]	515	1			T12	10		T27	1		T63	31
values[5]	664	1			T5	26		T10	5		T27	1
values[6]	826	1			T13	4		T30	1		T227	21
values[7]	768	1			T37	16		T149	1		T155	1
values[8]	580	1			T3	12		T5	15		T7	19
values[9]	3130	1			T1	3		T4	1		T8	11
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	603	1			T6	22		T8	12		T38	27
values[1]	2732	1			T1	3		T4	1		T6	17
values[2]	454	1			T5	22		T26	1		T86	14
values[3]	621	1			T5	26		T12	10		T27	1
values[4]	660	1			T10	5		T13	4		T27	1
values[5]	820	1			T37	16		T30	1		T149	1
values[6]	701	1			T195	7		T44	9		T247	1
values[7]	672	1			T3	12		T5	15		T7	19
values[8]	964	1			T8	11		T156	12		T40	3
values[9]	187	1			T29	8		T227	21		T157	1
minimum	17948	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	10		T151	8		T89	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	11		T38	16		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	9		T37	16		T45	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1466	1			T1	3		T4	1		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	14		T26	1		T251	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T86	1		T87	1		T176	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T151	7		T163	15		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	14		T12	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	2		T27	1		T149	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	3		T63	9		T181	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T37	7		T149	1		T150	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T30	1		T227	12		T63	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	3		T236	13		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T195	1		T247	1		T244	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T5	4		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	9		T27	1		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T8	1		T150	1		T194	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T156	1		T40	3		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T29	8		T294	12		T260	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T227	11		T157	1		T323	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17718	1			T2	14		T8	14		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T227	8		T42	4		T87	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	2		T151	8		T89	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	11		T38	11		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	8		T37	13		T45	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	885	1			T31	8		T232	28		T157	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T5	8		T251	11		T50	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T86	13		T176	7		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T151	12		T163	14		T246	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	12		T12	9		T63	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	3		T41	2		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T63	10		T183	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	9		T150	6		T163	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T227	9		T63	4		T153	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T44	6		T236	10		T272	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T195	6		T244	11		T184	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	11		T5	11		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	10		T150	13		T163	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	10		T150	11		T159	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T156	11		T180	9		T251	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T294	8		T260	2		T67	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T227	10		T323	11		T104	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	3		T13	2		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T227	5		T42	2		T249	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T321	1		T219	10		T179	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T156	1		T157	1		T46	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T228	13		T322	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T296	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T8	10		T151	8		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	4		T30	1		T227	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T89	12		T45	4		T229	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	11		T38	12		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	14		T6	9		T37	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T158	1		T84	10		T86	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T151	3		T163	15		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	1		T27	1		T63	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	2		T27	1		T149	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	14		T181	13		T51	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T150	8		T152	14		T163	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	3		T30	1		T227	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T37	7		T149	1		T44	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T155	1		T195	1		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	1		T5	4		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	9		T27	1		T150	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T8	1		T29	8		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1603	1			T1	3		T4	1		T11	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T219	8		T179	9		T256	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T156	11		T46	4		T206	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T322	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T296	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T8	2		T151	8		T244	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T227	5		T42	2		T89	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T89	10		T45	3		T229	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	11		T38	11		T156	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T5	8		T6	8		T37	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T84	12		T86	13		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T163	14		T246	9		T182	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T12	9		T63	16		T268	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	3		T41	2		T151	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	12		T51	1		T302	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T150	6		T163	9		T229	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T227	9		T63	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	9		T44	6		T236	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T195	6		T244	11		T290	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	11		T5	11		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	10		T150	13		T164	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	10		T150	11		T159	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	993	1			T232	28		T227	10		T192	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	3		T151	9		T89	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	12		T38	13		T156	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	9		T37	14		T45	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1211	1			T1	3		T4	1		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	9		T26	1		T251	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T86	14		T87	1		T176	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T151	14		T163	15		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	13		T12	10		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	4		T27	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	4		T63	11		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T37	10		T149	1		T150	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T30	1		T227	10		T63	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T44	9		T236	11		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T195	7		T247	1		T244	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	12		T5	12		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	11		T27	1		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T8	11		T150	12		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T156	12		T40	2		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T29	1		T294	9		T260	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T227	11		T157	1		T323	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17823	1			T2	14		T8	17		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T227	6		T42	4		T87	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	9		T151	7		T89	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	10		T38	14		T152	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	8		T37	15		T45	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1140	1			T24	26		T25	16		T28	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T5	13		T251	8		T50	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T176	10		T46	22		T258	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T151	5		T163	14		T246	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	13		T63	14		T268	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	1		T149	12		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T63	8		T181	12		T183	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T37	6		T150	6		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T227	11		T63	2		T153	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T236	12		T272	7		T186	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T244	9		T255	5		T184	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	3		T84	9		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	8		T150	13		T163	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T194	1		T43	1		T226	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	1		T251	6		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T29	7		T294	11		T67	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T227	10		T323	14		T104	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T228	12		T291	13		T324	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T227	7		T42	2		T47	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T321	1		T219	9		T179	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T156	12		T157	1		T46	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T228	1		T322	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T296	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	3		T151	9		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T38	1		T30	1		T227	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T89	11		T45	6		T229	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	12		T38	12		T156	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	9		T6	9		T37	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T158	1		T84	13		T86	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	1		T163	15		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T12	10		T27	1		T63	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	4		T27	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	13		T181	1		T51	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T150	8		T152	1		T163	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	4		T30	1		T227	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T37	10		T149	1		T44	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T155	1		T195	7		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	12		T5	12		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	11		T27	1		T150	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	11		T29	1		T150	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1348	1			T1	3		T4	1		T11	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T219	9		T325	4		T285	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T46	1		T206	10		T274	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T228	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T296	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T8	9		T151	7		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T38	3		T227	7		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T89	11		T45	1		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T6	10		T38	11		T152	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	13		T6	8		T37	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T84	9		T247	10		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T151	2		T163	14		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T63	14		T268	14		T258	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	1		T149	12		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	13		T181	12		T51	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T150	6		T152	13		T163	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T227	11		T63	10		T153	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T37	6		T236	12		T272	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T244	9		T253	8		T271	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	3		T84	9		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	8		T150	13		T164	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T29	7		T194	1		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1248	1			T40	1		T24	26		T25	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8