Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T8	3		T27	1		T150	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T5	13		T6	9		T12	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T1	3		T4	1		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T37	14		T163	12		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T156	12		T63	16		T244	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T149	1		T157	1		T257	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	12		T37	10		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	4		T149	1		T157	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	12		T38	1		T150	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T225	1		T158	1		T89	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	12		T29	1		T153	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	1		T227	6		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T8	11		T178	1		T258	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T39	1		T27	1		T150	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T226	1		T245	1		T236	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T227	10		T42	4		T225	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	9		T40	2		T162	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T10	4		T31	9		T227	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T259	7		T170	12		T260	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T30	1		T43	2		T89	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17808	1			T2	14		T8	17		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T8	9		T150	6		T161	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	13		T6	8		T38	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T7	8		T24	26		T25	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T37	15		T163	15		T84	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T63	10		T244	10		T164	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T149	12		T228	7		T46	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T37	6		T160	4		T165	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T194	1		T84	9		T228	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	10		T38	3		T150	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T89	11		T229	12		T50	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	3		T29	7		T153	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T227	7		T152	15		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T258	16		T126	7		T271	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T152	13		T255	10		T265	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T236	12		T176	6		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T227	11		T42	2		T163	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	13		T40	1		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T227	10		T63	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T170	9		T67	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T43	1		T89	13		T14	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T67	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T12	1		T40	3		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T226	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T27	1		T266	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T12	10		T256	11		T186	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	3		T150	7		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	13		T6	9		T156	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T1	3		T4	1		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T38	12		T163	12		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	12		T7	11		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T37	14		T149	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T156	12		T27	1		T63	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	4		T157	14		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T37	10		T153	9		T195	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T149	1		T227	6		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	12		T6	12		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T30	1		T45	6		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	11		T29	1		T84	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	1		T27	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T226	1		T236	11		T176	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T150	12		T86	14		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	9		T40	2		T162	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T10	4		T30	1		T31	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17431	1			T2	14		T8	17		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T186	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	9		T150	6		T268	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	13		T6	8		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T24	26		T25	16		T28	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T38	11		T163	15		T251	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	8		T63	8		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T37	15		T149	12		T84	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T63	2		T244	10		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T194	1		T84	9		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	6		T153	3		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T227	7		T89	11		T229	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	3		T6	10		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T45	1		T228	5		T270	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T29	7		T84	9		T258	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T152	28		T244	9		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T236	12		T176	6		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T159	9		T52	1		T272	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	13		T40	1		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	1		T227	21		T63	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8