Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23053

1

T1

3

T2

14

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3309

1

T3

12

T5

41

T6

39

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20823

1

T2

14

T5

48

T7

19

auto[1]

5539

1

T1

3

T3

12

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	337	1			T156	12		T227	21		T158	1
values[0]	1	1			T258	1		-	-		-	-
values[1]	877	1			T37	29		T156	11		T27	2
values[2]	2538	1			T1	3		T3	12		T4	1
values[3]	697	1			T5	48		T6	22		T7	19
values[4]	465	1			T5	15		T13	4		T150	1
values[5]	690	1			T8	12		T10	5		T38	4
values[6]	674	1			T27	1		T227	21		T157	14
values[7]	700	1			T150	40		T226	1		T158	1
values[8]	684	1			T37	16		T38	23		T149	1
values[9]	896	1			T6	17		T12	10		T40	3
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	667	1			T3	12		T27	2		T162	11
values[1]	2531	1			T1	3		T4	1		T7	19
values[2]	683	1			T5	63		T6	22		T26	1
values[3]	600	1			T13	4		T150	1		T152	14
values[4]	596	1			T8	12		T10	5		T38	4
values[5]	725	1			T27	1		T227	21		T157	14
values[6]	700	1			T38	23		T150	40		T226	1
values[7]	675	1			T37	16		T149	1		T227	13
values[8]	922	1			T6	17		T12	10		T40	3
values[9]	136	1			T156	12		T227	21		T158	1
minimum	18127	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T27	2		T162	11		T84	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	1		T163	16		T226	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1463	1			T1	3		T4	1		T7	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T31	1		T155	1		T194	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	14		T84	10		T267	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	18		T6	11		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	3		T150	1		T159	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T152	14		T195	1		T159	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	10		T39	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T10	2		T38	4		T63	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T27	1		T227	11		T63	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T157	1		T162	3		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T150	7		T247	11		T273	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T38	12		T150	14		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T227	8		T43	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T37	7		T149	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T40	3		T29	8		T42	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	9		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T227	12		T236	13		T99	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T156	1		T158	1		T268	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T2	14		T8	14		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T37	16		T150	1		T41	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T84	9		T244	3		T251	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	11		T163	11		T159	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	821	1			T7	10		T8	10		T232	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T31	8		T51	2		T274	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	8		T84	12		T180	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	23		T6	11		T151	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T159	10		T182	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T195	6		T159	11		T229	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	2		T163	14		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	3		T63	10		T163	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T227	10		T63	4		T164	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T157	13		T89	10		T256	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T150	6		T206	9		T275	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	11		T150	13		T233	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T227	5		T198	2		T268	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T37	9		T63	16		T89	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	2		T44	6		T262	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	8		T12	9		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T227	9		T236	10		T99	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T156	11		T268	13		T276	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	3		T156	10		T13	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T37	13		T150	11		T41	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T227	12		T44	3		T236	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T156	1		T158	1		T86	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T156	1		T27	2		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T37	16		T150	1		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T1	3		T4	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	1		T31	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	14		T7	9		T84	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	14		T6	11		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	3		T150	1		T159	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	4		T152	14		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	10		T39	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	2		T38	4		T63	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T27	1		T227	11		T63	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T157	1		T162	3		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T150	7		T158	1		T247	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T150	14		T226	1		T233	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T227	8		T198	1		T268	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T37	7		T38	12		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T40	3		T29	8		T42	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	9		T12	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T227	9		T44	6		T236	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T156	11		T86	13		T97	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T156	10		T153	8		T84	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T37	13		T150	11		T41	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	824	1			T8	10		T232	28		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	11		T31	8		T159	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	8		T7	10		T84	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	12		T6	11		T151	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T13	1		T159	10		T278	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T5	11		T229	16		T50	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	2		T163	14		T237	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	3		T63	10		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T227	10		T63	4		T164	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T157	13		T163	9		T89	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T150	6		T270	2		T206	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T150	13		T233	8		T210	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T227	5		T198	2		T268	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T37	9		T38	11		T63	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T42	2		T262	2		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	8		T12	9		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T27	2		T162	1		T84	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	12		T163	12		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T1	3		T4	1		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T31	9		T155	1		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	9		T84	13		T267	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	25		T6	12		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	4		T150	1		T159	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T152	1		T195	7		T159	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	3		T39	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	4		T38	1		T63	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	1		T227	11		T63	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T157	14		T162	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T150	7		T247	1		T273	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T38	12		T150	14		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T227	6		T43	1		T198	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T37	10		T149	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T40	2		T29	1		T42	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	9		T12	10		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T227	10		T236	11		T99	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T156	12		T158	1		T268	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17873	1			T2	14		T8	17		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T37	14		T150	12		T41	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T162	10		T84	9		T244	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T163	15		T226	13		T159	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T7	8		T24	26		T25	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T194	1		T43	1		T177	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	13		T84	9		T252	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T5	16		T6	10		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T159	9		T181	16		T182	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T152	13		T159	11		T229	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	9		T163	14		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	1		T38	3		T63	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T227	10		T63	2		T164	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T162	2		T89	11		T272	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T150	6		T247	10		T206	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T38	11		T150	13		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T227	7		T268	14		T182	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	6		T63	14		T89	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T40	1		T29	7		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	8		T149	12		T246	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T227	11		T236	12		T99	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T268	2		T276	10		T279	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T151	2		T280	13		T170	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T37	15		T41	2		T176	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T227	10		T44	9		T236	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T156	12		T158	1		T86	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T156	11		T27	2		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T37	14		T150	12		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T1	3		T4	1		T8	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	12		T31	9		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	9		T7	11		T84	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	13		T6	12		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	4		T150	1		T159	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	12		T152	1		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	3		T39	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	4		T38	1		T63	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T27	1		T227	11		T63	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T157	14		T162	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T150	7		T158	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T150	14		T226	1		T233	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T227	6		T198	3		T268	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T37	10		T38	12		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T40	2		T29	1		T42	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	9		T12	10		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T227	11		T236	12		T46	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T281	9		T97	2		T207	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T153	3		T162	10		T151	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T37	15		T41	2		T163	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T24	26		T25	16		T28	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T43	1		T226	13		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	13		T7	8		T84	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	13		T6	10		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T159	9		T181	16		T126	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T5	3		T152	13		T229	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	9		T163	14		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	1		T38	3		T63	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T227	10		T63	2		T164	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T162	2		T163	4		T89	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T150	6		T247	10		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T150	13		T233	10		T46	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T227	7		T268	14		T272	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T37	6		T38	11		T63	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T40	1		T29	7		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	8		T149	12		T89	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8