Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22915

1

T1

3

T2

14

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3447

1

T5

41

T6

17

T8

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20767

1

T2

14

T5

63

T6

17

auto[1]

5595

1

T1

3

T3

12

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T282	11		-	-		-	-
values[0]	53	1			T162	3		T272	17		T94	12
values[1]	679	1			T6	22		T227	21		T157	14
values[2]	499	1			T6	17		T8	12		T13	4
values[3]	697	1			T10	5		T40	3		T150	12
values[4]	525	1			T5	15		T156	11		T27	1
values[5]	726	1			T38	23		T156	12		T13	2
values[6]	623	1			T27	1		T227	21		T86	14
values[7]	633	1			T8	11		T157	1		T63	19
values[8]	867	1			T5	26		T7	19		T63	7
values[9]	3246	1			T1	3		T3	12		T4	1
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	859	1			T6	39		T13	4		T30	1
values[1]	477	1			T8	12		T26	1		T150	27
values[2]	614	1			T10	5		T163	27		T226	14
values[3]	742	1			T5	15		T38	23		T156	11
values[4]	702	1			T156	12		T13	2		T31	9
values[5]	628	1			T8	11		T27	1		T227	21
values[6]	2679	1			T1	3		T4	1		T11	3
values[7]	830	1			T5	48		T7	19		T27	1
values[8]	752	1			T12	10		T37	16		T39	1
values[9]	262	1			T3	12		T37	29		T38	4
minimum	17817	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	11		T13	3		T227	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	9		T30	1		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T26	1		T150	14		T89	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	10		T152	16		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	2		T226	14		T268	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T163	16		T257	1		T246	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T38	12		T156	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	4		T40	3		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T156	1		T152	14		T89	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	1		T31	1		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T42	1		T247	11		T244	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	1		T27	1		T227	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T1	3		T4	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T150	7		T163	15		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	14		T7	9		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	14		T163	5		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T37	7		T39	1		T227	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T196	7		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T3	1		T38	4		T229	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T37	16		T63	15		T151	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17685	1			T2	14		T8	14		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T283	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	11		T13	1		T227	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	8		T157	13		T84	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T150	13		T89	5		T44	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T8	2		T244	11		T229	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	3		T268	13		T46	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T163	11		T246	9		T160	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T38	11		T156	10		T150	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	11		T195	6		T176	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T156	11		T89	12		T256	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T31	8		T159	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T244	3		T262	2		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	10		T227	10		T63	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	825	1			T232	28		T63	4		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T150	6		T163	14		T180	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	8		T7	10		T151	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	12		T163	9		T237	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T37	9		T227	5		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	9		T268	8		T249	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T3	11		T229	11		T93	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T37	13		T63	16		T219	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	3		T13	2		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T282	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T162	3		T272	9		T94	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T284	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	11		T227	12		T153	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T157	1		T84	10		T45	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	3		T26	1		T150	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	9		T8	10		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T10	2		T150	1		T226	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	3		T152	16		T43	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T156	1		T27	1		T29	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	4		T194	2		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T38	12		T156	1		T152	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	1		T31	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T262	1		T253	9		T264	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	1		T227	11		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T41	4		T154	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T8	1		T157	1		T63	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	9		T63	3		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	14		T150	7		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1679	1			T1	3		T3	1		T4	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T12	1		T37	16		T63	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T282	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T272	8		T94	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T284	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	11		T227	9		T153	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T157	13		T84	9		T45	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	1		T150	13		T44	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T6	8		T8	2		T229	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	3		T150	11		T89	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T163	11		T244	11		T176	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T156	10		T46	4		T182	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T5	11		T246	9		T176	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T38	11		T156	11		T89	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	1		T31	8		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T262	2		T264	2		T234	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T227	10		T86	13		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T41	2		T89	10		T233	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	10		T63	10		T163	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	10		T63	4		T84	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	12		T150	6		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T3	11		T5	8		T37	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T12	9		T37	13		T63	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	12		T13	4		T227	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T6	9		T30	1		T157	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	1		T150	14		T89	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	3		T152	1		T43	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	4		T226	1		T268	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T163	12		T257	1		T246	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T38	12		T156	11		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	12		T40	2		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T156	12		T152	1		T89	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	2		T31	9		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	1		T247	1		T244	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	11		T27	1		T227	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1147	1			T1	3		T4	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T150	7		T163	15		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	9		T7	11		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	13		T163	10		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T37	10		T39	1		T227	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	10		T196	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T3	12		T38	1		T229	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T37	14		T63	17		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T2	14		T8	17		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T283	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	10		T227	11		T153	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	8		T84	9		T45	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T150	13		T89	2		T160	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T8	9		T152	15		T43	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	1		T226	13		T268	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T163	15		T246	14		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	11		T29	7		T177	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	3		T40	1		T194	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T152	13		T89	13		T184	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T159	29		T164	14		T165	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T247	10		T244	10		T233	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T227	10		T63	8		T161	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T24	26		T25	16		T28	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T150	6		T163	14		T84	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	13		T7	8		T149	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	13		T163	4		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	6		T227	7		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T196	6		T268	14		T285	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T38	3		T229	11		T93	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T37	15		T63	14		T151	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T282	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T162	1		T272	9		T94	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T284	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	12		T227	10		T153	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T157	14		T84	10		T45	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	4		T26	1		T150	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	9		T8	3		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	4		T150	12		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	2		T152	1		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T156	11		T27	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	12		T194	1		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T38	12		T156	12		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	2		T31	9		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T262	3		T253	1		T264	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T27	1		T227	11		T86	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T41	4		T154	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	11		T157	1		T63	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	11		T63	5		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	13		T150	7		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T1	3		T3	12		T4	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T12	10		T37	14		T63	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T162	2		T272	8		T94	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T284	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	10		T227	11		T153	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T84	9		T45	1		T251	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T150	13		T160	4		T268	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T6	8		T8	9		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	1		T226	13		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	1		T152	15		T43	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	7		T46	1		T182	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	3		T194	1		T246	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T38	11		T152	13		T89	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T159	20		T164	14		T228	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T253	8		T264	9		T170	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T227	10		T159	9		T161	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T41	2		T89	11		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T63	8		T163	14		T224	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	8		T63	2		T84	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	13		T150	6		T84	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T5	13		T37	6		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T37	15		T63	14		T151	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8