Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22927

1

T1

3

T2

14

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3435

1

T3

12

T5

26

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20772

1

T2

14

T5

63

T6

17

auto[1]

5590

1

T1

3

T3

12

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	51	1			T10	5		T150	27		T261	8
values[0]	21	1			T227	21		-	-		-	-
values[1]	845	1			T5	26		T6	17		T37	16
values[2]	577	1			T38	4		T153	12		T162	11
values[3]	740	1			T12	10		T227	21		T157	14
values[4]	629	1			T38	23		T156	12		T26	1
values[5]	550	1			T39	1		T63	19		T150	1
values[6]	637	1			T6	22		T8	23		T30	1
values[7]	685	1			T5	37		T37	29		T157	1
values[8]	2807	1			T1	3		T3	12		T4	1
values[9]	1017	1			T7	19		T40	3		T13	6
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	881	1			T6	17		T37	16		T149	13
values[1]	807	1			T5	26		T12	10		T38	4
values[2]	663	1			T156	12		T29	8		T227	21
values[3]	536	1			T38	23		T39	1		T26	1
values[4]	609	1			T27	1		T227	13		T63	19
values[5]	757	1			T5	22		T6	22		T8	23
values[6]	2652	1			T1	3		T3	12		T4	1
values[7]	774	1			T5	15		T13	6		T63	31
values[8]	756	1			T7	19		T10	5		T40	3
values[9]	114	1			T150	27		T225	1		T44	9
minimum	17813	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	9		T149	13		T162	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T37	7		T227	12		T89	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T42	1		T163	16		T247	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T5	14		T12	1		T38	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T227	11		T150	7		T89	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T156	1		T29	8		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	12		T39	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T26	1		T27	1		T226	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T227	8		T43	3		T277	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T27	1		T63	9		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	14		T6	11		T8	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T194	2		T257	1		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T1	3		T4	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T30	1		T152	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	4		T152	14		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	4		T63	15		T151	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T10	2		T63	3		T151	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	9		T40	3		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T165	3		T286	6		T287	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T150	14		T225	1		T44	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T288	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	8		T176	7		T268	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T37	9		T227	9		T89	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T163	11		T289	8		T124	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	12		T12	9		T157	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T227	10		T150	6		T89	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T156	11		T237	1		T89	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T38	11		T84	12		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T262	2		T46	4		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T227	5		T45	3		T180	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T63	10		T41	2		T163	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	8		T6	11		T8	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T256	9		T290	11		T278	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	836	1			T37	13		T156	10		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	11		T195	6		T233	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	11		T86	13		T244	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	2		T63	16		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	3		T63	4		T151	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	10		T163	14		T180	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T286	2		T287	3		T291	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T150	13		T44	6		T119	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T288	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T10	2		T261	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T150	14		T282	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T227	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	9		T149	13		T162	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T5	14		T37	7		T89	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T163	16		T247	11		T245	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	4		T153	4		T162	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T227	11		T151	3		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	1		T157	1		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T38	12		T27	1		T150	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T156	1		T26	1		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T39	1		T43	3		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T63	9		T150	1		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	11		T8	11		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T30	1		T194	2		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	18		T37	16		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T152	16		T195	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T1	3		T4	1		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T226	1		T84	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T63	3		T151	8		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T7	9		T40	3		T13	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T10	3		T261	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T150	13		T282	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T227	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	8		T268	13		T46	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T5	12		T37	9		T89	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T163	11		T176	7		T124	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T153	8		T42	2		T229	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T227	10		T89	5		T159	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	9		T157	13		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T38	11		T150	6		T84	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T156	11		T262	2		T210	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T45	3		T251	10		T184	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T63	10		T41	2		T163	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	11		T8	12		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T244	11		T268	13		T182	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	19		T37	13		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T195	6		T182	31		T249	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T156	10		T232	28		T192	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	11		T84	9		T233	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T63	4		T151	8		T176	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	10		T13	2		T63	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	9		T149	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T37	10		T227	10		T89	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T42	1		T163	12		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	13		T12	10		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T227	11		T150	7		T89	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T156	12		T29	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T38	12		T39	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T26	1		T27	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T227	6		T43	2		T277	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T27	1		T63	11		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	9		T6	12		T8	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T194	1		T257	1		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1153	1			T1	3		T4	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	12		T30	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	12		T152	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	6		T63	17		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	4		T63	5		T151	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	11		T40	2		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T165	1		T286	7		T287	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T150	14		T225	1		T44	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T288	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	8		T149	12		T162	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T37	6		T227	11		T89	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T163	15		T247	10		T289	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	13		T38	3		T153	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T227	10		T150	6		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T29	7		T89	11		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T38	11		T151	2		T84	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T226	13		T228	12		T46	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T227	7		T43	1		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T63	8		T41	2		T163	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	13		T6	10		T8	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T194	1		T177	3		T258	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T37	15		T24	26		T25	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T152	15		T84	2		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	3		T152	13		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T63	14		T151	3		T84	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	1		T63	2		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	8		T40	1		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T165	2		T286	1		T287	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T150	13		T213	9		T242	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T10	4		T261	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T150	14		T282	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T227	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	9		T149	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T5	13		T37	10		T89	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T163	12		T247	1		T245	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	1		T153	9		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T227	11		T151	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	10		T157	14		T237	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T38	12		T27	1		T150	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T156	12		T26	1		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	1		T43	2		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T63	11		T150	1		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	12		T8	14		T31	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T30	1		T194	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	21		T37	14		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T152	1		T195	7		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T1	3		T4	1		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	12		T226	1		T84	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T63	5		T151	9		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T7	11		T40	2		T13	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T10	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T150	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T227	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	8		T149	12		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	13		T37	6		T89	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T163	15		T247	10		T176	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T38	3		T153	3		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T227	10		T151	2		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T89	11		T236	12		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T38	11		T150	6		T84	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	7		T226	13		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T43	1		T45	1		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T63	8		T41	2		T163	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	10		T8	9		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T194	1		T244	9		T268	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	16		T37	15		T159	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T152	15		T84	2		T258	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T24	26		T25	16		T28	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T84	9		T233	10		T160	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T63	2		T151	7		T252	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	8		T40	1		T63	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8