Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23073

1

T1

3

T2

14

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3289

1

T3

12

T5

41

T6

39

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20846

1

T2

14

T5

48

T6

17

auto[1]

5516

1

T1

3

T3

12

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T236	23		T109	1		T298	1
values[0]	103	1			T37	29		T156	11		T258	1
values[1]	773	1			T27	2		T30	1		T150	12
values[2]	2551	1			T1	3		T3	12		T4	1
values[3]	648	1			T5	48		T6	22		T7	19
values[4]	428	1			T5	15		T38	4		T13	4
values[5]	803	1			T8	12		T10	5		T39	1
values[6]	657	1			T27	1		T227	21		T63	7
values[7]	680	1			T149	1		T150	40		T226	1
values[8]	716	1			T37	16		T38	23		T227	13
values[9]	1175	1			T6	17		T12	10		T156	12
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	994	1			T3	12		T37	29		T156	11
values[1]	2544	1			T1	3		T4	1		T7	19
values[2]	605	1			T5	37		T26	1		T151	16
values[3]	622	1			T5	26		T6	22		T13	4
values[4]	635	1			T10	5		T38	4		T39	1
values[5]	684	1			T8	12		T27	1		T227	21
values[6]	719	1			T38	23		T150	13		T226	1
values[7]	683	1			T37	16		T149	1		T227	13
values[8]	906	1			T6	17		T12	10		T156	12
values[9]	148	1			T227	21		T158	1		T236	23
minimum	17822	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T156	1		T27	2		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T37	16		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T1	3		T4	1		T7	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T31	1		T155	1		T194	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	14		T84	10		T267	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T5	4		T26	1		T151	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	3		T150	1		T159	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	14		T6	11		T159	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T39	1		T30	1		T163	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	2		T38	4		T63	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	10		T27	1		T227	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T157	1		T162	3		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T150	7		T273	1		T206	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T38	12		T226	1		T247	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T227	8		T43	1		T262	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T37	7		T149	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T40	3		T29	8		T42	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	9		T12	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T227	12		T236	13		T264	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T158	1		T268	3		T181	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T248	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T156	10		T244	3		T251	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	11		T37	13		T150	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	824	1			T7	10		T8	10		T232	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T31	8		T51	2		T274	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	8		T84	12		T180	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T5	11		T151	8		T251	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T159	10		T182	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	12		T6	11		T159	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T163	14		T237	1		T45	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	3		T63	10		T163	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	2		T227	10		T63	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T157	13		T89	10		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T150	6		T206	9		T275	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T38	11		T210	10		T46	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T227	5		T262	2		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T37	9		T63	16		T150	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T42	2		T44	6		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	8		T12	9		T156	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T227	9		T236	10		T264	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T268	13		T67	1		T279	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T248	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T236	13		T109	1		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T156	1		T258	1		T271	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T37	16		T285	11		T15	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T27	2		T30	1		T153	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T150	1		T41	4		T163	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T1	3		T4	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	1		T31	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	14		T7	9		T151	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	14		T6	11		T151	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	3		T150	1		T159	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T5	4		T38	4		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T8	10		T39	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T10	2		T157	1		T63	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T27	1		T227	11		T63	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T162	3		T154	1		T163	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T150	7		T228	8		T270	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T149	1		T150	14		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T227	8		T198	1		T268	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T37	7		T38	12		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T40	3		T29	8		T227	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T6	9		T12	1		T156	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T236	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T156	10		T299	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T37	13		T285	10		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T153	8		T84	9		T244	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T150	11		T41	2		T163	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	819	1			T8	10		T232	28		T192	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	11		T31	8		T159	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	8		T7	10		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	12		T6	11		T151	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	1		T159	10		T124	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T5	11		T229	16		T50	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	2		T163	14		T237	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	3		T157	13		T63	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T227	10		T63	4		T164	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T163	9		T89	10		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T150	6		T270	2		T206	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T150	13		T233	8		T210	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T227	5		T198	2		T268	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T37	9		T38	11		T63	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T227	9		T42	2		T44	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T6	8		T12	9		T156	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T156	11		T27	2		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	12		T37	14		T150	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T1	3		T4	1		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T31	9		T155	1		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	9		T84	13		T267	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	12		T26	1		T151	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	4		T150	1		T159	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	13		T6	12		T159	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T39	1		T30	1		T163	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	4		T38	1		T63	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	3		T27	1		T227	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T157	14		T162	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T150	7		T273	1		T206	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T38	12		T226	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T227	6		T43	1		T262	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T37	10		T149	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T40	2		T29	1		T42	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T6	9		T12	10		T156	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T227	10		T236	11		T264	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T158	1		T268	14		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T248	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T162	10		T151	2		T244	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T37	15		T41	2		T163	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1142	1			T7	8		T24	26		T25	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T194	1		T43	1		T177	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	13		T84	9		T124	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T5	3		T151	7		T196	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T159	9		T252	4		T181	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	13		T6	10		T159	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T163	14		T45	1		T164	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	1		T38	3		T63	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	9		T227	10		T63	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T162	2		T89	11		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T150	6		T206	10		T275	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T38	11		T247	10		T46	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T227	7		T268	14		T182	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T37	6		T63	14		T150	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T40	1		T29	7		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	8		T149	12		T246	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T227	11		T236	12		T264	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T268	2		T181	12		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T248	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T236	11		T109	1		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T156	11		T258	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T37	14		T285	11		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T27	2		T30	1		T153	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T150	12		T41	4		T163	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T1	3		T4	1		T8	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	12		T31	9		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	9		T7	11		T151	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	13		T6	12		T151	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	4		T150	1		T159	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T5	12		T38	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	3		T39	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	4		T157	14		T63	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T27	1		T227	11		T63	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T162	1		T154	1		T163	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T150	7		T228	1		T270	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T149	1		T150	14		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T227	6		T198	3		T268	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T37	10		T38	12		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T40	2		T29	1		T227	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T6	9		T12	10		T156	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T236	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T271	14		T299	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T37	15		T285	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T153	3		T162	10		T151	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T41	2		T163	15		T176	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1127	1			T24	26		T25	16		T28	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T43	1		T226	13		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	13		T7	8		T151	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	13		T6	10		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T159	9		T124	7		T126	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T5	3		T38	3		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	9		T163	14		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T63	8		T152	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T227	10		T63	2		T164	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T162	2		T163	4		T89	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T150	6		T228	7		T270	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	13		T247	10		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T227	7		T268	14		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T37	6		T38	11		T63	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T40	1		T29	7		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	8		T149	12		T89	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8