Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23122

1

T1

3

T2

14

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3240

1

T6

17

T7

19

T8

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20662

1

T2

14

T3

12

T5

63

auto[1]

5700

1

T1

3

T4

1

T6

39

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	559	1			T5	22		T12	1		T40	3
values[0]	12	1			T27	1		T256	11		-	-
values[1]	922	1			T5	26		T6	17		T8	12
values[2]	2676	1			T1	3		T4	1		T11	3
values[3]	742	1			T3	12		T7	19		T37	29
values[4]	655	1			T156	12		T13	4		T27	1
values[5]	664	1			T37	16		T38	4		T149	1
values[6]	656	1			T5	15		T6	22		T29	8
values[7]	568	1			T8	11		T39	1		T27	1
values[8]	715	1			T150	12		T226	1		T86	14
values[9]	762	1			T10	5		T40	3		T30	1
minimum	17431	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	927	1			T5	26		T6	17		T8	12
values[1]	2792	1			T1	3		T4	1		T7	19
values[2]	669	1			T3	12		T156	12		T149	13
values[3]	595	1			T37	16		T13	4		T27	1
values[4]	724	1			T6	22		T38	4		T149	1
values[5]	686	1			T5	15		T39	1		T29	8
values[6]	454	1			T8	11		T27	1		T150	12
values[7]	726	1			T227	21		T42	6		T225	1
values[8]	743	1			T5	22		T10	5		T40	3
values[9]	63	1			T30	1		T43	3		T89	26
minimum	17983	1			T2	14		T8	17		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T5	14		T13	1		T151	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	9		T8	10		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T1	3		T4	1		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	9		T37	16		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T156	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T149	13		T63	9		T84	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T37	7		T27	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	3		T157	1		T194	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	11		T38	4		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T149	1		T227	8		T150	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	4		T39	1		T29	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	1		T153	4		T152	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	1		T163	15		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T27	1		T150	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T225	1		T226	1		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T227	12		T42	4		T236	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	14		T10	2		T227	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	3		T31	1		T63	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T89	14		T264	10		T300	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T30	1		T43	3		T197	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17711	1			T2	14		T8	14		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T196	7		T164	15		T255	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	12		T13	1		T161	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	8		T8	2		T12	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	865	1			T232	28		T192	20		T89	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	10		T37	13		T159	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	11		T156	11		T63	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T63	10		T176	1		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	9		T180	9		T124	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	1		T157	13		T84	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	11		T229	11		T219	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T227	5		T150	13		T195	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	11		T84	9		T159	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T153	8		T262	2		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T8	10		T163	14		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T150	11		T86	13		T244	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T159	10		T176	9		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T227	9		T42	2		T236	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	8		T10	3		T227	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T31	8		T63	16		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T89	12		T264	2		T14	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	3		T13	2		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T164	16		T183	5		T256	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	415	1			T5	14		T12	1		T40	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T41	4		T43	3		T176	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T27	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T256	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T5	14		T13	1		T151	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	9		T8	10		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T1	3		T4	1		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T38	12		T43	1		T163	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	1		T26	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	9		T37	16		T149	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T156	1		T27	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	3		T157	1		T194	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T37	7		T38	4		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T149	1		T227	8		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	4		T6	11		T29	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T30	1		T150	14		T153	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	1		T39	1		T163	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T27	1		T42	1		T152	30
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T226	1		T267	1		T159	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T150	1		T86	1		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	2		T227	11		T162	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	3		T30	1		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17312	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T5	8		T264	2		T278	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T41	2		T176	7		T224	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T256	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	12		T13	1		T268	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	8		T8	2		T12	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	835	1			T232	28		T192	20		T269	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	11		T163	11		T180	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	11		T63	4		T89	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	10		T37	13		T63	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T156	11		T244	3		T180	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	1		T157	13		T84	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	9		T229	11		T47	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T227	5		T195	6		T89	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	11		T6	11		T159	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T150	13		T153	8		T45	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	10		T163	14		T84	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T244	11		T262	2		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T159	10		T176	9		T179	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T150	11		T86	13		T236	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	3		T227	10		T89	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T31	8		T227	9		T63	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	13		T13	2		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T6	9		T8	3		T12	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T1	3		T4	1		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	11		T37	14		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	12		T156	12		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T149	1		T63	11		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T37	10		T27	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	4		T157	14		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	12		T38	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T149	1		T227	6		T150	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	12		T39	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	1		T153	9		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	11		T163	15		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T27	1		T150	12		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T225	1		T226	1		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T227	10		T42	4		T236	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	9		T10	4		T227	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T40	2		T31	9		T63	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T89	13		T264	3		T300	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T30	1		T43	2		T197	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17857	1			T2	14		T8	17		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T196	1		T164	17		T255	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	13		T151	2		T161	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	8		T8	9		T38	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T24	26		T25	16		T28	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	8		T37	15		T159	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T63	2		T244	10		T165	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T149	12		T63	8		T84	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T37	6		T160	4		T228	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T194	1		T84	9		T251	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	10		T38	3		T247	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T227	7		T150	13		T89	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	3		T29	7		T84	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T153	3		T152	15		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T163	14		T258	8		T126	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T152	13		T244	9		T258	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T159	9		T176	6		T181	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T227	11		T42	2		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	13		T10	1		T227	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T40	1		T63	14		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T89	13		T264	9		T14	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T43	1		T241	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T186	15		T67	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T196	6		T164	14		T255	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	408	1			T5	9		T12	1		T40	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T41	4		T43	2		T176	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T27	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T256	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	13		T13	2		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T6	9		T8	3		T12	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T1	3		T4	1		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	12		T43	1		T163	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	12		T26	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	11		T37	14		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T156	12		T27	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	4		T157	14		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T37	10		T38	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T149	1		T227	6		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	12		T6	12		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T30	1		T150	14		T153	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	11		T39	1		T163	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T27	1		T42	1		T152	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T226	1		T267	1		T159	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T150	12		T86	14		T236	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	4		T227	11		T162	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T40	2		T30	1		T31	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17431	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T5	13		T264	9		T278	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T41	2		T43	1		T176	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	13		T151	2		T268	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	8		T8	9		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T24	26		T25	16		T28	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T38	11		T163	15		T107	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T63	2		T89	2		T268	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	8		T37	15		T149	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T244	10		T160	4		T228	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T194	1		T84	9		T251	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T37	6		T38	3		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T227	7		T89	11		T229	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	3		T6	10		T29	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T150	13		T153	3		T45	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T163	14		T84	9		T258	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T152	28		T244	9		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T159	9		T176	6		T181	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T236	12		T160	11		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	1		T227	10		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T40	1		T227	11		T63	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8