Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26362

1

T1

3

T2

14

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22925

1

T1

3

T2

14

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3437

1

T3

12

T6

22

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20555

1

T2

14

T6

17

T7

19

auto[1]

5807

1

T1

3

T3

12

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22639

1

T1

3

T2

14

T3

1

auto[1]

3723

1

T3

11

T5

31

T6

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	200	1			T157	14		T162	3		T155	1
values[0]	51	1			T6	22		T243	9		T200	1
values[1]	814	1			T5	41		T12	10		T13	4
values[2]	568	1			T3	12		T30	2		T149	1
values[3]	616	1			T7	19		T8	23		T156	11
values[4]	584	1			T37	29		T38	4		T156	12
values[5]	2945	1			T1	3		T4	1		T6	17
values[6]	543	1			T37	16		T27	1		T149	13
values[7]	668	1			T31	9		T154	1		T42	7
values[8]	505	1			T13	2		T151	3		T225	1
values[9]	1065	1			T5	22		T10	5		T38	23
minimum	17803	1			T2	14		T8	17		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	709	1			T3	12		T5	15		T12	10
values[1]	637	1			T7	19		T8	11		T30	1
values[2]	449	1			T8	12		T38	4		T156	11
values[3]	2914	1			T1	3		T4	1		T6	17
values[4]	709	1			T37	16		T40	3		T26	1
values[5]	541	1			T27	1		T31	9		T149	13
values[6]	760	1			T154	1		T42	6		T226	15
values[7]	409	1			T39	1		T13	2		T151	3
values[8]	944	1			T5	22		T10	5		T38	23
values[9]	173	1			T157	14		T162	3		T229	29
minimum	18117	1			T2	14		T5	26		T6	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

3940

1

T5

29

T6

18

T7

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	4		T30	1		T152	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T12	1		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T150	1		T84	3		T228	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	9		T8	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	10		T63	9		T153	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T38	4		T156	1		T29	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T1	3		T4	1		T6	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T37	16		T156	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	7		T40	3		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T158	1		T45	4		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T31	1		T149	13		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T27	1		T194	2		T86	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T42	4		T226	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T154	1		T226	14		T89	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	1		T151	3		T176	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T39	1		T225	1		T247	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	14		T10	2		T63	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T38	12		T227	11		T150	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T157	1		T238	1		T93	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T162	3		T229	13		T268	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	14		T5	14		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T6	11		T27	1		T176	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	11		T244	3		T210	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	11		T12	9		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T150	11		T46	1		T224	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	10		T8	10		T227	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	2		T63	10		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T156	10		T198	2		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T6	8		T232	28		T192	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T37	13		T156	11		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T37	9		T150	13		T151	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T45	3		T251	6		T179	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T31	8		T235	12		T301	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T86	13		T233	8		T148	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T42	2		T44	6		T236	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T89	12		T176	1		T164	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T13	1		T176	7		T302	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T159	11		T229	11		T180	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	8		T10	3		T63	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T38	11		T227	10		T150	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T157	13		T238	11		T93	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T229	16		T268	13		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	12		T8	3		T13	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T6	11		T176	9		T161	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T157	1		T155	1		T237	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T162	3		T206	11		T230	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T6	11		T243	9		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	18		T227	12		T152	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T13	3		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T30	1		T244	11		T228	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T30	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	10		T63	9		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	9		T8	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T27	1		T157	1		T84	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T37	16		T38	4		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T1	3		T4	1		T6	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T163	16		T158	1		T159	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T37	7		T149	13		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T27	1		T194	2		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T31	1		T42	5		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T154	1		T89	14		T164	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	1		T151	3		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T225	1		T226	14		T247	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	14		T10	2		T63	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T38	12		T39	1		T227	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	14		T8	14		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T157	13		T237	1		T96	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T206	9		T290	11		T303	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T6	11		T248	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	23		T227	9		T210	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	9		T13	1		T244	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T244	3		T46	1		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	11		T227	5		T63	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	2		T63	10		T150	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	10		T8	10		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T84	9		T246	9		T249	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	13		T156	11		T198	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T6	8		T232	28		T150	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T163	11		T159	10		T45	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T37	9		T159	10		T235	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T86	13		T233	8		T251	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T31	8		T42	2		T236	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T89	12		T164	16		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T13	1		T44	6		T302	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T159	11		T176	1		T180	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	8		T10	3		T63	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T38	11		T227	10		T150	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T13	2		T43	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	12		T30	1		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	12		T12	10		T13	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T150	12		T84	1		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	11		T8	11		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	3		T63	11		T153	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T38	1		T156	11		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T1	3		T4	1		T6	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T37	14		T156	12		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T37	10		T40	2		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T158	1		T45	6		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T31	9		T149	1		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T27	1		T194	1		T86	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	4		T226	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T154	1		T226	1		T89	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T13	2		T151	1		T176	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T39	1		T225	1		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	9		T10	4		T63	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T38	12		T227	11		T150	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T157	14		T238	12		T93	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T162	1		T229	17		T268	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17898	1			T2	14		T5	13		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T6	12		T27	1		T176	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	3		T152	15		T244	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T63	2		T244	9		T251	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T84	2		T228	5		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	8		T227	7		T163	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T8	9		T63	8		T153	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T38	3		T29	7		T152	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T6	8		T24	26		T25	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T37	15		T163	15		T196	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	6		T40	1		T150	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	1		T228	12		T251	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T149	12		T255	5		T271	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T194	1		T233	10		T252	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T42	2		T236	12		T258	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T226	13		T89	13		T164	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T151	2		T176	10		T186	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T247	10		T159	11		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	13		T10	1		T63	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T38	11		T227	10		T150	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T93	3		T304	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T162	2		T229	12		T268	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T5	13		T227	11		T46	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T6	10		T176	6		T161	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T157	14		T155	1		T237	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T162	1		T206	10		T230	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T6	12		T243	1		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	25		T227	10		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	10		T13	4		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T30	1		T244	4		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	12		T30	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	3		T63	11		T150	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	11		T8	11		T156	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T27	1		T157	1		T84	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T37	14		T38	1		T156	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T1	3		T4	1		T6	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T163	12		T158	1		T159	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T37	10		T149	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T27	1		T194	1		T86	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T31	9		T42	5		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T154	1		T89	13		T164	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	2		T151	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T225	1		T226	1		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	9		T10	4		T63	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T38	12		T39	1		T227	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17803	1			T2	14		T8	17		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T96	3		T187	8		T304	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T162	2		T206	10		T230	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T6	10		T243	8		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	16		T227	11		T152	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T244	9		T176	6		T161	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T244	10		T228	5		T46	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T227	7		T63	2		T163	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	9		T63	8		T153	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	8		T29	7		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T84	9		T246	14		T160	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T37	15		T38	3		T196	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T6	8		T40	1		T24	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T163	15		T159	9		T45	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T37	6		T149	12		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T194	1		T233	10		T251	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T42	2		T236	12		T258	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T89	13		T164	14		T252	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T151	2		T186	11		T254	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T226	13		T247	10		T159	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	13		T10	1		T63	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T38	11		T227	10		T150	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22422

1

T1

3

T2

14

T3

12

auto[1]

auto[0]

3940

1

T5

29

T6

18

T7

8