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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.34


Total test records in report: 920
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T793 /workspace/coverage/default/35.adc_ctrl_smoke.533713056 Jun 24 05:58:14 PM PDT 24 Jun 24 05:58:18 PM PDT 24 6049816324 ps
T794 /workspace/coverage/default/0.adc_ctrl_poweron_counter.1616352748 Jun 24 05:55:09 PM PDT 24 Jun 24 05:55:13 PM PDT 24 4170636911 ps
T320 /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1555661363 Jun 24 05:55:40 PM PDT 24 Jun 24 06:08:23 PM PDT 24 625018335179 ps
T795 /workspace/coverage/default/34.adc_ctrl_smoke.3609634898 Jun 24 05:58:05 PM PDT 24 Jun 24 05:58:10 PM PDT 24 5766655907 ps
T796 /workspace/coverage/default/39.adc_ctrl_filters_wakeup.491149256 Jun 24 05:58:57 PM PDT 24 Jun 24 06:12:02 PM PDT 24 362645093534 ps
T68 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.404138136 Jun 24 05:54:11 PM PDT 24 Jun 24 05:54:16 PM PDT 24 501908996 ps
T62 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3575267168 Jun 24 05:54:06 PM PDT 24 Jun 24 05:54:09 PM PDT 24 566182423 ps
T797 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3048928813 Jun 24 05:54:27 PM PDT 24 Jun 24 05:54:31 PM PDT 24 505266138 ps
T64 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2734376812 Jun 24 05:54:03 PM PDT 24 Jun 24 05:54:09 PM PDT 24 11048958000 ps
T73 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2343269145 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:06 PM PDT 24 809653579 ps
T798 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1641663580 Jun 24 05:54:25 PM PDT 24 Jun 24 05:54:28 PM PDT 24 362382042 ps
T78 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.713482115 Jun 24 05:54:08 PM PDT 24 Jun 24 05:54:11 PM PDT 24 494959010 ps
T799 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.711415781 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:26 PM PDT 24 396527950 ps
T59 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3340702391 Jun 24 05:54:04 PM PDT 24 Jun 24 05:54:19 PM PDT 24 4459826098 ps
T60 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4223119020 Jun 24 05:53:53 PM PDT 24 Jun 24 05:54:06 PM PDT 24 16366939732 ps
T800 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1685733589 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:25 PM PDT 24 414385514 ps
T140 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.532687491 Jun 24 05:54:03 PM PDT 24 Jun 24 05:54:06 PM PDT 24 451224846 ps
T129 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3920692163 Jun 24 05:53:54 PM PDT 24 Jun 24 05:53:57 PM PDT 24 400172062 ps
T141 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4266523066 Jun 24 05:54:03 PM PDT 24 Jun 24 05:54:11 PM PDT 24 2441405731 ps
T130 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1902878881 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:15 PM PDT 24 580432159 ps
T801 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.982617046 Jun 24 05:54:25 PM PDT 24 Jun 24 05:54:28 PM PDT 24 334746165 ps
T802 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4151526624 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:25 PM PDT 24 349336192 ps
T803 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1176491477 Jun 24 05:54:22 PM PDT 24 Jun 24 05:54:25 PM PDT 24 493891259 ps
T61 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2565912094 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:29 PM PDT 24 26873578308 ps
T804 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2971409299 Jun 24 05:54:25 PM PDT 24 Jun 24 05:54:28 PM PDT 24 529813483 ps
T142 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1698848463 Jun 24 05:54:11 PM PDT 24 Jun 24 05:54:33 PM PDT 24 5355391178 ps
T65 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1552707752 Jun 24 05:54:10 PM PDT 24 Jun 24 05:54:22 PM PDT 24 4593309767 ps
T805 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.589197321 Jun 24 05:54:09 PM PDT 24 Jun 24 05:54:12 PM PDT 24 490927532 ps
T74 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1827575652 Jun 24 05:54:06 PM PDT 24 Jun 24 05:54:09 PM PDT 24 1227801129 ps
T75 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.861557120 Jun 24 05:54:20 PM PDT 24 Jun 24 05:54:22 PM PDT 24 699932947 ps
T806 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4054705704 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:05 PM PDT 24 568211626 ps
T143 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2666786820 Jun 24 05:53:56 PM PDT 24 Jun 24 05:54:00 PM PDT 24 2025720737 ps
T807 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4240439696 Jun 24 05:54:26 PM PDT 24 Jun 24 05:54:30 PM PDT 24 323781439 ps
T77 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.581632105 Jun 24 05:54:15 PM PDT 24 Jun 24 05:54:20 PM PDT 24 917481066 ps
T808 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2148636406 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:27 PM PDT 24 302806450 ps
T809 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.293724424 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:15 PM PDT 24 568496601 ps
T810 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.286133653 Jun 24 05:54:25 PM PDT 24 Jun 24 05:54:28 PM PDT 24 474741887 ps
T66 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3597177378 Jun 24 05:53:55 PM PDT 24 Jun 24 05:54:01 PM PDT 24 4591843085 ps
T811 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2610551412 Jun 24 05:53:58 PM PDT 24 Jun 24 05:54:01 PM PDT 24 950275743 ps
T131 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3221192503 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:28 PM PDT 24 11207197514 ps
T110 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1816711099 Jun 24 05:54:22 PM PDT 24 Jun 24 05:54:25 PM PDT 24 556923711 ps
T812 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.715439294 Jun 24 05:54:17 PM PDT 24 Jun 24 05:54:20 PM PDT 24 388126307 ps
T69 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2198037093 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:19 PM PDT 24 8713404194 ps
T813 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2230958200 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:16 PM PDT 24 367555990 ps
T144 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4239106165 Jun 24 05:53:52 PM PDT 24 Jun 24 05:53:59 PM PDT 24 2694526628 ps
T145 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.928328243 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:07 PM PDT 24 1957058495 ps
T132 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.651017941 Jun 24 05:53:57 PM PDT 24 Jun 24 05:54:00 PM PDT 24 1095023693 ps
T111 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1670265346 Jun 24 05:54:00 PM PDT 24 Jun 24 05:54:02 PM PDT 24 613733835 ps
T146 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1001966730 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:23 PM PDT 24 2310490497 ps
T814 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1084839718 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:07 PM PDT 24 1127152477 ps
T112 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2016943279 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:07 PM PDT 24 411222195 ps
T815 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2380086659 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:05 PM PDT 24 408398459 ps
T329 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3116240628 Jun 24 05:54:21 PM PDT 24 Jun 24 05:54:34 PM PDT 24 8482568888 ps
T816 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3745332913 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:16 PM PDT 24 521468513 ps
T817 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1304568273 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:18 PM PDT 24 542372565 ps
T818 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1337180207 Jun 24 05:54:11 PM PDT 24 Jun 24 05:54:16 PM PDT 24 5562054617 ps
T819 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2261193462 Jun 24 05:54:00 PM PDT 24 Jun 24 05:54:03 PM PDT 24 413953794 ps
T820 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2024143559 Jun 24 05:54:15 PM PDT 24 Jun 24 05:54:20 PM PDT 24 568144180 ps
T821 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1419458324 Jun 24 05:54:10 PM PDT 24 Jun 24 05:54:24 PM PDT 24 5622311846 ps
T326 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2454529708 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:10 PM PDT 24 4221046029 ps
T822 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.762954439 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:26 PM PDT 24 519656007 ps
T823 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.959846981 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:05 PM PDT 24 1420115973 ps
T133 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.616156605 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:05 PM PDT 24 355678211 ps
T824 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3421653790 Jun 24 05:54:11 PM PDT 24 Jun 24 05:54:14 PM PDT 24 472083686 ps
T825 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1209524586 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:15 PM PDT 24 452842928 ps
T826 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.75357412 Jun 24 05:54:26 PM PDT 24 Jun 24 05:54:29 PM PDT 24 358656870 ps
T827 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2313165724 Jun 24 05:54:10 PM PDT 24 Jun 24 05:54:14 PM PDT 24 552831641 ps
T828 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1305766740 Jun 24 05:54:07 PM PDT 24 Jun 24 05:54:20 PM PDT 24 4393093016 ps
T829 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.987752540 Jun 24 05:54:15 PM PDT 24 Jun 24 05:54:18 PM PDT 24 391701038 ps
T830 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3169331051 Jun 24 05:54:06 PM PDT 24 Jun 24 05:54:10 PM PDT 24 5171600604 ps
T831 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1413019405 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:07 PM PDT 24 2572602559 ps
T832 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1276991960 Jun 24 05:54:11 PM PDT 24 Jun 24 05:54:21 PM PDT 24 4729297854 ps
T833 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1042244244 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:25 PM PDT 24 595391524 ps
T834 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3413024677 Jun 24 05:54:14 PM PDT 24 Jun 24 05:54:17 PM PDT 24 432682914 ps
T835 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2508951000 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:26 PM PDT 24 511097539 ps
T134 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3889136380 Jun 24 05:54:00 PM PDT 24 Jun 24 05:54:03 PM PDT 24 947875592 ps
T135 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.309256311 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:07 PM PDT 24 1112471014 ps
T836 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.638999398 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:05 PM PDT 24 540064257 ps
T837 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1690572904 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:16 PM PDT 24 471089748 ps
T838 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3539593096 Jun 24 05:54:04 PM PDT 24 Jun 24 05:54:07 PM PDT 24 552909929 ps
T839 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.178087170 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:05 PM PDT 24 2500371712 ps
T840 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2845317072 Jun 24 05:54:21 PM PDT 24 Jun 24 05:54:23 PM PDT 24 533579153 ps
T841 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1738745238 Jun 24 05:54:03 PM PDT 24 Jun 24 05:54:29 PM PDT 24 9127116835 ps
T136 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1827515135 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:54 PM PDT 24 20162096734 ps
T842 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3558302089 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:16 PM PDT 24 546696812 ps
T843 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.899308935 Jun 24 05:54:26 PM PDT 24 Jun 24 05:54:28 PM PDT 24 545388063 ps
T844 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2225925532 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:21 PM PDT 24 5303288334 ps
T845 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.167146143 Jun 24 05:54:16 PM PDT 24 Jun 24 05:54:19 PM PDT 24 521250658 ps
T846 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.260454177 Jun 24 05:54:03 PM PDT 24 Jun 24 05:54:06 PM PDT 24 636665100 ps
T847 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3929990631 Jun 24 05:54:04 PM PDT 24 Jun 24 05:54:07 PM PDT 24 521844488 ps
T137 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3551372205 Jun 24 05:53:57 PM PDT 24 Jun 24 05:54:01 PM PDT 24 1281297065 ps
T848 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.836528492 Jun 24 05:54:21 PM PDT 24 Jun 24 05:54:23 PM PDT 24 342832490 ps
T849 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3644331695 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:04 PM PDT 24 571300607 ps
T850 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.963164688 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:18 PM PDT 24 5079143517 ps
T851 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.546183531 Jun 24 05:54:07 PM PDT 24 Jun 24 05:54:11 PM PDT 24 698234826 ps
T852 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1238872753 Jun 24 05:54:17 PM PDT 24 Jun 24 05:54:19 PM PDT 24 483381559 ps
T853 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4059504051 Jun 24 05:54:00 PM PDT 24 Jun 24 05:54:02 PM PDT 24 557435888 ps
T854 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4214219549 Jun 24 05:54:15 PM PDT 24 Jun 24 05:54:17 PM PDT 24 319619139 ps
T855 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3034620358 Jun 24 05:54:16 PM PDT 24 Jun 24 05:54:20 PM PDT 24 2542139118 ps
T327 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1028535801 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:24 PM PDT 24 8519869085 ps
T856 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2234785103 Jun 24 05:53:59 PM PDT 24 Jun 24 05:54:02 PM PDT 24 404311733 ps
T857 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3241407696 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:18 PM PDT 24 586365022 ps
T328 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1779246877 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:21 PM PDT 24 4726850090 ps
T858 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3940382706 Jun 24 05:53:55 PM PDT 24 Jun 24 05:53:59 PM PDT 24 1062259671 ps
T330 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.339778655 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:34 PM PDT 24 8168590758 ps
T859 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2874049727 Jun 24 05:54:10 PM PDT 24 Jun 24 05:54:12 PM PDT 24 516162819 ps
T860 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2272159769 Jun 24 05:53:53 PM PDT 24 Jun 24 05:53:56 PM PDT 24 395801270 ps
T861 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.241973129 Jun 24 05:54:25 PM PDT 24 Jun 24 05:54:28 PM PDT 24 2414761472 ps
T862 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1474050060 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:16 PM PDT 24 824022140 ps
T863 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.906517957 Jun 24 05:53:55 PM PDT 24 Jun 24 05:53:58 PM PDT 24 601565802 ps
T138 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1846318218 Jun 24 05:54:04 PM PDT 24 Jun 24 05:54:07 PM PDT 24 326871305 ps
T864 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3074366970 Jun 24 05:54:16 PM PDT 24 Jun 24 05:54:30 PM PDT 24 4710954462 ps
T865 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1095835482 Jun 24 05:53:55 PM PDT 24 Jun 24 05:54:01 PM PDT 24 9721186331 ps
T866 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1075256729 Jun 24 05:54:10 PM PDT 24 Jun 24 05:54:12 PM PDT 24 499107813 ps
T867 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3853333131 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:05 PM PDT 24 578430232 ps
T868 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2969317358 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:26 PM PDT 24 700481701 ps
T869 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2346727006 Jun 24 05:54:10 PM PDT 24 Jun 24 05:54:15 PM PDT 24 782469672 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1136632473 Jun 24 05:53:53 PM PDT 24 Jun 24 05:53:55 PM PDT 24 503783255 ps
T871 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4187120606 Jun 24 05:54:26 PM PDT 24 Jun 24 05:54:29 PM PDT 24 344439320 ps
T872 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3079629522 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:26 PM PDT 24 483915696 ps
T873 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2167586196 Jun 24 05:54:26 PM PDT 24 Jun 24 05:54:29 PM PDT 24 558765067 ps
T874 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.466161351 Jun 24 05:54:14 PM PDT 24 Jun 24 05:54:16 PM PDT 24 385557437 ps
T875 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1862348486 Jun 24 05:54:00 PM PDT 24 Jun 24 05:54:02 PM PDT 24 339484207 ps
T876 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1231961481 Jun 24 05:54:16 PM PDT 24 Jun 24 05:54:21 PM PDT 24 932602475 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2908113931 Jun 24 05:53:59 PM PDT 24 Jun 24 05:54:02 PM PDT 24 340004884 ps
T878 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2113540905 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:04 PM PDT 24 1911316176 ps
T879 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1079789253 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:27 PM PDT 24 437749751 ps
T139 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.963703105 Jun 24 05:53:54 PM PDT 24 Jun 24 05:54:19 PM PDT 24 26636309037 ps
T880 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.57276638 Jun 24 05:53:51 PM PDT 24 Jun 24 05:53:54 PM PDT 24 337004322 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.803487214 Jun 24 05:54:00 PM PDT 24 Jun 24 05:54:05 PM PDT 24 859693282 ps
T882 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.144268057 Jun 24 05:54:00 PM PDT 24 Jun 24 05:54:05 PM PDT 24 677939408 ps
T883 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.420537009 Jun 24 05:53:54 PM PDT 24 Jun 24 05:53:57 PM PDT 24 643805920 ps
T884 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2116520110 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:16 PM PDT 24 671107552 ps
T885 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1269864446 Jun 24 05:54:11 PM PDT 24 Jun 24 05:54:14 PM PDT 24 507855885 ps
T886 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2629377354 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:25 PM PDT 24 560633991 ps
T887 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.272623537 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:15 PM PDT 24 465510977 ps
T888 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.424967031 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:09 PM PDT 24 3832727508 ps
T889 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3542286859 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:36 PM PDT 24 8038088700 ps
T890 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3547152102 Jun 24 05:54:06 PM PDT 24 Jun 24 05:54:08 PM PDT 24 330187328 ps
T891 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3434987778 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:26 PM PDT 24 482724998 ps
T892 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2328431721 Jun 24 05:54:15 PM PDT 24 Jun 24 05:54:17 PM PDT 24 331978607 ps
T893 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.510580182 Jun 24 05:54:04 PM PDT 24 Jun 24 05:54:07 PM PDT 24 560543416 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2880043829 Jun 24 05:53:56 PM PDT 24 Jun 24 05:53:59 PM PDT 24 499185807 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3537289200 Jun 24 05:54:14 PM PDT 24 Jun 24 05:54:17 PM PDT 24 718055500 ps
T896 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2095829734 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:26 PM PDT 24 368573681 ps
T897 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3264772460 Jun 24 05:54:22 PM PDT 24 Jun 24 05:54:24 PM PDT 24 363003329 ps
T898 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2237931036 Jun 24 05:53:59 PM PDT 24 Jun 24 05:54:03 PM PDT 24 932677090 ps
T899 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3604208014 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:28 PM PDT 24 335141262 ps
T900 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.455000623 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:21 PM PDT 24 8113632972 ps
T901 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3440348996 Jun 24 05:54:25 PM PDT 24 Jun 24 05:54:34 PM PDT 24 4915648423 ps
T902 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2444252726 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:24 PM PDT 24 4290355221 ps
T79 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3373341954 Jun 24 05:54:02 PM PDT 24 Jun 24 05:54:24 PM PDT 24 8605790295 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1446768792 Jun 24 05:53:59 PM PDT 24 Jun 24 05:54:05 PM PDT 24 4836325712 ps
T904 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2867909766 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:27 PM PDT 24 346089203 ps
T905 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.547679009 Jun 24 05:54:17 PM PDT 24 Jun 24 05:54:22 PM PDT 24 470965507 ps
T906 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.733200912 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:28 PM PDT 24 462393856 ps
T907 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.580676213 Jun 24 05:54:01 PM PDT 24 Jun 24 05:54:06 PM PDT 24 614297518 ps
T908 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.195707567 Jun 24 05:54:11 PM PDT 24 Jun 24 05:54:14 PM PDT 24 354377223 ps
T909 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3426938113 Jun 24 05:54:09 PM PDT 24 Jun 24 05:54:12 PM PDT 24 508401394 ps
T910 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2356825763 Jun 24 05:54:12 PM PDT 24 Jun 24 05:54:19 PM PDT 24 1895726016 ps
T911 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.172864501 Jun 24 05:54:17 PM PDT 24 Jun 24 05:54:19 PM PDT 24 480791603 ps
T912 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2513260082 Jun 24 05:54:23 PM PDT 24 Jun 24 05:54:26 PM PDT 24 322797464 ps
T913 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.819250464 Jun 24 05:54:25 PM PDT 24 Jun 24 05:54:29 PM PDT 24 446026232 ps
T914 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.100823162 Jun 24 05:54:04 PM PDT 24 Jun 24 05:54:08 PM PDT 24 596929727 ps
T915 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.26963035 Jun 24 05:53:55 PM PDT 24 Jun 24 05:53:58 PM PDT 24 305568852 ps
T916 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3945667663 Jun 24 05:54:26 PM PDT 24 Jun 24 05:54:29 PM PDT 24 536917463 ps
T917 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2216477462 Jun 24 05:54:13 PM PDT 24 Jun 24 05:54:17 PM PDT 24 487085092 ps
T918 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2101382174 Jun 24 05:53:54 PM PDT 24 Jun 24 05:53:56 PM PDT 24 592485518 ps
T919 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2371942783 Jun 24 05:53:53 PM PDT 24 Jun 24 05:53:56 PM PDT 24 1351527458 ps
T920 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4000580318 Jun 24 05:54:03 PM PDT 24 Jun 24 05:54:10 PM PDT 24 8573350766 ps

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1597720303
Short name T8
Test name
Test status
Simulation time 360673038254 ps
CPU time 794.33 seconds
Started Jun 24 06:00:00 PM PDT 24
Finished Jun 24 06:13:16 PM PDT 24
Peak memory 202184 kb
Host smart-98779787-cb15-45cd-89ab-948781f7a6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597720303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1597720303
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2005476394
Short name T12
Test name
Test status
Simulation time 284250594344 ps
CPU time 954.67 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 06:11:38 PM PDT 24
Peak memory 210728 kb
Host smart-6f16a1cc-f023-4a3e-a295-1dab6d9ed53d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005476394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2005476394
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.250301176
Short name T5
Test name
Test status
Simulation time 547683995589 ps
CPU time 333.95 seconds
Started Jun 24 05:59:52 PM PDT 24
Finished Jun 24 06:05:26 PM PDT 24
Peak memory 202208 kb
Host smart-0d5ad413-a978-4c81-a515-f70b479bee83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250301176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.250301176
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.221045760
Short name T46
Test name
Test status
Simulation time 729358092651 ps
CPU time 326.85 seconds
Started Jun 24 05:56:02 PM PDT 24
Finished Jun 24 06:01:30 PM PDT 24
Peak memory 218956 kb
Host smart-56edd554-fe24-4c89-8f9f-cb62c0065998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221045760 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.221045760
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.212935831
Short name T251
Test name
Test status
Simulation time 522015691594 ps
CPU time 276.68 seconds
Started Jun 24 05:59:16 PM PDT 24
Finished Jun 24 06:03:53 PM PDT 24
Peak memory 202212 kb
Host smart-44356b69-ec82-49f4-9cd0-72fc4d983cc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212935831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.212935831
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3582344680
Short name T13
Test name
Test status
Simulation time 26147437939 ps
CPU time 70.43 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 05:56:21 PM PDT 24
Peak memory 210868 kb
Host smart-f32a8d14-56f0-4394-b858-a77f1f382895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582344680 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3582344680
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.44715340
Short name T89
Test name
Test status
Simulation time 519064246130 ps
CPU time 1178.9 seconds
Started Jun 24 05:59:26 PM PDT 24
Finished Jun 24 06:19:06 PM PDT 24
Peak memory 202272 kb
Host smart-cd9530f6-7d6c-4b98-ab76-0de57b53596f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44715340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gatin
g.44715340
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3777686220
Short name T159
Test name
Test status
Simulation time 495681499651 ps
CPU time 279.06 seconds
Started Jun 24 05:59:55 PM PDT 24
Finished Jun 24 06:04:34 PM PDT 24
Peak memory 202356 kb
Host smart-a1a56ec3-98ae-4f14-a72c-12fa5c906422
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777686220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3777686220
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3781215591
Short name T150
Test name
Test status
Simulation time 702820877651 ps
CPU time 969.88 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 06:12:01 PM PDT 24
Peak memory 202216 kb
Host smart-52ac59a2-654b-4294-a686-338fce0ccce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781215591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3781215591
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.753004946
Short name T148
Test name
Test status
Simulation time 88782536757 ps
CPU time 190.79 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 05:58:22 PM PDT 24
Peak memory 210828 kb
Host smart-011bdab1-b33b-47d7-93bb-5fd38b6f6e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753004946 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.753004946
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2343269145
Short name T73
Test name
Test status
Simulation time 809653579 ps
CPU time 2.55 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:06 PM PDT 24
Peak memory 217472 kb
Host smart-b31d91dd-e6f2-47fb-84cc-a2f9a07ff060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343269145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2343269145
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1694540885
Short name T25
Test name
Test status
Simulation time 197626530665 ps
CPU time 41.42 seconds
Started Jun 24 05:56:07 PM PDT 24
Finished Jun 24 05:56:49 PM PDT 24
Peak memory 202260 kb
Host smart-0a886427-ca39-4dd2-b3fe-84306aa22c25
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694540885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1694540885
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1936121628
Short name T176
Test name
Test status
Simulation time 616480556878 ps
CPU time 788.44 seconds
Started Jun 24 05:56:20 PM PDT 24
Finished Jun 24 06:09:29 PM PDT 24
Peak memory 210784 kb
Host smart-6e7ff1d9-093c-4367-9c36-4307caf55f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936121628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1936121628
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1569694865
Short name T70
Test name
Test status
Simulation time 4096383627 ps
CPU time 9.95 seconds
Started Jun 24 05:55:23 PM PDT 24
Finished Jun 24 05:55:34 PM PDT 24
Peak memory 217720 kb
Host smart-b9b3d0ba-7333-4e51-9e09-614cba410170
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569694865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1569694865
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1577972147
Short name T227
Test name
Test status
Simulation time 531089675852 ps
CPU time 593.85 seconds
Started Jun 24 05:59:44 PM PDT 24
Finished Jun 24 06:09:39 PM PDT 24
Peak memory 202292 kb
Host smart-716146ad-78b8-4f46-96a1-0aa6c1c168e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577972147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1577972147
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1932646901
Short name T272
Test name
Test status
Simulation time 505834896705 ps
CPU time 1205.74 seconds
Started Jun 24 05:56:44 PM PDT 24
Finished Jun 24 06:16:51 PM PDT 24
Peak memory 202256 kb
Host smart-640f348c-f062-44d8-b872-d74e8dd27aae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932646901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1932646901
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4223119020
Short name T60
Test name
Test status
Simulation time 16366939732 ps
CPU time 11.82 seconds
Started Jun 24 05:53:53 PM PDT 24
Finished Jun 24 05:54:06 PM PDT 24
Peak memory 201420 kb
Host smart-f4d49663-65d7-46f7-83d0-7a4cf3257491
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223119020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4223119020
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.329289881
Short name T42
Test name
Test status
Simulation time 154200438632 ps
CPU time 93.59 seconds
Started Jun 24 05:59:10 PM PDT 24
Finished Jun 24 06:00:44 PM PDT 24
Peak memory 202400 kb
Host smart-8fabeec8-f726-40f5-b290-f166090d2f25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329289881 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.329289881
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3825489843
Short name T185
Test name
Test status
Simulation time 517223356556 ps
CPU time 835.6 seconds
Started Jun 24 05:56:26 PM PDT 24
Finished Jun 24 06:10:22 PM PDT 24
Peak memory 202152 kb
Host smart-dec51afc-13ba-48be-91ca-29e733fbd1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825489843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3825489843
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2411056060
Short name T226
Test name
Test status
Simulation time 620901211368 ps
CPU time 731.57 seconds
Started Jun 24 05:57:14 PM PDT 24
Finished Jun 24 06:09:27 PM PDT 24
Peak memory 202292 kb
Host smart-fe558186-349f-464a-9c1a-240536db7bec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411056060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2411056060
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2468653943
Short name T170
Test name
Test status
Simulation time 568758296343 ps
CPU time 317.37 seconds
Started Jun 24 05:57:57 PM PDT 24
Finished Jun 24 06:03:15 PM PDT 24
Peak memory 202192 kb
Host smart-5294314b-b5aa-4e42-9f0f-9b270f6de49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468653943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2468653943
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.844522341
Short name T255
Test name
Test status
Simulation time 608164248508 ps
CPU time 1410.98 seconds
Started Jun 24 05:56:01 PM PDT 24
Finished Jun 24 06:19:33 PM PDT 24
Peak memory 202088 kb
Host smart-687230a8-3e83-48a9-a764-3d92bf8e5cc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844522341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.844522341
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3097959278
Short name T157
Test name
Test status
Simulation time 323916283869 ps
CPU time 193.87 seconds
Started Jun 24 05:58:13 PM PDT 24
Finished Jun 24 06:01:28 PM PDT 24
Peak memory 202224 kb
Host smart-5d2e2c83-f4b8-4df0-8971-ca9c69f7a5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097959278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3097959278
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.942035124
Short name T239
Test name
Test status
Simulation time 364431001633 ps
CPU time 203.1 seconds
Started Jun 24 05:55:47 PM PDT 24
Finished Jun 24 05:59:11 PM PDT 24
Peak memory 202292 kb
Host smart-5bd07d80-8c8a-40d1-bb7a-2d71cf39cb1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942035124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.942035124
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.876221627
Short name T268
Test name
Test status
Simulation time 553703797259 ps
CPU time 654.3 seconds
Started Jun 24 05:56:45 PM PDT 24
Finished Jun 24 06:07:40 PM PDT 24
Peak memory 202204 kb
Host smart-b8c7ec5b-b3ad-4aa2-a535-45df169bde99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876221627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.876221627
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2923580280
Short name T219
Test name
Test status
Simulation time 379006445047 ps
CPU time 868.32 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 06:10:09 PM PDT 24
Peak memory 210776 kb
Host smart-efdb23c1-8124-4950-a0f6-9e4e2b02f5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923580280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2923580280
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.474918556
Short name T286
Test name
Test status
Simulation time 64786441652 ps
CPU time 150.81 seconds
Started Jun 24 05:59:37 PM PDT 24
Finished Jun 24 06:02:08 PM PDT 24
Peak memory 210668 kb
Host smart-a723cc8e-ab04-4e97-b2ed-d858baa3b021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474918556 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.474918556
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2198037093
Short name T69
Test name
Test status
Simulation time 8713404194 ps
CPU time 4.8 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:19 PM PDT 24
Peak memory 201384 kb
Host smart-b0fec416-d3af-450c-b71b-1f897dac26b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198037093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2198037093
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.340913081
Short name T371
Test name
Test status
Simulation time 494011505 ps
CPU time 0.9 seconds
Started Jun 24 05:55:47 PM PDT 24
Finished Jun 24 05:55:49 PM PDT 24
Peak memory 201900 kb
Host smart-498510ea-9abe-4912-8349-dde5d7739524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340913081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.340913081
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1565068746
Short name T156
Test name
Test status
Simulation time 324800012763 ps
CPU time 211.56 seconds
Started Jun 24 05:56:18 PM PDT 24
Finished Jun 24 05:59:50 PM PDT 24
Peak memory 202216 kb
Host smart-0584d33b-7727-4456-aabf-be68ffa49eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565068746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1565068746
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1545146637
Short name T284
Test name
Test status
Simulation time 87780334775 ps
CPU time 207.22 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 06:00:48 PM PDT 24
Peak memory 210856 kb
Host smart-93fdfa67-9db4-4735-aed6-e9dfbc72547a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545146637 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1545146637
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.657059377
Short name T248
Test name
Test status
Simulation time 504810295802 ps
CPU time 606.1 seconds
Started Jun 24 05:57:55 PM PDT 24
Finished Jun 24 06:08:02 PM PDT 24
Peak memory 202208 kb
Host smart-ad57e9e8-bb08-41c2-8cd2-c0e08b69bfca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657059377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.657059377
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3469631949
Short name T10
Test name
Test status
Simulation time 280721378282 ps
CPU time 603.25 seconds
Started Jun 24 05:55:17 PM PDT 24
Finished Jun 24 06:05:21 PM PDT 24
Peak memory 202216 kb
Host smart-879b48ce-beaa-45bb-9492-94f08ed55697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469631949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3469631949
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.681779259
Short name T38
Test name
Test status
Simulation time 324543582050 ps
CPU time 732.62 seconds
Started Jun 24 06:00:01 PM PDT 24
Finished Jun 24 06:12:15 PM PDT 24
Peak memory 202220 kb
Host smart-5e6c63c5-77f8-4d99-b7ae-c8b44ed52936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681779259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.681779259
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.495706582
Short name T228
Test name
Test status
Simulation time 629069215843 ps
CPU time 314.82 seconds
Started Jun 24 06:00:02 PM PDT 24
Finished Jun 24 06:05:18 PM PDT 24
Peak memory 202192 kb
Host smart-92f25de7-c603-4176-a6b7-37a2710e20b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495706582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.495706582
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.173363186
Short name T244
Test name
Test status
Simulation time 334704735197 ps
CPU time 397.96 seconds
Started Jun 24 05:55:41 PM PDT 24
Finished Jun 24 06:02:20 PM PDT 24
Peak memory 202204 kb
Host smart-85b43340-5d85-436e-820e-ae2ca054fb55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173363186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.173363186
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.584026834
Short name T295
Test name
Test status
Simulation time 522836497033 ps
CPU time 300.33 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 06:00:52 PM PDT 24
Peak memory 202216 kb
Host smart-1d78e5cd-2566-45ec-8620-0e6a55e3edd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584026834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.584026834
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3799201061
Short name T67
Test name
Test status
Simulation time 75228577424 ps
CPU time 177.43 seconds
Started Jun 24 05:56:35 PM PDT 24
Finished Jun 24 05:59:32 PM PDT 24
Peak memory 210440 kb
Host smart-49c117c6-aa62-42b8-960b-9f692fcc07aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799201061 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3799201061
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2781818470
Short name T194
Test name
Test status
Simulation time 168987881048 ps
CPU time 134.15 seconds
Started Jun 24 05:57:38 PM PDT 24
Finished Jun 24 05:59:53 PM PDT 24
Peak memory 202256 kb
Host smart-a9f933a0-7385-430b-bf01-7c4af23f3179
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781818470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2781818470
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1123992619
Short name T224
Test name
Test status
Simulation time 509399429117 ps
CPU time 145.35 seconds
Started Jun 24 05:58:04 PM PDT 24
Finished Jun 24 06:00:30 PM PDT 24
Peak memory 202180 kb
Host smart-49adda47-232e-4aee-8d24-15203364c61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123992619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1123992619
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3906990637
Short name T43
Test name
Test status
Simulation time 293259596581 ps
CPU time 634.76 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 06:05:57 PM PDT 24
Peak memory 211836 kb
Host smart-0d096281-c89e-458b-80c8-5110814a501c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906990637 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3906990637
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2666786820
Short name T143
Test name
Test status
Simulation time 2025720737 ps
CPU time 1.96 seconds
Started Jun 24 05:53:56 PM PDT 24
Finished Jun 24 05:54:00 PM PDT 24
Peak memory 201132 kb
Host smart-f0038498-e96b-4d82-ad93-26c7a4d66893
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666786820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2666786820
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.138284071
Short name T126
Test name
Test status
Simulation time 392507716491 ps
CPU time 965.33 seconds
Started Jun 24 05:55:57 PM PDT 24
Finished Jun 24 06:12:04 PM PDT 24
Peak memory 202456 kb
Host smart-2d8d86ea-c01b-455f-acd4-43dc177987f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138284071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.138284071
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2186148549
Short name T229
Test name
Test status
Simulation time 354918768705 ps
CPU time 404.93 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 06:03:48 PM PDT 24
Peak memory 202192 kb
Host smart-107cca2d-5de4-4f9f-850d-783961f2051f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186148549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2186148549
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.4129047027
Short name T236
Test name
Test status
Simulation time 163903185898 ps
CPU time 185.6 seconds
Started Jun 24 06:00:10 PM PDT 24
Finished Jun 24 06:03:17 PM PDT 24
Peak memory 202188 kb
Host smart-6eea231b-9857-4e75-9a6c-0b63f3fd53ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129047027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.4129047027
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2027968289
Short name T27
Test name
Test status
Simulation time 494226120396 ps
CPU time 1184.31 seconds
Started Jun 24 05:55:58 PM PDT 24
Finished Jun 24 06:15:44 PM PDT 24
Peak memory 202512 kb
Host smart-6e2e4eac-31c2-4dca-8dbe-bbeacb8781f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027968289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2027968289
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.4066440534
Short name T296
Test name
Test status
Simulation time 539079857966 ps
CPU time 312.3 seconds
Started Jun 24 05:56:36 PM PDT 24
Finished Jun 24 06:01:49 PM PDT 24
Peak memory 202204 kb
Host smart-42e94c4b-fb61-4296-b69e-3bfe2c03b3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066440534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4066440534
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3983046839
Short name T282
Test name
Test status
Simulation time 259732575216 ps
CPU time 846.05 seconds
Started Jun 24 05:56:48 PM PDT 24
Finished Jun 24 06:10:54 PM PDT 24
Peak memory 202488 kb
Host smart-29b1001b-2e95-4020-85d7-05ec2da9ed76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983046839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3983046839
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3590373538
Short name T37
Test name
Test status
Simulation time 350606557616 ps
CPU time 179.41 seconds
Started Jun 24 05:55:51 PM PDT 24
Finished Jun 24 05:58:51 PM PDT 24
Peak memory 202120 kb
Host smart-3759d9f2-847b-492d-afa0-aa2891fe1991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590373538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3590373538
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2842929783
Short name T283
Test name
Test status
Simulation time 60978335658 ps
CPU time 170.24 seconds
Started Jun 24 05:57:12 PM PDT 24
Finished Jun 24 06:00:03 PM PDT 24
Peak memory 210824 kb
Host smart-08dfbfdd-bc73-4dde-adad-266dccca4b99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842929783 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2842929783
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.89851541
Short name T281
Test name
Test status
Simulation time 475832846893 ps
CPU time 853.21 seconds
Started Jun 24 05:58:51 PM PDT 24
Finished Jun 24 06:13:05 PM PDT 24
Peak memory 218928 kb
Host smart-e4be68b7-4316-4562-bf6f-d4d92b9dfd6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89851541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.89851541
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1858161280
Short name T192
Test name
Test status
Simulation time 328261325262 ps
CPU time 692.73 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 06:06:46 PM PDT 24
Peak memory 202236 kb
Host smart-28b777bf-be3a-43ff-ad08-0367b06f0c4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858161280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1858161280
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1800598624
Short name T288
Test name
Test status
Simulation time 167816447932 ps
CPU time 195.19 seconds
Started Jun 24 05:55:44 PM PDT 24
Finished Jun 24 05:59:00 PM PDT 24
Peak memory 202216 kb
Host smart-cd321d4b-e219-44eb-871b-dfbc1f4b96f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800598624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1800598624
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1210492411
Short name T240
Test name
Test status
Simulation time 482639979004 ps
CPU time 1097.01 seconds
Started Jun 24 05:55:55 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 202216 kb
Host smart-d7cb081d-b39e-4974-8337-d6f97c6fec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210492411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1210492411
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3479768153
Short name T222
Test name
Test status
Simulation time 488642347305 ps
CPU time 303.66 seconds
Started Jun 24 05:56:23 PM PDT 24
Finished Jun 24 06:01:27 PM PDT 24
Peak memory 202268 kb
Host smart-9a5a24f8-971b-410e-bf11-4c02da128847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479768153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3479768153
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.322779181
Short name T292
Test name
Test status
Simulation time 164529821838 ps
CPU time 101.36 seconds
Started Jun 24 05:57:39 PM PDT 24
Finished Jun 24 05:59:20 PM PDT 24
Peak memory 202216 kb
Host smart-1e2f32b0-5876-418e-86ff-5bc192b145e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322779181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.322779181
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.274854341
Short name T258
Test name
Test status
Simulation time 706040716634 ps
CPU time 422.29 seconds
Started Jun 24 05:58:30 PM PDT 24
Finished Jun 24 06:05:33 PM PDT 24
Peak memory 202220 kb
Host smart-e6d514d1-432f-4c25-829b-3bce8043cf32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274854341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.274854341
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2292648116
Short name T440
Test name
Test status
Simulation time 353794914203 ps
CPU time 595.77 seconds
Started Jun 24 05:55:19 PM PDT 24
Finished Jun 24 06:05:16 PM PDT 24
Peak memory 210716 kb
Host smart-4ec22817-d832-489e-abd2-e26ed171055f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292648116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2292648116
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1046584492
Short name T256
Test name
Test status
Simulation time 487202290243 ps
CPU time 1028.64 seconds
Started Jun 24 05:55:32 PM PDT 24
Finished Jun 24 06:12:43 PM PDT 24
Peak memory 202212 kb
Host smart-40d16e8d-1291-4d7e-b02d-4a28f97dbac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046584492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1046584492
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.339778655
Short name T330
Test name
Test status
Simulation time 8168590758 ps
CPU time 20.07 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:34 PM PDT 24
Peak memory 201336 kb
Host smart-b2c1abe0-36f0-4695-b7fe-5c07d979a85e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339778655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.339778655
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3928915131
Short name T151
Test name
Test status
Simulation time 528469944399 ps
CPU time 1154.58 seconds
Started Jun 24 05:55:48 PM PDT 24
Finished Jun 24 06:15:03 PM PDT 24
Peak memory 202276 kb
Host smart-0f920806-66f0-4a15-8f1c-8debd4f42a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928915131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3928915131
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3132920467
Short name T98
Test name
Test status
Simulation time 159667057371 ps
CPU time 189.69 seconds
Started Jun 24 05:57:22 PM PDT 24
Finished Jun 24 06:00:33 PM PDT 24
Peak memory 202292 kb
Host smart-fd89c6d8-7469-47ce-a020-c4d5d7a3053e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132920467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3132920467
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.181279625
Short name T87
Test name
Test status
Simulation time 324351660390 ps
CPU time 742.22 seconds
Started Jun 24 05:57:45 PM PDT 24
Finished Jun 24 06:10:09 PM PDT 24
Peak memory 202232 kb
Host smart-6eb53b29-41f6-4607-9a91-e76cda6b9f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181279625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.181279625
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.299625400
Short name T234
Test name
Test status
Simulation time 326817167404 ps
CPU time 807.33 seconds
Started Jun 24 05:57:57 PM PDT 24
Finished Jun 24 06:11:25 PM PDT 24
Peak memory 202284 kb
Host smart-27a6c170-d9f1-42ad-9261-cc18f8a53dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299625400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.299625400
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2201504469
Short name T304
Test name
Test status
Simulation time 189479151457 ps
CPU time 162.28 seconds
Started Jun 24 05:59:25 PM PDT 24
Finished Jun 24 06:02:08 PM PDT 24
Peak memory 202188 kb
Host smart-cc890599-9aeb-4058-92f6-c49a107deef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201504469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2201504469
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4257696479
Short name T242
Test name
Test status
Simulation time 481345404604 ps
CPU time 1321.54 seconds
Started Jun 24 05:55:30 PM PDT 24
Finished Jun 24 06:17:33 PM PDT 24
Peak memory 210704 kb
Host smart-1f0a62be-411d-4666-a40d-22c8539d02f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257696479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4257696479
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3348830048
Short name T223
Test name
Test status
Simulation time 167074299640 ps
CPU time 367.3 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 06:01:38 PM PDT 24
Peak memory 202196 kb
Host smart-c3a499ed-19cd-4fef-9d48-ab01006a77af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348830048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3348830048
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3940382706
Short name T858
Test name
Test status
Simulation time 1062259671 ps
CPU time 2.47 seconds
Started Jun 24 05:53:55 PM PDT 24
Finished Jun 24 05:53:59 PM PDT 24
Peak memory 201368 kb
Host smart-63f48a52-77ee-4a70-bb53-6be4d7a99db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940382706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3940382706
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1443111767
Short name T3
Test name
Test status
Simulation time 164529925235 ps
CPU time 368.81 seconds
Started Jun 24 05:55:33 PM PDT 24
Finished Jun 24 06:01:43 PM PDT 24
Peak memory 202308 kb
Host smart-5e90d7d1-91b4-4d07-8231-9ade707e6f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443111767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1443111767
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3337686894
Short name T271
Test name
Test status
Simulation time 632244773423 ps
CPU time 224.15 seconds
Started Jun 24 05:55:41 PM PDT 24
Finished Jun 24 05:59:26 PM PDT 24
Peak memory 202188 kb
Host smart-1c707d4c-fed0-4fee-a545-80c1ca547f91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337686894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3337686894
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3400581585
Short name T337
Test name
Test status
Simulation time 81954590920 ps
CPU time 435.08 seconds
Started Jun 24 05:55:44 PM PDT 24
Finished Jun 24 06:03:00 PM PDT 24
Peak memory 202540 kb
Host smart-9ae1f75e-c5f3-4466-886d-f62efa74d692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400581585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3400581585
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2409893439
Short name T333
Test name
Test status
Simulation time 114575261288 ps
CPU time 633.83 seconds
Started Jun 24 05:55:44 PM PDT 24
Finished Jun 24 06:06:19 PM PDT 24
Peak memory 202488 kb
Host smart-18d2d986-04a9-49c8-a6cf-180774000416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409893439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2409893439
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.79309202
Short name T334
Test name
Test status
Simulation time 92175900527 ps
CPU time 335.44 seconds
Started Jun 24 05:56:52 PM PDT 24
Finished Jun 24 06:02:28 PM PDT 24
Peak memory 202560 kb
Host smart-629a7bf7-70fb-4a96-8baf-2dda10b7bb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79309202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.79309202
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.4038459666
Short name T322
Test name
Test status
Simulation time 822150693075 ps
CPU time 831.57 seconds
Started Jun 24 05:58:40 PM PDT 24
Finished Jun 24 06:12:32 PM PDT 24
Peak memory 202564 kb
Host smart-c29ed83c-2bc2-4cd2-b974-83c2000cdede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038459666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.4038459666
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3510338054
Short name T54
Test name
Test status
Simulation time 131535010960 ps
CPU time 709.35 seconds
Started Jun 24 05:55:22 PM PDT 24
Finished Jun 24 06:07:14 PM PDT 24
Peak memory 202508 kb
Host smart-d4f0b5f5-52b0-4f7f-af34-cc642e19ae1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510338054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3510338054
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1001040459
Short name T266
Test name
Test status
Simulation time 491519416695 ps
CPU time 1127.79 seconds
Started Jun 24 05:59:10 PM PDT 24
Finished Jun 24 06:17:58 PM PDT 24
Peak memory 202280 kb
Host smart-5d145ed0-add9-4177-9762-b1aa45d81f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001040459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1001040459
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2113179239
Short name T186
Test name
Test status
Simulation time 494647957685 ps
CPU time 208.29 seconds
Started Jun 24 06:00:10 PM PDT 24
Finished Jun 24 06:03:39 PM PDT 24
Peak memory 202272 kb
Host smart-46f1d55c-58f7-41dc-a2aa-18d990f389e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113179239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2113179239
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1578934754
Short name T217
Test name
Test status
Simulation time 319875975855 ps
CPU time 495.11 seconds
Started Jun 24 06:00:37 PM PDT 24
Finished Jun 24 06:08:53 PM PDT 24
Peak memory 202560 kb
Host smart-93f45207-cdfd-49b4-ba84-dafbd65af62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578934754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1578934754
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.803487214
Short name T881
Test name
Test status
Simulation time 859693282 ps
CPU time 3.74 seconds
Started Jun 24 05:54:00 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201296 kb
Host smart-cbbddac5-a75c-403f-820f-404c199e3389
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803487214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.803487214
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2371942783
Short name T919
Test name
Test status
Simulation time 1351527458 ps
CPU time 2.27 seconds
Started Jun 24 05:53:53 PM PDT 24
Finished Jun 24 05:53:56 PM PDT 24
Peak memory 201112 kb
Host smart-21c39ec9-e496-4830-9969-64c1ac828893
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371942783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2371942783
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.420537009
Short name T883
Test name
Test status
Simulation time 643805920 ps
CPU time 2.39 seconds
Started Jun 24 05:53:54 PM PDT 24
Finished Jun 24 05:53:57 PM PDT 24
Peak memory 201192 kb
Host smart-2b5214a6-a59b-46a3-95f8-6866db12dc63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420537009 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.420537009
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2101382174
Short name T918
Test name
Test status
Simulation time 592485518 ps
CPU time 0.93 seconds
Started Jun 24 05:53:54 PM PDT 24
Finished Jun 24 05:53:56 PM PDT 24
Peak memory 201132 kb
Host smart-68d12cb4-e2d5-4597-b355-392145b72cf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101382174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2101382174
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2234785103
Short name T856
Test name
Test status
Simulation time 404311733 ps
CPU time 1.57 seconds
Started Jun 24 05:53:59 PM PDT 24
Finished Jun 24 05:54:02 PM PDT 24
Peak memory 201096 kb
Host smart-39250542-dc62-484e-ba36-d3acee64b318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234785103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2234785103
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.57276638
Short name T880
Test name
Test status
Simulation time 337004322 ps
CPU time 2.05 seconds
Started Jun 24 05:53:51 PM PDT 24
Finished Jun 24 05:53:54 PM PDT 24
Peak memory 201324 kb
Host smart-9b673496-7aba-4443-b867-96f9b0b53efc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57276638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.57276638
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3597177378
Short name T66
Test name
Test status
Simulation time 4591843085 ps
CPU time 3.48 seconds
Started Jun 24 05:53:55 PM PDT 24
Finished Jun 24 05:54:01 PM PDT 24
Peak memory 201360 kb
Host smart-f57bf2b1-1f0e-4ca6-bf74-a2ba4c0657e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597177378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3597177378
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3551372205
Short name T137
Test name
Test status
Simulation time 1281297065 ps
CPU time 2.48 seconds
Started Jun 24 05:53:57 PM PDT 24
Finished Jun 24 05:54:01 PM PDT 24
Peak memory 201280 kb
Host smart-205cb5ff-064f-4510-867d-467010ac3867
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551372205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3551372205
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.963703105
Short name T139
Test name
Test status
Simulation time 26636309037 ps
CPU time 24.06 seconds
Started Jun 24 05:53:54 PM PDT 24
Finished Jun 24 05:54:19 PM PDT 24
Peak memory 201344 kb
Host smart-ec43e617-51ad-4c80-8196-e3c14666b14d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963703105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.963703105
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2610551412
Short name T811
Test name
Test status
Simulation time 950275743 ps
CPU time 2.78 seconds
Started Jun 24 05:53:58 PM PDT 24
Finished Jun 24 05:54:01 PM PDT 24
Peak memory 201084 kb
Host smart-ac802464-3fb3-4163-9347-d3846cd0a0a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610551412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2610551412
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1136632473
Short name T870
Test name
Test status
Simulation time 503783255 ps
CPU time 1.54 seconds
Started Jun 24 05:53:53 PM PDT 24
Finished Jun 24 05:53:55 PM PDT 24
Peak memory 201208 kb
Host smart-f3b89f4a-d3ae-471b-9d61-33d9e4d52a16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136632473 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1136632473
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2880043829
Short name T894
Test name
Test status
Simulation time 499185807 ps
CPU time 1.05 seconds
Started Jun 24 05:53:56 PM PDT 24
Finished Jun 24 05:53:59 PM PDT 24
Peak memory 201132 kb
Host smart-14800b52-03e9-4108-9304-724851abb8eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880043829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2880043829
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2272159769
Short name T860
Test name
Test status
Simulation time 395801270 ps
CPU time 1.57 seconds
Started Jun 24 05:53:53 PM PDT 24
Finished Jun 24 05:53:56 PM PDT 24
Peak memory 201108 kb
Host smart-b7615b99-3a34-4011-a9ab-d5a38c8346d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272159769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2272159769
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4239106165
Short name T144
Test name
Test status
Simulation time 2694526628 ps
CPU time 6.34 seconds
Started Jun 24 05:53:52 PM PDT 24
Finished Jun 24 05:53:59 PM PDT 24
Peak memory 201164 kb
Host smart-0fc9a36d-0dd7-4a5a-a1d1-e0f324c19515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239106165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.4239106165
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1095835482
Short name T865
Test name
Test status
Simulation time 9721186331 ps
CPU time 4.59 seconds
Started Jun 24 05:53:55 PM PDT 24
Finished Jun 24 05:54:01 PM PDT 24
Peak memory 201340 kb
Host smart-e382768a-1bdd-48a1-9b5d-a5947a54d3c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095835482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1095835482
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1209524586
Short name T825
Test name
Test status
Simulation time 452842928 ps
CPU time 1.61 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:15 PM PDT 24
Peak memory 201196 kb
Host smart-c649e5f7-d26b-4b2f-8e2b-87a4d7ad31a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209524586 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1209524586
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1846318218
Short name T138
Test name
Test status
Simulation time 326871305 ps
CPU time 1.13 seconds
Started Jun 24 05:54:04 PM PDT 24
Finished Jun 24 05:54:07 PM PDT 24
Peak memory 201128 kb
Host smart-0ca38569-3721-4bfb-9bc3-bc8b9d21657e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846318218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1846318218
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2874049727
Short name T859
Test name
Test status
Simulation time 516162819 ps
CPU time 0.8 seconds
Started Jun 24 05:54:10 PM PDT 24
Finished Jun 24 05:54:12 PM PDT 24
Peak memory 201116 kb
Host smart-cfa48630-6a22-4c99-bdeb-b6839f8f2518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874049727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2874049727
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2225925532
Short name T844
Test name
Test status
Simulation time 5303288334 ps
CPU time 6.12 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:21 PM PDT 24
Peak memory 201368 kb
Host smart-667c3fa8-6571-43c4-a495-73ff75beb42c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225925532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2225925532
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1827575652
Short name T74
Test name
Test status
Simulation time 1227801129 ps
CPU time 1.16 seconds
Started Jun 24 05:54:06 PM PDT 24
Finished Jun 24 05:54:09 PM PDT 24
Peak memory 201188 kb
Host smart-4942396f-56ed-4dc7-a6af-032968aba813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827575652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1827575652
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1305766740
Short name T828
Test name
Test status
Simulation time 4393093016 ps
CPU time 12.33 seconds
Started Jun 24 05:54:07 PM PDT 24
Finished Jun 24 05:54:20 PM PDT 24
Peak memory 201392 kb
Host smart-290459ae-9c62-4167-bfef-fdab60111124
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305766740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1305766740
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3558302089
Short name T842
Test name
Test status
Simulation time 546696812 ps
CPU time 2.17 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:16 PM PDT 24
Peak memory 201168 kb
Host smart-f7c4981f-1e0d-49db-9410-eef38380432d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558302089 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3558302089
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.272623537
Short name T887
Test name
Test status
Simulation time 465510977 ps
CPU time 0.94 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:15 PM PDT 24
Peak memory 201124 kb
Host smart-381fc948-ee2e-477d-92e9-5a38284ff9f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272623537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.272623537
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.589197321
Short name T805
Test name
Test status
Simulation time 490927532 ps
CPU time 0.87 seconds
Started Jun 24 05:54:09 PM PDT 24
Finished Jun 24 05:54:12 PM PDT 24
Peak memory 201112 kb
Host smart-f261d2fa-e0a3-46a7-bb53-0356ad536961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589197321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.589197321
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2356825763
Short name T910
Test name
Test status
Simulation time 1895726016 ps
CPU time 5.3 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:19 PM PDT 24
Peak memory 201108 kb
Host smart-d9903433-0f78-4135-ab52-f02c777cd0bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356825763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2356825763
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.581632105
Short name T77
Test name
Test status
Simulation time 917481066 ps
CPU time 3.11 seconds
Started Jun 24 05:54:15 PM PDT 24
Finished Jun 24 05:54:20 PM PDT 24
Peak memory 209560 kb
Host smart-67e7f869-167e-452b-b8d4-0872fedf5737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581632105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.581632105
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1779246877
Short name T328
Test name
Test status
Simulation time 4726850090 ps
CPU time 5.85 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:21 PM PDT 24
Peak memory 201396 kb
Host smart-527cf4f2-60b1-4abb-ad31-b6b9a53d049e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779246877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1779246877
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2116520110
Short name T884
Test name
Test status
Simulation time 671107552 ps
CPU time 1.31 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:16 PM PDT 24
Peak memory 201188 kb
Host smart-8abeee2e-8d68-4d24-85e8-c26a42b0e490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116520110 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2116520110
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2230958200
Short name T813
Test name
Test status
Simulation time 367555990 ps
CPU time 1.62 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:16 PM PDT 24
Peak memory 201148 kb
Host smart-e63b623d-fc7a-4597-a2ed-0b3081d3f184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230958200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2230958200
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.293724424
Short name T809
Test name
Test status
Simulation time 568496601 ps
CPU time 0.69 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:15 PM PDT 24
Peak memory 201112 kb
Host smart-25cd8fc2-835d-46f7-82d9-5a34a3f509a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293724424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.293724424
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1276991960
Short name T832
Test name
Test status
Simulation time 4729297854 ps
CPU time 7.69 seconds
Started Jun 24 05:54:11 PM PDT 24
Finished Jun 24 05:54:21 PM PDT 24
Peak memory 201368 kb
Host smart-999d355e-7126-4bd6-84e4-797af882b94c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276991960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1276991960
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1231961481
Short name T876
Test name
Test status
Simulation time 932602475 ps
CPU time 3.64 seconds
Started Jun 24 05:54:16 PM PDT 24
Finished Jun 24 05:54:21 PM PDT 24
Peak memory 201380 kb
Host smart-8388f4ef-feda-4e08-a06d-2b06c75c2df1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231961481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1231961481
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.455000623
Short name T900
Test name
Test status
Simulation time 8113632972 ps
CPU time 5.46 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:21 PM PDT 24
Peak memory 201364 kb
Host smart-b3c19b4d-af0b-45a6-b9de-3c955afc9657
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455000623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.455000623
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3537289200
Short name T895
Test name
Test status
Simulation time 718055500 ps
CPU time 1.66 seconds
Started Jun 24 05:54:14 PM PDT 24
Finished Jun 24 05:54:17 PM PDT 24
Peak memory 209864 kb
Host smart-9c93bba4-7649-42ad-baae-e237feec26ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537289200 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3537289200
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.172864501
Short name T911
Test name
Test status
Simulation time 480791603 ps
CPU time 1.06 seconds
Started Jun 24 05:54:17 PM PDT 24
Finished Jun 24 05:54:19 PM PDT 24
Peak memory 200572 kb
Host smart-9225aeb8-b5d7-4a09-9e62-edf4279cf3fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172864501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.172864501
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1238872753
Short name T852
Test name
Test status
Simulation time 483381559 ps
CPU time 0.74 seconds
Started Jun 24 05:54:17 PM PDT 24
Finished Jun 24 05:54:19 PM PDT 24
Peak memory 201120 kb
Host smart-33804fb5-da8c-4d05-9152-c1bf52adca04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238872753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1238872753
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2444252726
Short name T902
Test name
Test status
Simulation time 4290355221 ps
CPU time 9.09 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:24 PM PDT 24
Peak memory 201416 kb
Host smart-03539d2b-88e0-42d4-9e7a-2af9ebc290d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444252726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2444252726
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.404138136
Short name T68
Test name
Test status
Simulation time 501908996 ps
CPU time 3.68 seconds
Started Jun 24 05:54:11 PM PDT 24
Finished Jun 24 05:54:16 PM PDT 24
Peak memory 209620 kb
Host smart-17d476b3-f680-45e6-ba4b-1a99bd7aca10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404138136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.404138136
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3074366970
Short name T864
Test name
Test status
Simulation time 4710954462 ps
CPU time 11.77 seconds
Started Jun 24 05:54:16 PM PDT 24
Finished Jun 24 05:54:30 PM PDT 24
Peak memory 201108 kb
Host smart-5b21a58a-0226-48a6-8b0d-747b98b2e029
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074366970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3074366970
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1690572904
Short name T837
Test name
Test status
Simulation time 471089748 ps
CPU time 1.3 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:16 PM PDT 24
Peak memory 201184 kb
Host smart-25b57d4c-df4e-4da8-aafe-bcc931d533a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690572904 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1690572904
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2313165724
Short name T827
Test name
Test status
Simulation time 552831641 ps
CPU time 2.16 seconds
Started Jun 24 05:54:10 PM PDT 24
Finished Jun 24 05:54:14 PM PDT 24
Peak memory 201128 kb
Host smart-1a3b60b5-cb31-462e-b11f-3d272c66ce94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313165724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2313165724
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.715439294
Short name T812
Test name
Test status
Simulation time 388126307 ps
CPU time 1.5 seconds
Started Jun 24 05:54:17 PM PDT 24
Finished Jun 24 05:54:20 PM PDT 24
Peak memory 201116 kb
Host smart-f0dfe8d1-532f-4ac2-b004-da59a0536606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715439294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.715439294
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1001966730
Short name T146
Test name
Test status
Simulation time 2310490497 ps
CPU time 9.02 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:23 PM PDT 24
Peak memory 201164 kb
Host smart-7b0e9590-11b7-40b4-a1bd-1af081c1ad1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001966730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1001966730
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2216477462
Short name T917
Test name
Test status
Simulation time 487085092 ps
CPU time 2.33 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:17 PM PDT 24
Peak memory 201412 kb
Host smart-9dc5dd8f-fd3c-4f33-86f8-aea40397af1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216477462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2216477462
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.963164688
Short name T850
Test name
Test status
Simulation time 5079143517 ps
CPU time 3.6 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:18 PM PDT 24
Peak memory 201420 kb
Host smart-482e8c1a-6084-494d-a6bb-5d1c9f0e3c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963164688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.963164688
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3241407696
Short name T857
Test name
Test status
Simulation time 586365022 ps
CPU time 2.19 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:18 PM PDT 24
Peak memory 201188 kb
Host smart-098074a9-204e-4bb8-92ac-155ef7fc7dd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241407696 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3241407696
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.987752540
Short name T829
Test name
Test status
Simulation time 391701038 ps
CPU time 1.63 seconds
Started Jun 24 05:54:15 PM PDT 24
Finished Jun 24 05:54:18 PM PDT 24
Peak memory 201056 kb
Host smart-d315bbd0-ce40-4850-90e8-26388f63f6c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987752540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.987752540
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4214219549
Short name T854
Test name
Test status
Simulation time 319619139 ps
CPU time 0.8 seconds
Started Jun 24 05:54:15 PM PDT 24
Finished Jun 24 05:54:17 PM PDT 24
Peak memory 201112 kb
Host smart-3a7fdd04-e956-49cd-a9f4-fa2f49b44eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214219549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4214219549
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1419458324
Short name T821
Test name
Test status
Simulation time 5622311846 ps
CPU time 12.63 seconds
Started Jun 24 05:54:10 PM PDT 24
Finished Jun 24 05:54:24 PM PDT 24
Peak memory 201368 kb
Host smart-45878631-62c5-4392-b18a-875493e65778
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419458324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1419458324
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3745332913
Short name T816
Test name
Test status
Simulation time 521468513 ps
CPU time 2.05 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:16 PM PDT 24
Peak memory 201384 kb
Host smart-2e2fac6b-d774-4f60-94c7-c43fd62e2f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745332913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3745332913
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3542286859
Short name T889
Test name
Test status
Simulation time 8038088700 ps
CPU time 21.59 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 201388 kb
Host smart-d8ece709-50fc-4798-a348-2d47c7c67ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542286859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3542286859
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1304568273
Short name T817
Test name
Test status
Simulation time 542372565 ps
CPU time 2.06 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:18 PM PDT 24
Peak memory 201424 kb
Host smart-aa213bb9-048d-4165-9291-f0d33eb5e95e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304568273 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1304568273
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1902878881
Short name T130
Test name
Test status
Simulation time 580432159 ps
CPU time 1.19 seconds
Started Jun 24 05:54:12 PM PDT 24
Finished Jun 24 05:54:15 PM PDT 24
Peak memory 201088 kb
Host smart-013869a0-e8ff-4d32-ac3c-9c06cbe5f8d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902878881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1902878881
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3413024677
Short name T834
Test name
Test status
Simulation time 432682914 ps
CPU time 0.94 seconds
Started Jun 24 05:54:14 PM PDT 24
Finished Jun 24 05:54:17 PM PDT 24
Peak memory 201076 kb
Host smart-b7bfc453-d308-433b-9884-b20988c5dddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413024677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3413024677
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1337180207
Short name T818
Test name
Test status
Simulation time 5562054617 ps
CPU time 4.2 seconds
Started Jun 24 05:54:11 PM PDT 24
Finished Jun 24 05:54:16 PM PDT 24
Peak memory 201404 kb
Host smart-544699e6-ed3c-4843-a56b-636fcf7bf79e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337180207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1337180207
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2024143559
Short name T820
Test name
Test status
Simulation time 568144180 ps
CPU time 3.62 seconds
Started Jun 24 05:54:15 PM PDT 24
Finished Jun 24 05:54:20 PM PDT 24
Peak memory 210584 kb
Host smart-505aa348-2179-457a-8635-e9e02aeb6dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024143559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2024143559
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1474050060
Short name T862
Test name
Test status
Simulation time 824022140 ps
CPU time 1.15 seconds
Started Jun 24 05:54:13 PM PDT 24
Finished Jun 24 05:54:16 PM PDT 24
Peak memory 201144 kb
Host smart-8818559e-eb99-4cd0-9a02-479bf05c4608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474050060 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1474050060
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.195707567
Short name T908
Test name
Test status
Simulation time 354377223 ps
CPU time 1.16 seconds
Started Jun 24 05:54:11 PM PDT 24
Finished Jun 24 05:54:14 PM PDT 24
Peak memory 201140 kb
Host smart-17b16813-c474-4750-ad27-73d67f77eecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195707567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.195707567
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2328431721
Short name T892
Test name
Test status
Simulation time 331978607 ps
CPU time 0.81 seconds
Started Jun 24 05:54:15 PM PDT 24
Finished Jun 24 05:54:17 PM PDT 24
Peak memory 201040 kb
Host smart-fc6c00f3-4eab-4019-9d12-71f10d61bdaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328431721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2328431721
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3034620358
Short name T855
Test name
Test status
Simulation time 2542139118 ps
CPU time 2.19 seconds
Started Jun 24 05:54:16 PM PDT 24
Finished Jun 24 05:54:20 PM PDT 24
Peak memory 200900 kb
Host smart-83c361c2-df53-48df-adbe-7f79dd2d4fae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034620358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3034620358
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2346727006
Short name T869
Test name
Test status
Simulation time 782469672 ps
CPU time 3.12 seconds
Started Jun 24 05:54:10 PM PDT 24
Finished Jun 24 05:54:15 PM PDT 24
Peak memory 210604 kb
Host smart-eaa21885-f476-4b09-a7aa-ec3f0afde34f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346727006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2346727006
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4187120606
Short name T871
Test name
Test status
Simulation time 344439320 ps
CPU time 1.16 seconds
Started Jun 24 05:54:26 PM PDT 24
Finished Jun 24 05:54:29 PM PDT 24
Peak memory 201116 kb
Host smart-1180919b-29ac-4853-a4e2-d5b1debf96d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187120606 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.4187120606
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.167146143
Short name T845
Test name
Test status
Simulation time 521250658 ps
CPU time 1.34 seconds
Started Jun 24 05:54:16 PM PDT 24
Finished Jun 24 05:54:19 PM PDT 24
Peak memory 201128 kb
Host smart-5be81835-92e6-4609-ab84-6d185f71b9d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167146143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.167146143
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.466161351
Short name T874
Test name
Test status
Simulation time 385557437 ps
CPU time 0.85 seconds
Started Jun 24 05:54:14 PM PDT 24
Finished Jun 24 05:54:16 PM PDT 24
Peak memory 201044 kb
Host smart-3b120ffd-3cae-48a1-b42e-fbc4d5b117f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466161351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.466161351
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3440348996
Short name T901
Test name
Test status
Simulation time 4915648423 ps
CPU time 6.45 seconds
Started Jun 24 05:54:25 PM PDT 24
Finished Jun 24 05:54:34 PM PDT 24
Peak memory 201432 kb
Host smart-264d6ad3-1f9e-4950-9808-839590c36d76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440348996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3440348996
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.547679009
Short name T905
Test name
Test status
Simulation time 470965507 ps
CPU time 3.74 seconds
Started Jun 24 05:54:17 PM PDT 24
Finished Jun 24 05:54:22 PM PDT 24
Peak memory 200900 kb
Host smart-afaaa78d-457d-41bc-b7c1-48b1887ffb22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547679009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.547679009
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1552707752
Short name T65
Test name
Test status
Simulation time 4593309767 ps
CPU time 10.61 seconds
Started Jun 24 05:54:10 PM PDT 24
Finished Jun 24 05:54:22 PM PDT 24
Peak memory 201352 kb
Host smart-6d4251cf-5d90-4094-90c4-43f6a9bed027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552707752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1552707752
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1816711099
Short name T110
Test name
Test status
Simulation time 556923711 ps
CPU time 1.25 seconds
Started Jun 24 05:54:22 PM PDT 24
Finished Jun 24 05:54:25 PM PDT 24
Peak memory 201192 kb
Host smart-e6913a18-5727-43b3-b4f2-1641d9de7aa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816711099 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1816711099
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3264772460
Short name T897
Test name
Test status
Simulation time 363003329 ps
CPU time 1.67 seconds
Started Jun 24 05:54:22 PM PDT 24
Finished Jun 24 05:54:24 PM PDT 24
Peak memory 201124 kb
Host smart-ac2f21e3-c366-413f-ac23-113339412ac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264772460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3264772460
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.899308935
Short name T843
Test name
Test status
Simulation time 545388063 ps
CPU time 0.91 seconds
Started Jun 24 05:54:26 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 201124 kb
Host smart-d8f64bee-2897-45ec-bffb-4cf77fe81f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899308935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.899308935
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.241973129
Short name T861
Test name
Test status
Simulation time 2414761472 ps
CPU time 1.55 seconds
Started Jun 24 05:54:25 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 201164 kb
Host smart-c0234ef6-34c8-4801-8b1f-1ab3b09d44da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241973129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.241973129
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.861557120
Short name T75
Test name
Test status
Simulation time 699932947 ps
CPU time 1.65 seconds
Started Jun 24 05:54:20 PM PDT 24
Finished Jun 24 05:54:22 PM PDT 24
Peak memory 201352 kb
Host smart-2ef412cd-78eb-4c59-a264-1e0e5870b701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861557120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.861557120
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3116240628
Short name T329
Test name
Test status
Simulation time 8482568888 ps
CPU time 12.49 seconds
Started Jun 24 05:54:21 PM PDT 24
Finished Jun 24 05:54:34 PM PDT 24
Peak memory 201336 kb
Host smart-a8d85f59-b99f-45af-8bf7-dfe76aac0076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116240628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3116240628
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.309256311
Short name T135
Test name
Test status
Simulation time 1112471014 ps
CPU time 4.71 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:07 PM PDT 24
Peak memory 201312 kb
Host smart-bc6d3610-1506-4d2e-93de-5dea498a5b09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309256311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.309256311
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2565912094
Short name T61
Test name
Test status
Simulation time 26873578308 ps
CPU time 25.45 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:29 PM PDT 24
Peak memory 201360 kb
Host smart-e49e3b77-1b91-4ef9-b39e-8fa4a40867f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565912094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2565912094
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.651017941
Short name T132
Test name
Test status
Simulation time 1095023693 ps
CPU time 1.33 seconds
Started Jun 24 05:53:57 PM PDT 24
Finished Jun 24 05:54:00 PM PDT 24
Peak memory 201084 kb
Host smart-911315c6-6b25-4675-a82f-1618f4ae423f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651017941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.651017941
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.638999398
Short name T836
Test name
Test status
Simulation time 540064257 ps
CPU time 2.29 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201184 kb
Host smart-dcc8e405-cf10-42f4-926e-adba4e1398dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638999398 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.638999398
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3920692163
Short name T129
Test name
Test status
Simulation time 400172062 ps
CPU time 1.46 seconds
Started Jun 24 05:53:54 PM PDT 24
Finished Jun 24 05:53:57 PM PDT 24
Peak memory 201140 kb
Host smart-9dc10488-c396-47dd-accb-513aece8e78a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920692163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3920692163
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.26963035
Short name T915
Test name
Test status
Simulation time 305568852 ps
CPU time 1.32 seconds
Started Jun 24 05:53:55 PM PDT 24
Finished Jun 24 05:53:58 PM PDT 24
Peak memory 201108 kb
Host smart-6da40553-0400-4ecd-b459-cad4171d0ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26963035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.26963035
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2113540905
Short name T878
Test name
Test status
Simulation time 1911316176 ps
CPU time 1.6 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:04 PM PDT 24
Peak memory 201108 kb
Host smart-3f9cab61-c9da-4c76-95c7-280e49253009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113540905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2113540905
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.906517957
Short name T863
Test name
Test status
Simulation time 601565802 ps
CPU time 1.83 seconds
Started Jun 24 05:53:55 PM PDT 24
Finished Jun 24 05:53:58 PM PDT 24
Peak memory 201336 kb
Host smart-2578f8a6-a292-4c46-8fde-d3553e19ba9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906517957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.906517957
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1446768792
Short name T903
Test name
Test status
Simulation time 4836325712 ps
CPU time 4.51 seconds
Started Jun 24 05:53:59 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201332 kb
Host smart-a4946c22-0784-4e46-b718-989d2160ccef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446768792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1446768792
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.286133653
Short name T810
Test name
Test status
Simulation time 474741887 ps
CPU time 0.95 seconds
Started Jun 24 05:54:25 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 201132 kb
Host smart-2ab59d3f-5a64-488b-93b8-15375965d96a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286133653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.286133653
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.75357412
Short name T826
Test name
Test status
Simulation time 358656870 ps
CPU time 0.89 seconds
Started Jun 24 05:54:26 PM PDT 24
Finished Jun 24 05:54:29 PM PDT 24
Peak memory 201040 kb
Host smart-3bc01274-a3ad-48ab-bd26-e6c7478a827d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75357412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.75357412
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1079789253
Short name T879
Test name
Test status
Simulation time 437749751 ps
CPU time 1.09 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:27 PM PDT 24
Peak memory 201104 kb
Host smart-2a35bdf7-7e8c-489d-8a1c-7a41954c2716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079789253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1079789253
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1641663580
Short name T798
Test name
Test status
Simulation time 362382042 ps
CPU time 1.2 seconds
Started Jun 24 05:54:25 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 201108 kb
Host smart-2a422061-775c-4833-93d2-11ffda160887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641663580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1641663580
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4151526624
Short name T802
Test name
Test status
Simulation time 349336192 ps
CPU time 0.82 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:25 PM PDT 24
Peak memory 201116 kb
Host smart-25577c4f-5102-4ee3-b3bf-6e88d4d66fe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151526624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.4151526624
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2971409299
Short name T804
Test name
Test status
Simulation time 529813483 ps
CPU time 1.21 seconds
Started Jun 24 05:54:25 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 201076 kb
Host smart-82317b55-2eb1-4f9c-ac71-ecc2f3a846ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971409299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2971409299
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1685733589
Short name T800
Test name
Test status
Simulation time 414385514 ps
CPU time 1.48 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:25 PM PDT 24
Peak memory 201104 kb
Host smart-83ac63a4-13a3-456e-b9d0-11ae18fe6475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685733589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1685733589
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1176491477
Short name T803
Test name
Test status
Simulation time 493891259 ps
CPU time 1.79 seconds
Started Jun 24 05:54:22 PM PDT 24
Finished Jun 24 05:54:25 PM PDT 24
Peak memory 201116 kb
Host smart-397d29fd-cbeb-4ab7-8130-f1b88ef3bd94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176491477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1176491477
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3079629522
Short name T872
Test name
Test status
Simulation time 483915696 ps
CPU time 0.95 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:26 PM PDT 24
Peak memory 201116 kb
Host smart-9b212bcd-0c1d-42e1-821f-d943553b02e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079629522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3079629522
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4240439696
Short name T807
Test name
Test status
Simulation time 323781439 ps
CPU time 1 seconds
Started Jun 24 05:54:26 PM PDT 24
Finished Jun 24 05:54:30 PM PDT 24
Peak memory 201096 kb
Host smart-89567b2f-4daa-4063-ade4-d6ca5cc6dfd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240439696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4240439696
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.144268057
Short name T882
Test name
Test status
Simulation time 677939408 ps
CPU time 3.5 seconds
Started Jun 24 05:54:00 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201300 kb
Host smart-47b83351-f49f-49c3-ae87-17044d1f3534
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144268057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.144268057
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1827515135
Short name T136
Test name
Test status
Simulation time 20162096734 ps
CPU time 51.67 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:54 PM PDT 24
Peak memory 201376 kb
Host smart-779159fd-7df5-49ef-99bc-ee6d3f42b878
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827515135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1827515135
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.959846981
Short name T823
Test name
Test status
Simulation time 1420115973 ps
CPU time 1.23 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201112 kb
Host smart-00a87a6e-43ae-4dc9-a464-79057b874ee7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959846981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.959846981
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1670265346
Short name T111
Test name
Test status
Simulation time 613733835 ps
CPU time 1.02 seconds
Started Jun 24 05:54:00 PM PDT 24
Finished Jun 24 05:54:02 PM PDT 24
Peak memory 201176 kb
Host smart-140895d9-6d6e-4b5d-ab19-08411e2c6681
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670265346 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1670265346
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2908113931
Short name T877
Test name
Test status
Simulation time 340004884 ps
CPU time 1.66 seconds
Started Jun 24 05:53:59 PM PDT 24
Finished Jun 24 05:54:02 PM PDT 24
Peak memory 201104 kb
Host smart-d30e6726-0cac-4924-9a49-d57be30b812c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908113931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2908113931
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1862348486
Short name T875
Test name
Test status
Simulation time 339484207 ps
CPU time 0.86 seconds
Started Jun 24 05:54:00 PM PDT 24
Finished Jun 24 05:54:02 PM PDT 24
Peak memory 201116 kb
Host smart-909b4c48-751f-4e80-946b-8fd7be65c53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862348486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1862348486
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.178087170
Short name T839
Test name
Test status
Simulation time 2500371712 ps
CPU time 2.29 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201176 kb
Host smart-ed963cc3-3e0f-40b5-85cb-ffb94f9bd08d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178087170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.178087170
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2237931036
Short name T898
Test name
Test status
Simulation time 932677090 ps
CPU time 3.16 seconds
Started Jun 24 05:53:59 PM PDT 24
Finished Jun 24 05:54:03 PM PDT 24
Peak memory 217620 kb
Host smart-2c1e7d5b-3e7c-4526-a19c-d4dda20386af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237931036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2237931036
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3373341954
Short name T79
Test name
Test status
Simulation time 8605790295 ps
CPU time 20.25 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:24 PM PDT 24
Peak memory 201364 kb
Host smart-d32fc654-a7f9-49bd-9452-ade7138d59d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373341954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3373341954
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2629377354
Short name T886
Test name
Test status
Simulation time 560633991 ps
CPU time 0.95 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:25 PM PDT 24
Peak memory 201116 kb
Host smart-95ae29ec-acf7-4d67-9948-41d43e7b3ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629377354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2629377354
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3604208014
Short name T899
Test name
Test status
Simulation time 335141262 ps
CPU time 0.85 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 201120 kb
Host smart-e2383e08-259c-4660-bd43-79b1f20d8904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604208014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3604208014
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3434987778
Short name T891
Test name
Test status
Simulation time 482724998 ps
CPU time 0.79 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:26 PM PDT 24
Peak memory 201116 kb
Host smart-f68b0b2c-7ceb-499d-bdd4-a0ea791e5079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434987778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3434987778
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1042244244
Short name T833
Test name
Test status
Simulation time 595391524 ps
CPU time 0.74 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:25 PM PDT 24
Peak memory 201096 kb
Host smart-b10cfc28-0bd7-44c1-968d-7b8d15fd0c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042244244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1042244244
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2845317072
Short name T840
Test name
Test status
Simulation time 533579153 ps
CPU time 1.03 seconds
Started Jun 24 05:54:21 PM PDT 24
Finished Jun 24 05:54:23 PM PDT 24
Peak memory 201108 kb
Host smart-54f5c5f2-9a59-4252-b5a8-78b423d9f532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845317072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2845317072
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2508951000
Short name T835
Test name
Test status
Simulation time 511097539 ps
CPU time 1.73 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:26 PM PDT 24
Peak memory 201108 kb
Host smart-2b8cf129-685c-4f2d-aae6-e70460afb347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508951000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2508951000
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2969317358
Short name T868
Test name
Test status
Simulation time 700481701 ps
CPU time 0.71 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:26 PM PDT 24
Peak memory 201116 kb
Host smart-5fccd009-de16-4a8e-946f-629bb1a3d448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969317358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2969317358
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3945667663
Short name T916
Test name
Test status
Simulation time 536917463 ps
CPU time 0.94 seconds
Started Jun 24 05:54:26 PM PDT 24
Finished Jun 24 05:54:29 PM PDT 24
Peak memory 201112 kb
Host smart-02a19288-9022-4be5-b3e3-2a746d87241d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945667663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3945667663
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2167586196
Short name T873
Test name
Test status
Simulation time 558765067 ps
CPU time 0.98 seconds
Started Jun 24 05:54:26 PM PDT 24
Finished Jun 24 05:54:29 PM PDT 24
Peak memory 201100 kb
Host smart-2b9203fc-1012-460e-abb3-532ea8d37580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167586196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2167586196
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.711415781
Short name T799
Test name
Test status
Simulation time 396527950 ps
CPU time 1.49 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:26 PM PDT 24
Peak memory 201096 kb
Host smart-8ac5216d-5f92-4056-b623-27521764e8fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711415781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.711415781
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3889136380
Short name T134
Test name
Test status
Simulation time 947875592 ps
CPU time 1.62 seconds
Started Jun 24 05:54:00 PM PDT 24
Finished Jun 24 05:54:03 PM PDT 24
Peak memory 201312 kb
Host smart-a62abb7e-7a1c-4685-b7df-625fa3bf7495
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889136380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3889136380
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3221192503
Short name T131
Test name
Test status
Simulation time 11207197514 ps
CPU time 25.84 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 201360 kb
Host smart-73811af5-b070-480f-9749-24b02ec3d5c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221192503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3221192503
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1084839718
Short name T814
Test name
Test status
Simulation time 1127152477 ps
CPU time 3.42 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:07 PM PDT 24
Peak memory 201132 kb
Host smart-4532ea14-91ac-4788-977c-8f8cfc29a063
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084839718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1084839718
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.713482115
Short name T78
Test name
Test status
Simulation time 494959010 ps
CPU time 1.07 seconds
Started Jun 24 05:54:08 PM PDT 24
Finished Jun 24 05:54:11 PM PDT 24
Peak memory 201188 kb
Host smart-0dc22078-159f-461b-a41c-1a2f45dbbc7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713482115 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.713482115
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3853333131
Short name T867
Test name
Test status
Simulation time 578430232 ps
CPU time 1 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201092 kb
Host smart-52855dbf-c16f-4340-a20f-552a4cba6c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853333131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3853333131
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4054705704
Short name T806
Test name
Test status
Simulation time 568211626 ps
CPU time 0.88 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201120 kb
Host smart-eda9df71-f557-4992-9efd-7e1c69d179d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054705704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4054705704
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.928328243
Short name T145
Test name
Test status
Simulation time 1957058495 ps
CPU time 2.83 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:07 PM PDT 24
Peak memory 201128 kb
Host smart-3d5ab5b8-3854-42af-8bab-7cf7afe3c3e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928328243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.928328243
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2454529708
Short name T326
Test name
Test status
Simulation time 4221046029 ps
CPU time 8.28 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:10 PM PDT 24
Peak memory 201396 kb
Host smart-3ddcd3c0-2535-4e43-a6ed-db67f7deb071
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454529708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2454529708
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2513260082
Short name T912
Test name
Test status
Simulation time 322797464 ps
CPU time 1.47 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:26 PM PDT 24
Peak memory 201116 kb
Host smart-22a97e76-25c1-4c0e-a048-c7458fed4599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513260082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2513260082
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.733200912
Short name T906
Test name
Test status
Simulation time 462393856 ps
CPU time 1.63 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 201104 kb
Host smart-c3e1a6a5-a9c4-485f-a5b8-e8f67245d484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733200912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.733200912
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2148636406
Short name T808
Test name
Test status
Simulation time 302806450 ps
CPU time 0.81 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:27 PM PDT 24
Peak memory 201080 kb
Host smart-0117829a-a95f-46c0-b53e-6027b6e39f0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148636406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2148636406
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2867909766
Short name T904
Test name
Test status
Simulation time 346089203 ps
CPU time 1.34 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:27 PM PDT 24
Peak memory 201104 kb
Host smart-5be3f067-4a47-437c-812d-7792800d95af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867909766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2867909766
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2095829734
Short name T896
Test name
Test status
Simulation time 368573681 ps
CPU time 1.44 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:26 PM PDT 24
Peak memory 201096 kb
Host smart-3ba28dc1-d6c9-49fc-ae81-1fedca193005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095829734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2095829734
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.819250464
Short name T913
Test name
Test status
Simulation time 446026232 ps
CPU time 1.56 seconds
Started Jun 24 05:54:25 PM PDT 24
Finished Jun 24 05:54:29 PM PDT 24
Peak memory 201108 kb
Host smart-3cf7e3c3-bf75-44af-a529-132162f812c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819250464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.819250464
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.836528492
Short name T848
Test name
Test status
Simulation time 342832490 ps
CPU time 0.78 seconds
Started Jun 24 05:54:21 PM PDT 24
Finished Jun 24 05:54:23 PM PDT 24
Peak memory 201100 kb
Host smart-8a35d8a7-bb1c-4306-a261-05d9074d0508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836528492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.836528492
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.762954439
Short name T822
Test name
Test status
Simulation time 519656007 ps
CPU time 0.74 seconds
Started Jun 24 05:54:23 PM PDT 24
Finished Jun 24 05:54:26 PM PDT 24
Peak memory 201112 kb
Host smart-a339056d-abef-4781-afda-147b872df57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762954439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.762954439
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.982617046
Short name T801
Test name
Test status
Simulation time 334746165 ps
CPU time 1.37 seconds
Started Jun 24 05:54:25 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 201116 kb
Host smart-2db871c8-af17-49da-b1a5-6f1760e7de6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982617046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.982617046
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3048928813
Short name T797
Test name
Test status
Simulation time 505266138 ps
CPU time 0.93 seconds
Started Jun 24 05:54:27 PM PDT 24
Finished Jun 24 05:54:31 PM PDT 24
Peak memory 201116 kb
Host smart-50072710-fc09-4c20-ac54-c524d30acbef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048928813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3048928813
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3644331695
Short name T849
Test name
Test status
Simulation time 571300607 ps
CPU time 1.17 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:04 PM PDT 24
Peak memory 201188 kb
Host smart-c35de164-a535-4efa-98f3-32885cb5608d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644331695 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3644331695
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4059504051
Short name T853
Test name
Test status
Simulation time 557435888 ps
CPU time 1.02 seconds
Started Jun 24 05:54:00 PM PDT 24
Finished Jun 24 05:54:02 PM PDT 24
Peak memory 201100 kb
Host smart-50650484-4c67-4903-bba8-c1daf2f23467
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059504051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4059504051
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2261193462
Short name T819
Test name
Test status
Simulation time 413953794 ps
CPU time 0.77 seconds
Started Jun 24 05:54:00 PM PDT 24
Finished Jun 24 05:54:03 PM PDT 24
Peak memory 201136 kb
Host smart-d06611e3-5a4a-4c21-8bf2-deacff1dc87f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261193462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2261193462
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3340702391
Short name T59
Test name
Test status
Simulation time 4459826098 ps
CPU time 13.91 seconds
Started Jun 24 05:54:04 PM PDT 24
Finished Jun 24 05:54:19 PM PDT 24
Peak memory 201404 kb
Host smart-2a489837-1794-4015-a726-8569fbc5a314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340702391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3340702391
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.546183531
Short name T851
Test name
Test status
Simulation time 698234826 ps
CPU time 2.4 seconds
Started Jun 24 05:54:07 PM PDT 24
Finished Jun 24 05:54:11 PM PDT 24
Peak memory 201340 kb
Host smart-8845f7d8-9f5f-45a5-8674-49c739e1f1ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546183531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.546183531
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4000580318
Short name T920
Test name
Test status
Simulation time 8573350766 ps
CPU time 5.6 seconds
Started Jun 24 05:54:03 PM PDT 24
Finished Jun 24 05:54:10 PM PDT 24
Peak memory 201372 kb
Host smart-fd59a8ec-e38d-4afe-8a6a-95b871a5cffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000580318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4000580318
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.260454177
Short name T846
Test name
Test status
Simulation time 636665100 ps
CPU time 1.21 seconds
Started Jun 24 05:54:03 PM PDT 24
Finished Jun 24 05:54:06 PM PDT 24
Peak memory 201172 kb
Host smart-766273d8-f59d-4a96-aab9-a50d47c9848f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260454177 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.260454177
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3426938113
Short name T909
Test name
Test status
Simulation time 508401394 ps
CPU time 1.41 seconds
Started Jun 24 05:54:09 PM PDT 24
Finished Jun 24 05:54:12 PM PDT 24
Peak memory 201120 kb
Host smart-1cbaca7b-76a1-4fac-b0e8-4a82913eefd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426938113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3426938113
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2380086659
Short name T815
Test name
Test status
Simulation time 408398459 ps
CPU time 1 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201124 kb
Host smart-10fdae6b-3a56-43fb-84b5-17c57ccc07cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380086659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2380086659
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1413019405
Short name T831
Test name
Test status
Simulation time 2572602559 ps
CPU time 2.92 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:07 PM PDT 24
Peak memory 201180 kb
Host smart-a5e47c97-bd42-4787-bad2-24c5340e4289
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413019405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1413019405
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.580676213
Short name T907
Test name
Test status
Simulation time 614297518 ps
CPU time 2.55 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:06 PM PDT 24
Peak memory 217716 kb
Host smart-c8fb4078-ea4f-4ff2-8222-6af2246f188f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580676213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.580676213
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2734376812
Short name T64
Test name
Test status
Simulation time 11048958000 ps
CPU time 3.8 seconds
Started Jun 24 05:54:03 PM PDT 24
Finished Jun 24 05:54:09 PM PDT 24
Peak memory 201368 kb
Host smart-081b0a30-d90d-4dfa-86f8-27ccc6d6c9c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734376812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2734376812
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.100823162
Short name T914
Test name
Test status
Simulation time 596929727 ps
CPU time 2.31 seconds
Started Jun 24 05:54:04 PM PDT 24
Finished Jun 24 05:54:08 PM PDT 24
Peak memory 201176 kb
Host smart-f5e47d74-ccc2-4f65-a028-9d3cd0988aef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100823162 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.100823162
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3575267168
Short name T62
Test name
Test status
Simulation time 566182423 ps
CPU time 2.11 seconds
Started Jun 24 05:54:06 PM PDT 24
Finished Jun 24 05:54:09 PM PDT 24
Peak memory 201100 kb
Host smart-62c8ed96-4f57-4f77-a61c-510ec69c9de3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575267168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3575267168
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3547152102
Short name T890
Test name
Test status
Simulation time 330187328 ps
CPU time 0.98 seconds
Started Jun 24 05:54:06 PM PDT 24
Finished Jun 24 05:54:08 PM PDT 24
Peak memory 201084 kb
Host smart-392766cb-a3bc-45e0-9c6e-3d0a3823b025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547152102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3547152102
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3169331051
Short name T830
Test name
Test status
Simulation time 5171600604 ps
CPU time 2.95 seconds
Started Jun 24 05:54:06 PM PDT 24
Finished Jun 24 05:54:10 PM PDT 24
Peak memory 201360 kb
Host smart-d2619b4a-d9ff-4b38-a99f-5f7b05b2174b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169331051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3169331051
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3539593096
Short name T838
Test name
Test status
Simulation time 552909929 ps
CPU time 1.38 seconds
Started Jun 24 05:54:04 PM PDT 24
Finished Jun 24 05:54:07 PM PDT 24
Peak memory 201140 kb
Host smart-3ef3f250-595c-4622-b38d-68b538107a24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539593096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3539593096
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1028535801
Short name T327
Test name
Test status
Simulation time 8519869085 ps
CPU time 19.84 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:24 PM PDT 24
Peak memory 201384 kb
Host smart-43bf10ac-0628-42b8-90f9-27f8e7f91620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028535801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1028535801
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.510580182
Short name T893
Test name
Test status
Simulation time 560543416 ps
CPU time 1.55 seconds
Started Jun 24 05:54:04 PM PDT 24
Finished Jun 24 05:54:07 PM PDT 24
Peak memory 209608 kb
Host smart-b70fa2e3-f333-49de-9176-4d63623464c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510580182 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.510580182
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.616156605
Short name T133
Test name
Test status
Simulation time 355678211 ps
CPU time 0.98 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:05 PM PDT 24
Peak memory 201120 kb
Host smart-1d72dafe-e586-43a3-9d5a-37b4cbce0dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616156605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.616156605
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3421653790
Short name T824
Test name
Test status
Simulation time 472083686 ps
CPU time 1.73 seconds
Started Jun 24 05:54:11 PM PDT 24
Finished Jun 24 05:54:14 PM PDT 24
Peak memory 201060 kb
Host smart-099147d0-89a5-463a-a19b-e7cb21075dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421653790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3421653790
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4266523066
Short name T141
Test name
Test status
Simulation time 2441405731 ps
CPU time 5.96 seconds
Started Jun 24 05:54:03 PM PDT 24
Finished Jun 24 05:54:11 PM PDT 24
Peak memory 201176 kb
Host smart-253aaa93-41d1-431e-8032-26b5c708ce95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266523066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.4266523066
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1269864446
Short name T885
Test name
Test status
Simulation time 507855885 ps
CPU time 2.04 seconds
Started Jun 24 05:54:11 PM PDT 24
Finished Jun 24 05:54:14 PM PDT 24
Peak memory 209556 kb
Host smart-76cdce84-defc-451b-b447-f7293166349c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269864446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1269864446
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.424967031
Short name T888
Test name
Test status
Simulation time 3832727508 ps
CPU time 6.37 seconds
Started Jun 24 05:54:01 PM PDT 24
Finished Jun 24 05:54:09 PM PDT 24
Peak memory 201352 kb
Host smart-ccfca8fd-57e7-49eb-8f65-89ae81f59c15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424967031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.424967031
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3929990631
Short name T847
Test name
Test status
Simulation time 521844488 ps
CPU time 2.01 seconds
Started Jun 24 05:54:04 PM PDT 24
Finished Jun 24 05:54:07 PM PDT 24
Peak memory 201176 kb
Host smart-bba0badb-f5f5-4385-9384-a28bbf908bd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929990631 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3929990631
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.532687491
Short name T140
Test name
Test status
Simulation time 451224846 ps
CPU time 1.82 seconds
Started Jun 24 05:54:03 PM PDT 24
Finished Jun 24 05:54:06 PM PDT 24
Peak memory 201132 kb
Host smart-9edced8c-61bd-403b-9260-91d5ad56a2be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532687491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.532687491
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1075256729
Short name T866
Test name
Test status
Simulation time 499107813 ps
CPU time 0.9 seconds
Started Jun 24 05:54:10 PM PDT 24
Finished Jun 24 05:54:12 PM PDT 24
Peak memory 201116 kb
Host smart-9f572d66-635f-4d13-8e1b-a5dde6c14ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075256729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1075256729
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1698848463
Short name T142
Test name
Test status
Simulation time 5355391178 ps
CPU time 20.62 seconds
Started Jun 24 05:54:11 PM PDT 24
Finished Jun 24 05:54:33 PM PDT 24
Peak memory 201324 kb
Host smart-9e948914-a239-4280-b2a9-f512f0df6d84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698848463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1698848463
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2016943279
Short name T112
Test name
Test status
Simulation time 411222195 ps
CPU time 2.98 seconds
Started Jun 24 05:54:02 PM PDT 24
Finished Jun 24 05:54:07 PM PDT 24
Peak memory 201424 kb
Host smart-e18a9109-a8a0-43e3-913f-5f27277751e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016943279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2016943279
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1738745238
Short name T841
Test name
Test status
Simulation time 9127116835 ps
CPU time 23.69 seconds
Started Jun 24 05:54:03 PM PDT 24
Finished Jun 24 05:54:29 PM PDT 24
Peak memory 201380 kb
Host smart-ca7b2589-5bed-449b-b34a-7c03ce3f07b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738745238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1738745238
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.219491283
Short name T672
Test name
Test status
Simulation time 355501197 ps
CPU time 1.48 seconds
Started Jun 24 05:55:12 PM PDT 24
Finished Jun 24 05:55:15 PM PDT 24
Peak memory 201904 kb
Host smart-bb837f28-8d60-4b14-88ba-07f95633a401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219491283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.219491283
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1168437683
Short name T290
Test name
Test status
Simulation time 174285703051 ps
CPU time 69.4 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 05:56:20 PM PDT 24
Peak memory 201720 kb
Host smart-cc86d953-50f6-44d3-8312-483e5d03c556
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168437683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1168437683
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1760805708
Short name T166
Test name
Test status
Simulation time 371835949888 ps
CPU time 108.62 seconds
Started Jun 24 05:55:10 PM PDT 24
Finished Jun 24 05:57:00 PM PDT 24
Peak memory 202220 kb
Host smart-66fcfc1e-5564-4cfb-89c4-23879b9b9460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760805708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1760805708
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1193089437
Short name T198
Test name
Test status
Simulation time 328556695226 ps
CPU time 181.21 seconds
Started Jun 24 05:55:03 PM PDT 24
Finished Jun 24 05:58:08 PM PDT 24
Peak memory 202204 kb
Host smart-fba2b4bb-a16d-4b41-940a-b9d39cf983dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193089437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1193089437
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1658170694
Short name T650
Test name
Test status
Simulation time 329268321633 ps
CPU time 222.39 seconds
Started Jun 24 05:55:04 PM PDT 24
Finished Jun 24 05:58:49 PM PDT 24
Peak memory 202244 kb
Host smart-e03367db-781a-4afb-902a-403e04484b7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658170694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1658170694
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1490976582
Short name T604
Test name
Test status
Simulation time 325407077580 ps
CPU time 681.98 seconds
Started Jun 24 05:55:04 PM PDT 24
Finished Jun 24 06:06:30 PM PDT 24
Peak memory 202200 kb
Host smart-09004be4-96d6-46ca-ba76-0d3f38f8ba13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490976582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1490976582
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.826382158
Short name T394
Test name
Test status
Simulation time 491770350755 ps
CPU time 1122.07 seconds
Started Jun 24 05:55:02 PM PDT 24
Finished Jun 24 06:13:47 PM PDT 24
Peak memory 202164 kb
Host smart-eb385f32-17c8-4140-91aa-86a0a46ad7d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=826382158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.826382158
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.8405914
Short name T243
Test name
Test status
Simulation time 558357000125 ps
CPU time 356.8 seconds
Started Jun 24 05:55:03 PM PDT 24
Finished Jun 24 06:01:02 PM PDT 24
Peak memory 202196 kb
Host smart-a44f3675-5483-4db0-8593-805303a63236
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8405914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wak
eup.8405914
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.708783108
Short name T407
Test name
Test status
Simulation time 201340177016 ps
CPU time 233.74 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 05:59:04 PM PDT 24
Peak memory 201608 kb
Host smart-243f76f0-edc8-403d-942d-1969dd4e541f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708783108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.708783108
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1198916044
Short name T122
Test name
Test status
Simulation time 103657818847 ps
CPU time 347.97 seconds
Started Jun 24 05:55:03 PM PDT 24
Finished Jun 24 06:00:54 PM PDT 24
Peak memory 202428 kb
Host smart-96f606af-2c2b-439f-92e5-445ed4befcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198916044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1198916044
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1315635993
Short name T398
Test name
Test status
Simulation time 44198003652 ps
CPU time 47.13 seconds
Started Jun 24 05:55:12 PM PDT 24
Finished Jun 24 05:56:02 PM PDT 24
Peak memory 202020 kb
Host smart-e5b8d6e7-20f7-4ca0-bec8-aee7f87dc43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315635993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1315635993
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1616352748
Short name T794
Test name
Test status
Simulation time 4170636911 ps
CPU time 2.7 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 05:55:13 PM PDT 24
Peak memory 202012 kb
Host smart-634ef058-f485-4049-8e4b-d8efb66ecbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616352748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1616352748
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.245847885
Short name T72
Test name
Test status
Simulation time 8224307592 ps
CPU time 5.49 seconds
Started Jun 24 05:55:10 PM PDT 24
Finished Jun 24 05:55:18 PM PDT 24
Peak memory 218792 kb
Host smart-aa7973a4-129a-4a21-95b5-05c935a7d585
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245847885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.245847885
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1583672790
Short name T489
Test name
Test status
Simulation time 5660767332 ps
CPU time 6.1 seconds
Started Jun 24 05:55:03 PM PDT 24
Finished Jun 24 05:55:13 PM PDT 24
Peak memory 202000 kb
Host smart-e9cc58dd-3b24-4ef6-93fd-171447c59d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583672790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1583672790
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.4256243683
Short name T724
Test name
Test status
Simulation time 111887376144 ps
CPU time 438.17 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 06:02:29 PM PDT 24
Peak memory 210796 kb
Host smart-07929836-a43c-47f3-bde0-2a4217fff220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256243683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
4256243683
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2301002955
Short name T47
Test name
Test status
Simulation time 376182175238 ps
CPU time 293.15 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:59:55 PM PDT 24
Peak memory 211856 kb
Host smart-485c37a2-1c6d-4e6a-b9c1-f4b9ddfb47cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301002955 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2301002955
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1276948695
Short name T572
Test name
Test status
Simulation time 375555030 ps
CPU time 1.56 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 05:55:12 PM PDT 24
Peak memory 201908 kb
Host smart-43adfce0-cbff-42b9-90b4-0cb47a24f883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276948695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1276948695
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3736601505
Short name T202
Test name
Test status
Simulation time 552542162697 ps
CPU time 180.14 seconds
Started Jun 24 05:55:10 PM PDT 24
Finished Jun 24 05:58:12 PM PDT 24
Peak memory 202260 kb
Host smart-41ec08e2-0ce8-4b1d-ad8e-03331311c2f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736601505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3736601505
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1389211801
Short name T469
Test name
Test status
Simulation time 500704052758 ps
CPU time 250.05 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:59:23 PM PDT 24
Peak memory 202228 kb
Host smart-40a85816-a5fd-4b48-a862-a6ad3fe74634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389211801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1389211801
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.4242215179
Short name T723
Test name
Test status
Simulation time 339511117356 ps
CPU time 368.09 seconds
Started Jun 24 05:55:14 PM PDT 24
Finished Jun 24 06:01:24 PM PDT 24
Peak memory 202204 kb
Host smart-4187d8e3-ddb4-400c-aae4-dc40c0094f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242215179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.4242215179
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.947392995
Short name T39
Test name
Test status
Simulation time 165195073368 ps
CPU time 396.64 seconds
Started Jun 24 05:55:10 PM PDT 24
Finished Jun 24 06:01:49 PM PDT 24
Peak memory 202288 kb
Host smart-e30e87e1-317e-4b97-bb79-a7268bbb4b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947392995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.947392995
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2249956887
Short name T452
Test name
Test status
Simulation time 494286000038 ps
CPU time 278.28 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:59:51 PM PDT 24
Peak memory 202236 kb
Host smart-e3aaf3ba-636a-43d5-a6e3-4fb8706ec1e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249956887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2249956887
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3204117628
Short name T247
Test name
Test status
Simulation time 454924107888 ps
CPU time 636.24 seconds
Started Jun 24 05:55:14 PM PDT 24
Finished Jun 24 06:05:52 PM PDT 24
Peak memory 202192 kb
Host smart-851d180c-589a-4c17-96a9-593173a28a83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204117628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3204117628
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3128971153
Short name T596
Test name
Test status
Simulation time 390647404633 ps
CPU time 143.95 seconds
Started Jun 24 05:55:07 PM PDT 24
Finished Jun 24 05:57:33 PM PDT 24
Peak memory 202176 kb
Host smart-8dbbf07b-2b6f-4f1d-bedf-b06235b9422f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128971153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3128971153
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2105552567
Short name T529
Test name
Test status
Simulation time 89661763303 ps
CPU time 467.27 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 06:02:58 PM PDT 24
Peak memory 202488 kb
Host smart-dacc68ed-7bbf-4600-bff5-8b5e72d74459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105552567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2105552567
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.136383105
Short name T342
Test name
Test status
Simulation time 28600283156 ps
CPU time 64.8 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:56:18 PM PDT 24
Peak memory 202008 kb
Host smart-44ac5ed9-495b-4ce1-b974-db29ac0e6303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136383105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.136383105
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.4159671725
Short name T701
Test name
Test status
Simulation time 3629772476 ps
CPU time 2.83 seconds
Started Jun 24 05:55:15 PM PDT 24
Finished Jun 24 05:55:19 PM PDT 24
Peak memory 201940 kb
Host smart-72e6e882-8309-4279-a1b9-026d03227dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159671725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.4159671725
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.845142366
Short name T82
Test name
Test status
Simulation time 5050011850 ps
CPU time 4.72 seconds
Started Jun 24 05:55:13 PM PDT 24
Finished Jun 24 05:55:20 PM PDT 24
Peak memory 217732 kb
Host smart-6bc77bc1-34cd-43c8-84ae-6cc78d204aea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845142366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.845142366
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3981601602
Short name T787
Test name
Test status
Simulation time 5937426390 ps
CPU time 8.37 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:55:22 PM PDT 24
Peak memory 202036 kb
Host smart-d9c50abf-0ccc-41fa-b916-3895e5b1a7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981601602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3981601602
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3429743775
Short name T245
Test name
Test status
Simulation time 195704102535 ps
CPU time 111.79 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:57:05 PM PDT 24
Peak memory 202224 kb
Host smart-f6e44286-9c52-494b-96a2-5380c464eaba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429743775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3429743775
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1058584058
Short name T626
Test name
Test status
Simulation time 515318983 ps
CPU time 1.38 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 05:55:45 PM PDT 24
Peak memory 201908 kb
Host smart-8ea695c5-c43f-4dc6-8596-fed22fe74566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058584058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1058584058
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3439385171
Short name T559
Test name
Test status
Simulation time 174824749809 ps
CPU time 104.1 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 05:57:25 PM PDT 24
Peak memory 202176 kb
Host smart-5024bc65-711d-4ea2-a95f-7cd2d1657e24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439385171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3439385171
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.976101173
Short name T310
Test name
Test status
Simulation time 532343475336 ps
CPU time 1228 seconds
Started Jun 24 05:55:39 PM PDT 24
Finished Jun 24 06:16:08 PM PDT 24
Peak memory 202200 kb
Host smart-3ef25695-f579-4bdf-a077-75771019dbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976101173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.976101173
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3824474965
Short name T391
Test name
Test status
Simulation time 162108747435 ps
CPU time 88.3 seconds
Started Jun 24 05:55:33 PM PDT 24
Finished Jun 24 05:57:02 PM PDT 24
Peak memory 202224 kb
Host smart-8be73723-a5db-48d9-ab9f-6cc0b8bfb540
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824474965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3824474965
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1111844483
Short name T211
Test name
Test status
Simulation time 162241919528 ps
CPU time 98.04 seconds
Started Jun 24 05:55:36 PM PDT 24
Finished Jun 24 05:57:15 PM PDT 24
Peak memory 202208 kb
Host smart-bd6fa81e-fd65-4856-b055-c3ac65383148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111844483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1111844483
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2186354292
Short name T666
Test name
Test status
Simulation time 333016448476 ps
CPU time 432.78 seconds
Started Jun 24 05:55:30 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 202252 kb
Host smart-dac83f4d-1eea-4586-8494-fb9d3085d350
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186354292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2186354292
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2246023096
Short name T162
Test name
Test status
Simulation time 476723386154 ps
CPU time 521.68 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 06:04:15 PM PDT 24
Peak memory 202276 kb
Host smart-9783359b-c553-405a-8075-bc96d952062f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246023096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2246023096
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3759120606
Short name T540
Test name
Test status
Simulation time 206267847570 ps
CPU time 129.51 seconds
Started Jun 24 05:55:30 PM PDT 24
Finished Jun 24 05:57:41 PM PDT 24
Peak memory 202176 kb
Host smart-68a79115-2a6c-4ce6-8362-84acfb6f67ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759120606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3759120606
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.287581654
Short name T215
Test name
Test status
Simulation time 133921442787 ps
CPU time 557.94 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 06:05:01 PM PDT 24
Peak memory 202440 kb
Host smart-57587782-2087-4af2-954a-3c530dc4ff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287581654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.287581654
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.224593605
Short name T340
Test name
Test status
Simulation time 43164401887 ps
CPU time 61.67 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 05:56:43 PM PDT 24
Peak memory 202020 kb
Host smart-d77a2093-f401-4593-a1ea-c06f4ff0af06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224593605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.224593605
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3977064500
Short name T740
Test name
Test status
Simulation time 3954680762 ps
CPU time 9.92 seconds
Started Jun 24 05:55:43 PM PDT 24
Finished Jun 24 05:55:54 PM PDT 24
Peak memory 202008 kb
Host smart-4ebab810-e21a-4d58-8478-63775c0c57c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977064500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3977064500
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2133217008
Short name T639
Test name
Test status
Simulation time 6054614672 ps
CPU time 7.28 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:55:36 PM PDT 24
Peak memory 202272 kb
Host smart-f6466355-81eb-44c8-ad55-a888d2fbe8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133217008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2133217008
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3174004369
Short name T735
Test name
Test status
Simulation time 61192479508 ps
CPU time 52.38 seconds
Started Jun 24 05:55:41 PM PDT 24
Finished Jun 24 05:56:35 PM PDT 24
Peak memory 210884 kb
Host smart-260c33c1-cbd1-406c-8213-12802cd75ad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174004369 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3174004369
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.136013260
Short name T163
Test name
Test status
Simulation time 538981439235 ps
CPU time 352.98 seconds
Started Jun 24 05:55:48 PM PDT 24
Finished Jun 24 06:01:42 PM PDT 24
Peak memory 202224 kb
Host smart-19b7de63-4cfe-49e4-a808-41abe3fc3f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136013260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.136013260
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2731545545
Short name T571
Test name
Test status
Simulation time 494776112994 ps
CPU time 594.41 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 06:05:35 PM PDT 24
Peak memory 202292 kb
Host smart-23d34317-a1be-49fe-9c57-c057cd6a70ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731545545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2731545545
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3448683740
Short name T378
Test name
Test status
Simulation time 492696057566 ps
CPU time 1158.79 seconds
Started Jun 24 05:55:44 PM PDT 24
Finished Jun 24 06:15:03 PM PDT 24
Peak memory 202260 kb
Host smart-7fbc6532-75f7-47f5-bffe-39b22b3feace
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448683740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3448683740
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3294829287
Short name T732
Test name
Test status
Simulation time 319396003894 ps
CPU time 194.41 seconds
Started Jun 24 05:55:43 PM PDT 24
Finished Jun 24 05:58:59 PM PDT 24
Peak memory 202200 kb
Host smart-0a3af006-39d5-4113-9dfc-5782318d80e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294829287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3294829287
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1129982025
Short name T387
Test name
Test status
Simulation time 493181360403 ps
CPU time 292.14 seconds
Started Jun 24 05:55:41 PM PDT 24
Finished Jun 24 06:00:34 PM PDT 24
Peak memory 202148 kb
Host smart-392b2534-65ec-4c60-94bf-26ba15e47589
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129982025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1129982025
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1312507228
Short name T761
Test name
Test status
Simulation time 592243163381 ps
CPU time 88.85 seconds
Started Jun 24 05:55:44 PM PDT 24
Finished Jun 24 05:57:14 PM PDT 24
Peak memory 202160 kb
Host smart-5548827b-fda7-47a7-9e6b-771d5dfd7c23
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312507228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1312507228
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.260361521
Short name T676
Test name
Test status
Simulation time 35936066761 ps
CPU time 83.11 seconds
Started Jun 24 05:55:44 PM PDT 24
Finished Jun 24 05:57:08 PM PDT 24
Peak memory 201996 kb
Host smart-c63f8782-3bb0-4d51-ac66-bbf133f38225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260361521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.260361521
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2308996464
Short name T564
Test name
Test status
Simulation time 5356811265 ps
CPU time 3.35 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 05:55:47 PM PDT 24
Peak memory 201952 kb
Host smart-b6bc9aec-6b8b-4e4d-9157-d9119fc60a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308996464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2308996464
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3351932411
Short name T351
Test name
Test status
Simulation time 5634099424 ps
CPU time 13.12 seconds
Started Jun 24 05:55:48 PM PDT 24
Finished Jun 24 05:56:01 PM PDT 24
Peak memory 202008 kb
Host smart-b8530185-247d-40b7-8b17-0ac5ae3c2425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351932411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3351932411
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3360757824
Short name T32
Test name
Test status
Simulation time 336651546122 ps
CPU time 294.66 seconds
Started Jun 24 05:55:44 PM PDT 24
Finished Jun 24 06:00:40 PM PDT 24
Peak memory 210852 kb
Host smart-3e3c4eaf-0b5f-461e-8373-2b4ddb59be33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360757824 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3360757824
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3214491584
Short name T729
Test name
Test status
Simulation time 421081123 ps
CPU time 0.86 seconds
Started Jun 24 05:55:41 PM PDT 24
Finished Jun 24 05:55:43 PM PDT 24
Peak memory 201904 kb
Host smart-e1e12268-e0ef-4a60-82d5-0515811e1558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214491584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3214491584
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1376169537
Short name T184
Test name
Test status
Simulation time 373801061703 ps
CPU time 101.26 seconds
Started Jun 24 05:55:41 PM PDT 24
Finished Jun 24 05:57:24 PM PDT 24
Peak memory 202276 kb
Host smart-61106f62-d5cc-486d-9fff-116a1e370f69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376169537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1376169537
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3964072220
Short name T312
Test name
Test status
Simulation time 164415485178 ps
CPU time 380.5 seconds
Started Jun 24 05:55:43 PM PDT 24
Finished Jun 24 06:02:05 PM PDT 24
Peak memory 202220 kb
Host smart-89c43ee4-e7d9-48a5-8527-162f592a71d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964072220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3964072220
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3518645873
Short name T574
Test name
Test status
Simulation time 165463192572 ps
CPU time 372.16 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 06:01:54 PM PDT 24
Peak memory 202136 kb
Host smart-aa640bfb-ae42-4d05-a887-54f35cd7bb5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518645873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3518645873
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2109862879
Short name T505
Test name
Test status
Simulation time 493761779782 ps
CPU time 1059.45 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 06:13:23 PM PDT 24
Peak memory 202212 kb
Host smart-d14bf2ea-ba0f-42fa-b2f1-90a871a9ff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109862879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2109862879
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2491145310
Short name T175
Test name
Test status
Simulation time 166896291717 ps
CPU time 96.85 seconds
Started Jun 24 05:55:41 PM PDT 24
Finished Jun 24 05:57:19 PM PDT 24
Peak memory 202172 kb
Host smart-3f2b6000-0d45-4f2f-896a-3dd331686c5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491145310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2491145310
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1555661363
Short name T320
Test name
Test status
Simulation time 625018335179 ps
CPU time 762.36 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 06:08:23 PM PDT 24
Peak memory 202256 kb
Host smart-a52ba72c-e164-4beb-a0e4-d4e6b268a22c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555661363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1555661363
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3222723431
Short name T193
Test name
Test status
Simulation time 377758387203 ps
CPU time 232.98 seconds
Started Jun 24 05:55:45 PM PDT 24
Finished Jun 24 05:59:39 PM PDT 24
Peak memory 202160 kb
Host smart-6dca6368-d66f-406e-81f1-c73b35d1b84a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222723431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3222723431
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3660895004
Short name T448
Test name
Test status
Simulation time 31172445188 ps
CPU time 55.98 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 05:56:37 PM PDT 24
Peak memory 202032 kb
Host smart-0a0e8566-8c50-4be6-9e5e-556965f6c3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660895004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3660895004
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.806209500
Short name T652
Test name
Test status
Simulation time 4123435426 ps
CPU time 5.62 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 05:55:48 PM PDT 24
Peak memory 202024 kb
Host smart-e4bc40a9-a8a4-476e-a1e5-411bc0a6496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806209500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.806209500
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.793002123
Short name T147
Test name
Test status
Simulation time 5745090440 ps
CPU time 13.98 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 05:55:57 PM PDT 24
Peak memory 201876 kb
Host smart-826a2c7c-e170-40b7-905f-c222d0b9a71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793002123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.793002123
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2893929530
Short name T168
Test name
Test status
Simulation time 214528174113 ps
CPU time 130.57 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 05:57:52 PM PDT 24
Peak memory 202264 kb
Host smart-e2ee852c-bc5e-4a0a-af24-51464583e8a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893929530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2893929530
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.933407732
Short name T774
Test name
Test status
Simulation time 89423867991 ps
CPU time 80.78 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 05:57:04 PM PDT 24
Peak memory 218664 kb
Host smart-17b45f00-553e-4abe-9e4b-3861238e7cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933407732 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.933407732
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2997275773
Short name T80
Test name
Test status
Simulation time 469870231 ps
CPU time 1.74 seconds
Started Jun 24 05:55:47 PM PDT 24
Finished Jun 24 05:55:49 PM PDT 24
Peak memory 201900 kb
Host smart-b345e9be-e2b9-4ceb-9581-3a5f9a130318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997275773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2997275773
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1590498230
Short name T84
Test name
Test status
Simulation time 633944774196 ps
CPU time 636.42 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 06:06:18 PM PDT 24
Peak memory 202188 kb
Host smart-efad7f40-86eb-4935-8733-796a4d413308
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590498230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1590498230
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2779492362
Short name T164
Test name
Test status
Simulation time 340302730750 ps
CPU time 114.57 seconds
Started Jun 24 05:55:39 PM PDT 24
Finished Jun 24 05:57:34 PM PDT 24
Peak memory 202296 kb
Host smart-f7b078d8-2faa-4e9f-a873-609f566fb6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779492362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2779492362
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.149484660
Short name T647
Test name
Test status
Simulation time 336864004030 ps
CPU time 406.6 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 06:02:30 PM PDT 24
Peak memory 202236 kb
Host smart-ce09baf1-e0ab-4613-bd9e-3f8af453dead
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=149484660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.149484660
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3557249183
Short name T154
Test name
Test status
Simulation time 161896815000 ps
CPU time 54.8 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 05:56:36 PM PDT 24
Peak memory 202200 kb
Host smart-daf24d5b-ae9e-4d69-b9c5-fe1552fbddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557249183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3557249183
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3856156162
Short name T36
Test name
Test status
Simulation time 331159027950 ps
CPU time 473.29 seconds
Started Jun 24 05:55:43 PM PDT 24
Finished Jun 24 06:03:38 PM PDT 24
Peak memory 202152 kb
Host smart-282a3fc6-7168-49a5-a924-57e2c905b59a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856156162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3856156162
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3350156172
Short name T771
Test name
Test status
Simulation time 272036771122 ps
CPU time 663.86 seconds
Started Jun 24 05:55:40 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 202196 kb
Host smart-de829a92-399c-4fe6-b6fc-71a67c6797e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350156172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3350156172
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2305162742
Short name T90
Test name
Test status
Simulation time 394333948559 ps
CPU time 223.92 seconds
Started Jun 24 05:55:41 PM PDT 24
Finished Jun 24 05:59:26 PM PDT 24
Peak memory 202176 kb
Host smart-cf754937-0e07-4c25-b9ed-4ad245f87a4a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305162742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2305162742
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1208377751
Short name T447
Test name
Test status
Simulation time 116564841074 ps
CPU time 443.72 seconds
Started Jun 24 05:55:43 PM PDT 24
Finished Jun 24 06:03:08 PM PDT 24
Peak memory 202512 kb
Host smart-febdc0de-c4d8-4685-b67c-c7dcef055629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208377751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1208377751
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1442078477
Short name T518
Test name
Test status
Simulation time 30579946710 ps
CPU time 18.05 seconds
Started Jun 24 05:55:41 PM PDT 24
Finished Jun 24 05:56:00 PM PDT 24
Peak memory 202044 kb
Host smart-ec5b43b0-eede-452a-b7ff-fb8ec724d797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442078477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1442078477
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2253216990
Short name T404
Test name
Test status
Simulation time 3797424293 ps
CPU time 9.69 seconds
Started Jun 24 05:55:47 PM PDT 24
Finished Jun 24 05:55:57 PM PDT 24
Peak memory 202016 kb
Host smart-46b072d3-dd5c-4e51-86e1-db6fa0c23651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253216990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2253216990
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1076743503
Short name T478
Test name
Test status
Simulation time 6049760305 ps
CPU time 14.56 seconds
Started Jun 24 05:55:44 PM PDT 24
Finished Jun 24 05:56:00 PM PDT 24
Peak memory 202040 kb
Host smart-f22fe484-41a9-4a00-9fec-5fb596e275c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076743503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1076743503
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3179596376
Short name T48
Test name
Test status
Simulation time 9881513871 ps
CPU time 22.02 seconds
Started Jun 24 05:55:43 PM PDT 24
Finished Jun 24 05:56:06 PM PDT 24
Peak memory 202020 kb
Host smart-9cfc7bf6-1bc2-43ff-81f1-185c6aeb73e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179596376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3179596376
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3088456543
Short name T16
Test name
Test status
Simulation time 10923380997 ps
CPU time 8.34 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 05:55:52 PM PDT 24
Peak memory 202380 kb
Host smart-434bca27-b031-4aef-aa21-e46b0f3b185a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088456543 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3088456543
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3460370967
Short name T368
Test name
Test status
Simulation time 332815504 ps
CPU time 0.82 seconds
Started Jun 24 05:55:49 PM PDT 24
Finished Jun 24 05:55:51 PM PDT 24
Peak memory 201896 kb
Host smart-521657e7-d031-42c0-8a86-3f6af747ad74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460370967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3460370967
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1895336280
Short name T622
Test name
Test status
Simulation time 364837096431 ps
CPU time 416.4 seconds
Started Jun 24 05:55:48 PM PDT 24
Finished Jun 24 06:02:46 PM PDT 24
Peak memory 202188 kb
Host smart-1613f06a-4e2e-4f74-bf5d-5fce3f0d5677
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895336280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1895336280
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.842267271
Short name T715
Test name
Test status
Simulation time 165607663844 ps
CPU time 94.78 seconds
Started Jun 24 05:55:54 PM PDT 24
Finished Jun 24 05:57:29 PM PDT 24
Peak memory 202136 kb
Host smart-5b40f44c-d9b4-43fa-ac96-0bb1db1c9248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842267271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.842267271
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.378349001
Short name T86
Test name
Test status
Simulation time 165268754644 ps
CPU time 107.28 seconds
Started Jun 24 05:55:49 PM PDT 24
Finished Jun 24 05:57:37 PM PDT 24
Peak memory 202212 kb
Host smart-42c5b115-61fb-4d26-a2aa-242f00f0fc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378349001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.378349001
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3761576210
Short name T355
Test name
Test status
Simulation time 491297639054 ps
CPU time 1189.48 seconds
Started Jun 24 05:55:52 PM PDT 24
Finished Jun 24 06:15:42 PM PDT 24
Peak memory 202216 kb
Host smart-21fe5bce-5830-4440-9f0c-97e1749759af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761576210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3761576210
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3479194005
Short name T653
Test name
Test status
Simulation time 326801833641 ps
CPU time 182.72 seconds
Started Jun 24 05:55:49 PM PDT 24
Finished Jun 24 05:58:53 PM PDT 24
Peak memory 202220 kb
Host smart-c88acc34-97c4-4152-bd09-0d9133702dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479194005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3479194005
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.207751620
Short name T120
Test name
Test status
Simulation time 160883651777 ps
CPU time 32.34 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 05:56:23 PM PDT 24
Peak memory 202416 kb
Host smart-5c4e84b5-75c4-4f68-a8ab-be0a3b6b8650
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=207751620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.207751620
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.948880785
Short name T710
Test name
Test status
Simulation time 398449219709 ps
CPU time 308.45 seconds
Started Jun 24 05:55:58 PM PDT 24
Finished Jun 24 06:01:07 PM PDT 24
Peak memory 202184 kb
Host smart-7422eb08-7827-4429-8994-2929006225a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948880785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.948880785
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3142268273
Short name T384
Test name
Test status
Simulation time 199253605002 ps
CPU time 119.63 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 05:57:51 PM PDT 24
Peak memory 202176 kb
Host smart-113cb5e4-83aa-4d5a-8cae-071bf7f8afb3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142268273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3142268273
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2471228289
Short name T214
Test name
Test status
Simulation time 76384159674 ps
CPU time 262.92 seconds
Started Jun 24 05:55:49 PM PDT 24
Finished Jun 24 06:00:13 PM PDT 24
Peak memory 202516 kb
Host smart-daeb0eba-d101-4a39-b21d-84aa56cc8119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471228289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2471228289
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1237605860
Short name T776
Test name
Test status
Simulation time 39990081917 ps
CPU time 48.38 seconds
Started Jun 24 05:55:52 PM PDT 24
Finished Jun 24 05:56:41 PM PDT 24
Peak memory 202048 kb
Host smart-c9296aed-c6fb-4ab9-bb18-4b96869c4891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237605860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1237605860
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3252333552
Short name T765
Test name
Test status
Simulation time 2951886953 ps
CPU time 3.85 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 05:55:55 PM PDT 24
Peak memory 202272 kb
Host smart-763a4c15-d887-4d24-9a88-2da73d2f4844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252333552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3252333552
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1128536545
Short name T560
Test name
Test status
Simulation time 5754957515 ps
CPU time 13.49 seconds
Started Jun 24 05:55:42 PM PDT 24
Finished Jun 24 05:55:56 PM PDT 24
Peak memory 202012 kb
Host smart-a106b702-e5b4-42e6-8c1a-17d09971516d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128536545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1128536545
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2109261651
Short name T14
Test name
Test status
Simulation time 40157856253 ps
CPU time 50.85 seconds
Started Jun 24 05:55:48 PM PDT 24
Finished Jun 24 05:56:40 PM PDT 24
Peak memory 210516 kb
Host smart-edd50e6e-0434-4dde-bd23-96108465b830
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109261651 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2109261651
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1626755134
Short name T402
Test name
Test status
Simulation time 462349039 ps
CPU time 1.59 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 05:55:53 PM PDT 24
Peak memory 201904 kb
Host smart-697ac07d-73ea-4504-a106-792935ef21a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626755134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1626755134
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.749496011
Short name T237
Test name
Test status
Simulation time 162557598709 ps
CPU time 25.88 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 05:56:16 PM PDT 24
Peak memory 202176 kb
Host smart-4a1c036d-5173-4fe4-85a9-94519b807d2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749496011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.749496011
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3664768226
Short name T267
Test name
Test status
Simulation time 161322491500 ps
CPU time 188.55 seconds
Started Jun 24 05:55:48 PM PDT 24
Finished Jun 24 05:58:57 PM PDT 24
Peak memory 202196 kb
Host smart-a5d39838-8f66-4383-8ab3-e426dcce8f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664768226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3664768226
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2711829253
Short name T790
Test name
Test status
Simulation time 165963557670 ps
CPU time 95.84 seconds
Started Jun 24 05:55:49 PM PDT 24
Finished Jun 24 05:57:26 PM PDT 24
Peak memory 202164 kb
Host smart-584107cb-6b2f-4b3a-9be5-ba77d127878f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711829253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2711829253
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2146688993
Short name T197
Test name
Test status
Simulation time 329668839336 ps
CPU time 129.6 seconds
Started Jun 24 05:55:49 PM PDT 24
Finished Jun 24 05:57:59 PM PDT 24
Peak memory 202292 kb
Host smart-8c37810c-2152-4f8e-ab90-e594a1219942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146688993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2146688993
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.106420853
Short name T656
Test name
Test status
Simulation time 329848736352 ps
CPU time 187.43 seconds
Started Jun 24 05:55:49 PM PDT 24
Finished Jun 24 05:58:57 PM PDT 24
Peak memory 202176 kb
Host smart-dd720220-0c01-4d4f-b09a-64162221a8da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=106420853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.106420853
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1446622992
Short name T116
Test name
Test status
Simulation time 664481159607 ps
CPU time 1537.16 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 06:21:34 PM PDT 24
Peak memory 202392 kb
Host smart-13d2f7b7-5a60-449c-802f-429dc17fd92e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446622992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1446622992
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3161009758
Short name T507
Test name
Test status
Simulation time 596785657044 ps
CPU time 298.23 seconds
Started Jun 24 05:55:48 PM PDT 24
Finished Jun 24 06:00:47 PM PDT 24
Peak memory 202240 kb
Host smart-05505ba0-a539-4a63-a683-a219772edb47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161009758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3161009758
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1641484047
Short name T102
Test name
Test status
Simulation time 83884998146 ps
CPU time 308 seconds
Started Jun 24 05:55:51 PM PDT 24
Finished Jun 24 06:01:00 PM PDT 24
Peak memory 202492 kb
Host smart-0f7d0ccd-ca3c-483b-8620-84647aaaee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641484047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1641484047
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.291657553
Short name T722
Test name
Test status
Simulation time 41982373757 ps
CPU time 46.82 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 05:56:38 PM PDT 24
Peak memory 202040 kb
Host smart-070c4096-083c-459f-8351-3b2dc827d31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291657553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.291657553
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2174110170
Short name T439
Test name
Test status
Simulation time 2935379894 ps
CPU time 7.3 seconds
Started Jun 24 05:55:52 PM PDT 24
Finished Jun 24 05:56:00 PM PDT 24
Peak memory 202008 kb
Host smart-14e0ebe6-a1a3-4001-9238-dd92dccefba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174110170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2174110170
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1471267000
Short name T786
Test name
Test status
Simulation time 5877518752 ps
CPU time 4.01 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 05:55:55 PM PDT 24
Peak memory 201932 kb
Host smart-178159a7-a9a1-4973-8ea8-3df376bcce17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471267000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1471267000
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1644454557
Short name T338
Test name
Test status
Simulation time 481115076438 ps
CPU time 1368.43 seconds
Started Jun 24 05:55:52 PM PDT 24
Finished Jun 24 06:18:41 PM PDT 24
Peak memory 202556 kb
Host smart-cdf7c87b-b6b8-4420-b8be-fe5887db43a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644454557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1644454557
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3014261278
Short name T101
Test name
Test status
Simulation time 46076129607 ps
CPU time 117.67 seconds
Started Jun 24 05:55:47 PM PDT 24
Finished Jun 24 05:57:45 PM PDT 24
Peak memory 210976 kb
Host smart-d97465b8-cae4-402e-a1fe-ff05e7d64edc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014261278 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3014261278
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3668613067
Short name T689
Test name
Test status
Simulation time 466915861 ps
CPU time 0.88 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 05:55:52 PM PDT 24
Peak memory 201920 kb
Host smart-5d32729a-d901-4a37-91ad-c80a9d15c90d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668613067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3668613067
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3567948939
Short name T779
Test name
Test status
Simulation time 159762295559 ps
CPU time 354.4 seconds
Started Jun 24 05:55:49 PM PDT 24
Finished Jun 24 06:01:45 PM PDT 24
Peak memory 202208 kb
Host smart-66b9d328-40b8-46ff-bef7-5019d2f633c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567948939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3567948939
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2937431321
Short name T438
Test name
Test status
Simulation time 328121058099 ps
CPU time 363.47 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 06:01:55 PM PDT 24
Peak memory 202152 kb
Host smart-f96f0641-9e29-4b87-b8de-0eaa4fcca270
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937431321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2937431321
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.120585407
Short name T178
Test name
Test status
Simulation time 161612519858 ps
CPU time 64.88 seconds
Started Jun 24 05:55:48 PM PDT 24
Finished Jun 24 05:56:54 PM PDT 24
Peak memory 202216 kb
Host smart-b4bc0533-10c6-450d-b190-dfb8866f501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120585407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.120585407
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1323917944
Short name T426
Test name
Test status
Simulation time 331634565713 ps
CPU time 130.26 seconds
Started Jun 24 05:55:58 PM PDT 24
Finished Jun 24 05:58:09 PM PDT 24
Peak memory 202176 kb
Host smart-06f13188-5f88-4e3d-858f-5fa2655f8454
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323917944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1323917944
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3499966078
Short name T476
Test name
Test status
Simulation time 391032212792 ps
CPU time 407.3 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 06:02:38 PM PDT 24
Peak memory 202276 kb
Host smart-30c42449-2a8f-4072-9515-8456e7faf63f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499966078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3499966078
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2596252259
Short name T103
Test name
Test status
Simulation time 198325098456 ps
CPU time 452.74 seconds
Started Jun 24 05:55:49 PM PDT 24
Finished Jun 24 06:03:23 PM PDT 24
Peak memory 202256 kb
Host smart-9127b716-f023-401e-aada-77a5eae48f99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596252259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2596252259
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2574298986
Short name T220
Test name
Test status
Simulation time 77151894275 ps
CPU time 272.33 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 06:00:23 PM PDT 24
Peak memory 202496 kb
Host smart-4660bad3-9258-4f02-9c2a-47a04f6abc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574298986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2574298986
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.994401417
Short name T728
Test name
Test status
Simulation time 40618181427 ps
CPU time 25.94 seconds
Started Jun 24 05:55:52 PM PDT 24
Finished Jun 24 05:56:19 PM PDT 24
Peak memory 202012 kb
Host smart-7ca6e94e-ea39-476e-b860-e7f5a01dd89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994401417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.994401417
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.371078069
Short name T569
Test name
Test status
Simulation time 5465677543 ps
CPU time 3.52 seconds
Started Jun 24 05:55:48 PM PDT 24
Finished Jun 24 05:55:53 PM PDT 24
Peak memory 201996 kb
Host smart-6b4bd7a1-477b-4ea2-868d-ba51b90273b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371078069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.371078069
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3083853870
Short name T752
Test name
Test status
Simulation time 5680517563 ps
CPU time 4.4 seconds
Started Jun 24 05:55:50 PM PDT 24
Finished Jun 24 05:55:56 PM PDT 24
Peak memory 202020 kb
Host smart-eff714e5-f72e-4ab0-85ec-a87d5775d141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083853870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3083853870
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.835791474
Short name T775
Test name
Test status
Simulation time 43903881440 ps
CPU time 24.76 seconds
Started Jun 24 05:55:58 PM PDT 24
Finished Jun 24 05:56:24 PM PDT 24
Peak memory 202020 kb
Host smart-5e71dd7e-8d56-49dc-8926-7a2d52cbff4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835791474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
835791474
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.846079911
Short name T50
Test name
Test status
Simulation time 85223435257 ps
CPU time 177.25 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:58:55 PM PDT 24
Peak memory 212108 kb
Host smart-c10197ab-32c3-4a59-8adf-d9f9e11f4606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846079911 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.846079911
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3631770082
Short name T380
Test name
Test status
Simulation time 464461495 ps
CPU time 1.17 seconds
Started Jun 24 05:55:57 PM PDT 24
Finished Jun 24 05:55:59 PM PDT 24
Peak memory 201904 kb
Host smart-6697a980-41df-4e26-b75c-0dea1df0fd47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631770082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3631770082
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1558459042
Short name T789
Test name
Test status
Simulation time 166473981032 ps
CPU time 10.54 seconds
Started Jun 24 05:55:57 PM PDT 24
Finished Jun 24 05:56:09 PM PDT 24
Peak memory 202196 kb
Host smart-9afe011e-985e-410f-bb5b-14ee50c670dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558459042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1558459042
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2573824444
Short name T287
Test name
Test status
Simulation time 163373408916 ps
CPU time 103.08 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:57:40 PM PDT 24
Peak memory 202204 kb
Host smart-4f51c561-333a-45f1-b4c7-974e9dfddcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573824444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2573824444
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3671290483
Short name T663
Test name
Test status
Simulation time 163527824487 ps
CPU time 203.61 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:59:21 PM PDT 24
Peak memory 202192 kb
Host smart-e44ee908-bc8c-4f87-b880-007012cb1db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671290483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3671290483
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3896926756
Short name T767
Test name
Test status
Simulation time 160791967968 ps
CPU time 192.96 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:59:10 PM PDT 24
Peak memory 202440 kb
Host smart-8d30cb17-e4a9-427b-920b-16904d3fd609
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896926756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3896926756
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2455207941
Short name T718
Test name
Test status
Simulation time 322071896246 ps
CPU time 743.95 seconds
Started Jun 24 05:55:53 PM PDT 24
Finished Jun 24 06:08:17 PM PDT 24
Peak memory 202308 kb
Host smart-291870ad-8c4c-429a-badc-c9325919ec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455207941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2455207941
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1677903003
Short name T714
Test name
Test status
Simulation time 161885343949 ps
CPU time 43.23 seconds
Started Jun 24 05:55:52 PM PDT 24
Finished Jun 24 05:56:36 PM PDT 24
Peak memory 202160 kb
Host smart-46a2322f-f347-4635-b334-97b8ab2b93bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677903003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1677903003
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3350943803
Short name T546
Test name
Test status
Simulation time 587960549733 ps
CPU time 1426.28 seconds
Started Jun 24 05:55:52 PM PDT 24
Finished Jun 24 06:19:40 PM PDT 24
Peak memory 202232 kb
Host smart-a9a9a531-a2a9-4ed3-8777-b8e5d76d064b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350943803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3350943803
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1038354672
Short name T590
Test name
Test status
Simulation time 98748602597 ps
CPU time 479.49 seconds
Started Jun 24 05:55:59 PM PDT 24
Finished Jun 24 06:04:00 PM PDT 24
Peak memory 202588 kb
Host smart-8a8e5c21-9ee1-4617-ab87-e827f20ef0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038354672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1038354672
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.830046688
Short name T623
Test name
Test status
Simulation time 46221946952 ps
CPU time 28.59 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:56:25 PM PDT 24
Peak memory 201988 kb
Host smart-f2720c1f-f273-4057-89ef-cbbbdc2407e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830046688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.830046688
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1416498757
Short name T673
Test name
Test status
Simulation time 4112793984 ps
CPU time 5.15 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:56:03 PM PDT 24
Peak memory 201924 kb
Host smart-717afc92-5827-404c-8e41-63b691b52e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416498757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1416498757
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.177757261
Short name T504
Test name
Test status
Simulation time 5681388225 ps
CPU time 7.26 seconds
Started Jun 24 05:55:51 PM PDT 24
Finished Jun 24 05:55:59 PM PDT 24
Peak memory 201944 kb
Host smart-ffda323b-8b19-469a-91b6-b5c817438bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177757261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.177757261
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2448217563
Short name T109
Test name
Test status
Simulation time 197004185072 ps
CPU time 101.34 seconds
Started Jun 24 05:55:55 PM PDT 24
Finished Jun 24 05:57:36 PM PDT 24
Peak memory 202292 kb
Host smart-9c61c359-ad38-4bd1-94e3-2ba617a02f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448217563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2448217563
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1329681225
Short name T20
Test name
Test status
Simulation time 23587612326 ps
CPU time 25.9 seconds
Started Jun 24 05:55:58 PM PDT 24
Finished Jun 24 05:56:25 PM PDT 24
Peak memory 202584 kb
Host smart-cf090522-db5f-4521-918e-f42ba07dec09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329681225 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1329681225
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2211927588
Short name T535
Test name
Test status
Simulation time 367407677 ps
CPU time 0.87 seconds
Started Jun 24 05:55:57 PM PDT 24
Finished Jun 24 05:55:59 PM PDT 24
Peak memory 201904 kb
Host smart-beff9aae-1e07-4b22-9aac-09b893867c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211927588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2211927588
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2781768169
Short name T104
Test name
Test status
Simulation time 507420384105 ps
CPU time 394.45 seconds
Started Jun 24 05:56:01 PM PDT 24
Finished Jun 24 06:02:37 PM PDT 24
Peak memory 202180 kb
Host smart-393b053c-e8c4-4829-baac-176ff5dee6da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781768169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2781768169
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.943705015
Short name T207
Test name
Test status
Simulation time 554993392135 ps
CPU time 311.7 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 06:01:09 PM PDT 24
Peak memory 202200 kb
Host smart-8df802aa-8321-4171-9b4a-ef3ca4387d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943705015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.943705015
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1695517271
Short name T303
Test name
Test status
Simulation time 329868177662 ps
CPU time 101.29 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:57:39 PM PDT 24
Peak memory 202212 kb
Host smart-66bc2a52-fc6c-46a2-9160-238531332bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695517271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1695517271
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.4150161235
Short name T678
Test name
Test status
Simulation time 322395458454 ps
CPU time 201.5 seconds
Started Jun 24 05:55:59 PM PDT 24
Finished Jun 24 05:59:22 PM PDT 24
Peak memory 202232 kb
Host smart-cb144e72-d3b9-4cf4-b80c-13f5dc6af559
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150161235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.4150161235
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2031834845
Short name T418
Test name
Test status
Simulation time 326554420911 ps
CPU time 379.79 seconds
Started Jun 24 05:56:02 PM PDT 24
Finished Jun 24 06:02:23 PM PDT 24
Peak memory 202184 kb
Host smart-a2f6e685-faae-4150-9d51-61bc7e609f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031834845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2031834845
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.580930180
Short name T108
Test name
Test status
Simulation time 495778203477 ps
CPU time 1167.79 seconds
Started Jun 24 05:56:02 PM PDT 24
Finished Jun 24 06:15:31 PM PDT 24
Peak memory 202160 kb
Host smart-7768fe9c-915b-409a-8b85-89da1ec3363d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=580930180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.580930180
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4131799113
Short name T600
Test name
Test status
Simulation time 201314637668 ps
CPU time 126.07 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:58:04 PM PDT 24
Peak memory 202180 kb
Host smart-c0e29f63-63f7-4528-85d2-e3693014dc15
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131799113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4131799113
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1911356814
Short name T218
Test name
Test status
Simulation time 80086943436 ps
CPU time 437.19 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 06:03:15 PM PDT 24
Peak memory 202508 kb
Host smart-96574754-c72e-41f6-b199-5bda4189edee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911356814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1911356814
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.929117578
Short name T510
Test name
Test status
Simulation time 31241474168 ps
CPU time 35.28 seconds
Started Jun 24 05:55:57 PM PDT 24
Finished Jun 24 05:56:34 PM PDT 24
Peak memory 201952 kb
Host smart-a63bca75-9839-4b08-9c9c-91b7cd6427cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929117578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.929117578
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2753468728
Short name T432
Test name
Test status
Simulation time 5200551901 ps
CPU time 7.88 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:56:04 PM PDT 24
Peak memory 202000 kb
Host smart-cc980d84-f9eb-4d92-a5b0-3f7a8aea3951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753468728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2753468728
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.355445152
Short name T621
Test name
Test status
Simulation time 5533992001 ps
CPU time 7.19 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:56:05 PM PDT 24
Peak memory 202036 kb
Host smart-a1279e49-5f3d-4ee6-873c-c254edb3f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355445152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.355445152
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3055308838
Short name T161
Test name
Test status
Simulation time 212330014156 ps
CPU time 243.16 seconds
Started Jun 24 05:55:58 PM PDT 24
Finished Jun 24 06:00:02 PM PDT 24
Peak memory 202264 kb
Host smart-4cc14457-17e6-44cc-a630-d66ffd4980de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055308838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3055308838
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2010247857
Short name T727
Test name
Test status
Simulation time 468775867 ps
CPU time 1.7 seconds
Started Jun 24 05:56:06 PM PDT 24
Finished Jun 24 05:56:09 PM PDT 24
Peak memory 201880 kb
Host smart-84167524-72ea-4776-b4c0-fb86c508de37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010247857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2010247857
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1184752411
Short name T734
Test name
Test status
Simulation time 164060866210 ps
CPU time 354.88 seconds
Started Jun 24 05:56:08 PM PDT 24
Finished Jun 24 06:02:03 PM PDT 24
Peak memory 202176 kb
Host smart-87349eda-b45c-4eaf-80e1-51715c31ab53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184752411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1184752411
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1776087838
Short name T557
Test name
Test status
Simulation time 163405176477 ps
CPU time 191.17 seconds
Started Jun 24 05:56:07 PM PDT 24
Finished Jun 24 05:59:19 PM PDT 24
Peak memory 202128 kb
Host smart-72a6fc89-8b8f-48ef-b53f-a18bf5dc0675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776087838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1776087838
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.555310314
Short name T471
Test name
Test status
Simulation time 161185710109 ps
CPU time 405.61 seconds
Started Jun 24 05:56:09 PM PDT 24
Finished Jun 24 06:02:55 PM PDT 24
Peak memory 202236 kb
Host smart-4e3b0848-d7ae-4d29-9296-1110684f8e3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=555310314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.555310314
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3831929095
Short name T659
Test name
Test status
Simulation time 168611114302 ps
CPU time 396.73 seconds
Started Jun 24 05:55:55 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 202256 kb
Host smart-c1c77677-7ae7-459e-add5-12ae11170780
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831929095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3831929095
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1677688440
Short name T152
Test name
Test status
Simulation time 365158240664 ps
CPU time 402.63 seconds
Started Jun 24 05:56:07 PM PDT 24
Finished Jun 24 06:02:51 PM PDT 24
Peak memory 202268 kb
Host smart-6c8819e8-de16-4802-b07a-28fa313a75d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677688440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1677688440
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1495862652
Short name T331
Test name
Test status
Simulation time 72269157372 ps
CPU time 272.32 seconds
Started Jun 24 05:56:06 PM PDT 24
Finished Jun 24 06:00:40 PM PDT 24
Peak memory 202540 kb
Host smart-79bff784-854c-450e-aefb-25c5f4697d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495862652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1495862652
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2087631985
Short name T695
Test name
Test status
Simulation time 42611509098 ps
CPU time 93.93 seconds
Started Jun 24 05:56:06 PM PDT 24
Finished Jun 24 05:57:42 PM PDT 24
Peak memory 201976 kb
Host smart-fa5c923b-e679-4afb-8b19-91d073c6c9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087631985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2087631985
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.868709469
Short name T700
Test name
Test status
Simulation time 5589771810 ps
CPU time 4.17 seconds
Started Jun 24 05:56:06 PM PDT 24
Finished Jun 24 05:56:11 PM PDT 24
Peak memory 202004 kb
Host smart-16f49acd-0a59-4b88-96e3-16be147af0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868709469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.868709469
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.569198047
Short name T460
Test name
Test status
Simulation time 6218163577 ps
CPU time 4.24 seconds
Started Jun 24 05:55:56 PM PDT 24
Finished Jun 24 05:56:02 PM PDT 24
Peak memory 202008 kb
Host smart-96afb1dc-d6d1-437e-a1fe-6a04c8dadcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569198047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.569198047
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1034495452
Short name T246
Test name
Test status
Simulation time 404392292523 ps
CPU time 142.82 seconds
Started Jun 24 05:56:06 PM PDT 24
Finished Jun 24 05:58:30 PM PDT 24
Peak memory 202184 kb
Host smart-391d35e2-930b-4dfa-ad20-bcd32d694229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034495452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1034495452
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1798967850
Short name T748
Test name
Test status
Simulation time 90875660282 ps
CPU time 209.1 seconds
Started Jun 24 05:56:06 PM PDT 24
Finished Jun 24 05:59:37 PM PDT 24
Peak memory 219056 kb
Host smart-9cb1b68f-3d28-4d2f-b42e-3cf13caf957a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798967850 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1798967850
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.692506301
Short name T491
Test name
Test status
Simulation time 334019619 ps
CPU time 0.8 seconds
Started Jun 24 05:55:12 PM PDT 24
Finished Jun 24 05:55:15 PM PDT 24
Peak memory 201900 kb
Host smart-11296272-cfbd-417e-9b05-845d6b21b67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692506301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.692506301
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.35377403
Short name T318
Test name
Test status
Simulation time 172166457182 ps
CPU time 284.63 seconds
Started Jun 24 05:55:08 PM PDT 24
Finished Jun 24 05:59:54 PM PDT 24
Peak memory 202200 kb
Host smart-5050acd1-fa92-412b-9e34-cb0e75eab8f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35377403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating
.35377403
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4044408161
Short name T692
Test name
Test status
Simulation time 327419594252 ps
CPU time 715.2 seconds
Started Jun 24 05:55:18 PM PDT 24
Finished Jun 24 06:07:14 PM PDT 24
Peak memory 202300 kb
Host smart-b62704e4-2dec-4c1f-a4f7-cbc600dd47be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044408161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4044408161
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.809746661
Short name T261
Test name
Test status
Simulation time 333398273339 ps
CPU time 182.4 seconds
Started Jun 24 05:55:17 PM PDT 24
Finished Jun 24 05:58:20 PM PDT 24
Peak memory 202300 kb
Host smart-e219f7c7-e26b-40ff-9762-cc72145a8ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809746661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.809746661
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2163022922
Short name T736
Test name
Test status
Simulation time 321247448397 ps
CPU time 716.86 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 06:07:09 PM PDT 24
Peak memory 202168 kb
Host smart-c64f4357-5686-4fc2-ba91-8659fe549a1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163022922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2163022922
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1697457875
Short name T300
Test name
Test status
Simulation time 499849002846 ps
CPU time 601.42 seconds
Started Jun 24 05:55:10 PM PDT 24
Finished Jun 24 06:05:13 PM PDT 24
Peak memory 202272 kb
Host smart-af27aa07-ee0c-45e6-8d1f-be6037f2af04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697457875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1697457875
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1615956306
Short name T697
Test name
Test status
Simulation time 504944791714 ps
CPU time 334.44 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 06:00:45 PM PDT 24
Peak memory 202152 kb
Host smart-071f9f46-41e1-4b11-9c60-e2e4fff00621
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615956306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1615956306
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2091711514
Short name T314
Test name
Test status
Simulation time 348404308585 ps
CPU time 386.82 seconds
Started Jun 24 05:55:10 PM PDT 24
Finished Jun 24 06:01:39 PM PDT 24
Peak memory 202252 kb
Host smart-1823eee5-d5b6-4eed-b96b-e1022681806f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091711514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2091711514
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2038943342
Short name T500
Test name
Test status
Simulation time 202710011126 ps
CPU time 496.1 seconds
Started Jun 24 05:55:14 PM PDT 24
Finished Jun 24 06:03:32 PM PDT 24
Peak memory 202096 kb
Host smart-3dbfe092-6239-4bf6-8879-4f2a382030f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038943342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2038943342
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.4061948469
Short name T435
Test name
Test status
Simulation time 119226580767 ps
CPU time 449.27 seconds
Started Jun 24 05:55:17 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 202588 kb
Host smart-6ca04c44-2e10-49b8-aac2-c30d1f0eec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061948469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.4061948469
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2320571845
Short name T496
Test name
Test status
Simulation time 30800741555 ps
CPU time 68.4 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:56:22 PM PDT 24
Peak memory 202020 kb
Host smart-5abfa6fb-be79-418c-9af1-bee228fc5ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320571845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2320571845
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2134409132
Short name T610
Test name
Test status
Simulation time 4702369233 ps
CPU time 5.69 seconds
Started Jun 24 05:55:09 PM PDT 24
Finished Jun 24 05:55:16 PM PDT 24
Peak memory 202016 kb
Host smart-18ebc5a4-8615-4855-aafd-7725fd979328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134409132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2134409132
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2905883169
Short name T81
Test name
Test status
Simulation time 4201753611 ps
CPU time 10.08 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:55:23 PM PDT 24
Peak memory 217800 kb
Host smart-8e536d97-5122-4a81-860e-2fb223b8f21c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905883169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2905883169
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3505327322
Short name T527
Test name
Test status
Simulation time 5866510996 ps
CPU time 3.69 seconds
Started Jun 24 05:55:16 PM PDT 24
Finished Jun 24 05:55:21 PM PDT 24
Peak memory 202028 kb
Host smart-ffcb43ed-f9b4-4c7f-ab02-4c9f8ea0bc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505327322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3505327322
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.113459656
Short name T488
Test name
Test status
Simulation time 410555794058 ps
CPU time 264.5 seconds
Started Jun 24 05:55:08 PM PDT 24
Finished Jun 24 05:59:34 PM PDT 24
Peak memory 202200 kb
Host smart-8c55f9d0-7668-446b-8d86-30cf1837baa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113459656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.113459656
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2723671668
Short name T425
Test name
Test status
Simulation time 431543840 ps
CPU time 0.88 seconds
Started Jun 24 05:56:20 PM PDT 24
Finished Jun 24 05:56:22 PM PDT 24
Peak memory 201900 kb
Host smart-16553dee-f4a5-44a0-9e80-e1f47ebdea0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723671668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2723671668
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2649458620
Short name T301
Test name
Test status
Simulation time 332553942425 ps
CPU time 720.81 seconds
Started Jun 24 05:56:21 PM PDT 24
Finished Jun 24 06:08:22 PM PDT 24
Peak memory 202248 kb
Host smart-38c4c8c5-7751-45d8-b2b5-e8bbb37383c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649458620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2649458620
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4242784157
Short name T153
Test name
Test status
Simulation time 164398219462 ps
CPU time 198.95 seconds
Started Jun 24 05:56:21 PM PDT 24
Finished Jun 24 05:59:41 PM PDT 24
Peak memory 202200 kb
Host smart-78a5cc79-f8d8-403d-8025-a04961287027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242784157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4242784157
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1301499166
Short name T260
Test name
Test status
Simulation time 332147464123 ps
CPU time 766.23 seconds
Started Jun 24 05:56:20 PM PDT 24
Finished Jun 24 06:09:07 PM PDT 24
Peak memory 202280 kb
Host smart-6ca0046d-de1c-4f71-81a2-3aa65b91a0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301499166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1301499166
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.657273675
Short name T615
Test name
Test status
Simulation time 170119213905 ps
CPU time 377.15 seconds
Started Jun 24 05:56:25 PM PDT 24
Finished Jun 24 06:02:42 PM PDT 24
Peak memory 202176 kb
Host smart-99495fd3-779a-4af7-b01c-fa588e57ddf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=657273675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.657273675
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3122886349
Short name T703
Test name
Test status
Simulation time 164508482643 ps
CPU time 157.59 seconds
Started Jun 24 05:56:06 PM PDT 24
Finished Jun 24 05:58:45 PM PDT 24
Peak memory 202200 kb
Host smart-ffa34feb-ee2d-4c60-9195-4b3fd7454430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122886349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3122886349
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1659017450
Short name T782
Test name
Test status
Simulation time 166847788288 ps
CPU time 355.28 seconds
Started Jun 24 05:56:06 PM PDT 24
Finished Jun 24 06:02:03 PM PDT 24
Peak memory 202176 kb
Host smart-d4064812-3c5a-47d3-a99b-3fb583cfa9e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659017450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1659017450
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2400203323
Short name T549
Test name
Test status
Simulation time 651256057686 ps
CPU time 1560.12 seconds
Started Jun 24 05:56:22 PM PDT 24
Finished Jun 24 06:22:23 PM PDT 24
Peak memory 202264 kb
Host smart-ef15f0f4-052b-47fd-9573-25df62023a88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400203323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2400203323
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3188147374
Short name T451
Test name
Test status
Simulation time 606500637649 ps
CPU time 339.33 seconds
Started Jun 24 05:56:23 PM PDT 24
Finished Jun 24 06:02:03 PM PDT 24
Peak memory 202272 kb
Host smart-a1116d4c-28ec-4c06-a69d-86995dae5fb3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188147374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3188147374
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3784330539
Short name T173
Test name
Test status
Simulation time 107474758812 ps
CPU time 370.53 seconds
Started Jun 24 05:56:21 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 202592 kb
Host smart-5d60332d-8bdc-42d5-946e-9d542edf82eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784330539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3784330539
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3941603141
Short name T737
Test name
Test status
Simulation time 24411321369 ps
CPU time 25.3 seconds
Started Jun 24 05:56:23 PM PDT 24
Finished Jun 24 05:56:49 PM PDT 24
Peak memory 202048 kb
Host smart-8e679409-f484-4156-9ee6-fa6ac79a0faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941603141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3941603141
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1507144143
Short name T458
Test name
Test status
Simulation time 3523474806 ps
CPU time 8.62 seconds
Started Jun 24 05:56:21 PM PDT 24
Finished Jun 24 05:56:30 PM PDT 24
Peak memory 202016 kb
Host smart-6562e9a1-c980-4d3e-b2ba-b5498291a9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507144143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1507144143
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2956602430
Short name T83
Test name
Test status
Simulation time 5981262999 ps
CPU time 4.03 seconds
Started Jun 24 05:56:07 PM PDT 24
Finished Jun 24 05:56:12 PM PDT 24
Peak memory 202016 kb
Host smart-0ba678f2-c30f-40b9-b1b3-12e0c1175f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956602430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2956602430
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2995662906
Short name T17
Test name
Test status
Simulation time 16724284307 ps
CPU time 46.99 seconds
Started Jun 24 05:56:21 PM PDT 24
Finished Jun 24 05:57:09 PM PDT 24
Peak memory 210764 kb
Host smart-54bb3b1d-d575-4857-94d4-27ec0d31f7ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995662906 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2995662906
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3807675485
Short name T450
Test name
Test status
Simulation time 305058470 ps
CPU time 0.99 seconds
Started Jun 24 05:56:26 PM PDT 24
Finished Jun 24 05:56:28 PM PDT 24
Peak memory 201920 kb
Host smart-6f66842f-d670-4fa8-b836-048d07b54439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807675485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3807675485
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2560807859
Short name T113
Test name
Test status
Simulation time 388199041737 ps
CPU time 595.86 seconds
Started Jun 24 05:56:20 PM PDT 24
Finished Jun 24 06:06:16 PM PDT 24
Peak memory 202192 kb
Host smart-455e473c-749d-4d1b-9155-0fdaeeb415ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560807859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2560807859
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2580575781
Short name T792
Test name
Test status
Simulation time 180971194785 ps
CPU time 118.13 seconds
Started Jun 24 05:56:21 PM PDT 24
Finished Jun 24 05:58:20 PM PDT 24
Peak memory 202260 kb
Host smart-dd765663-4588-4b02-aaa3-f4680ef42b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580575781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2580575781
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2180249080
Short name T434
Test name
Test status
Simulation time 325685875676 ps
CPU time 431.14 seconds
Started Jun 24 05:56:20 PM PDT 24
Finished Jun 24 06:03:32 PM PDT 24
Peak memory 202232 kb
Host smart-12165b3e-ddea-4026-b81d-0b497d393b38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180249080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2180249080
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2286667768
Short name T712
Test name
Test status
Simulation time 328323610701 ps
CPU time 107.15 seconds
Started Jun 24 05:56:19 PM PDT 24
Finished Jun 24 05:58:07 PM PDT 24
Peak memory 202248 kb
Host smart-12dd01fd-aaab-4ee9-9bc7-db0fe61db16b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286667768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2286667768
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.415353689
Short name T684
Test name
Test status
Simulation time 171495326832 ps
CPU time 134.11 seconds
Started Jun 24 05:56:23 PM PDT 24
Finished Jun 24 05:58:38 PM PDT 24
Peak memory 202288 kb
Host smart-4c1b25bc-1513-48ab-b957-b7f6047cbe2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415353689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.415353689
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2929176953
Short name T24
Test name
Test status
Simulation time 407951497092 ps
CPU time 458.7 seconds
Started Jun 24 05:56:25 PM PDT 24
Finished Jun 24 06:04:04 PM PDT 24
Peak memory 202192 kb
Host smart-dfbca08d-6d36-45e0-9ef7-60eb33b237aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929176953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2929176953
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1901060848
Short name T216
Test name
Test status
Simulation time 111026201649 ps
CPU time 441.91 seconds
Started Jun 24 05:56:23 PM PDT 24
Finished Jun 24 06:03:46 PM PDT 24
Peak memory 202528 kb
Host smart-c568d45a-147c-4f78-a989-2161099146da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901060848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1901060848
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2101053488
Short name T533
Test name
Test status
Simulation time 39689634052 ps
CPU time 12.08 seconds
Started Jun 24 05:56:26 PM PDT 24
Finished Jun 24 05:56:39 PM PDT 24
Peak memory 202040 kb
Host smart-9ad59d07-76d7-4d7b-97c2-7e084ad35f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101053488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2101053488
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2432029270
Short name T713
Test name
Test status
Simulation time 5260676646 ps
CPU time 3.83 seconds
Started Jun 24 05:56:25 PM PDT 24
Finished Jun 24 05:56:30 PM PDT 24
Peak memory 202272 kb
Host smart-4188ae08-7d74-4f52-a980-540e1f04e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432029270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2432029270
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3082110867
Short name T416
Test name
Test status
Simulation time 5927227194 ps
CPU time 3.95 seconds
Started Jun 24 05:56:21 PM PDT 24
Finished Jun 24 05:56:26 PM PDT 24
Peak memory 202032 kb
Host smart-fa8e09d4-f5b5-43a5-ae58-44644c5e19b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082110867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3082110867
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.903382522
Short name T233
Test name
Test status
Simulation time 175949333004 ps
CPU time 204.04 seconds
Started Jun 24 05:56:25 PM PDT 24
Finished Jun 24 05:59:50 PM PDT 24
Peak memory 202184 kb
Host smart-bfed1bde-aa56-4073-b365-aabef4f621b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903382522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
903382522
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3141191212
Short name T611
Test name
Test status
Simulation time 60611031765 ps
CPU time 102.57 seconds
Started Jun 24 05:56:24 PM PDT 24
Finished Jun 24 05:58:07 PM PDT 24
Peak memory 210520 kb
Host smart-16a2515f-3c4d-4216-8dea-e07bc880408a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141191212 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3141191212
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1486118168
Short name T555
Test name
Test status
Simulation time 350023826 ps
CPU time 0.79 seconds
Started Jun 24 05:56:35 PM PDT 24
Finished Jun 24 05:56:36 PM PDT 24
Peak memory 201832 kb
Host smart-a5731a19-063c-43da-8764-e08c5b50a4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486118168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1486118168
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4184240662
Short name T275
Test name
Test status
Simulation time 203272397595 ps
CPU time 101.38 seconds
Started Jun 24 05:56:26 PM PDT 24
Finished Jun 24 05:58:08 PM PDT 24
Peak memory 202188 kb
Host smart-ec8239f7-89dc-4862-bab9-2bdad2440ee2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184240662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4184240662
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3304936343
Short name T203
Test name
Test status
Simulation time 487898943636 ps
CPU time 100.68 seconds
Started Jun 24 05:56:25 PM PDT 24
Finished Jun 24 05:58:07 PM PDT 24
Peak memory 202228 kb
Host smart-687babae-6672-42a8-8110-f7eaa165b9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304936343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3304936343
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.120383720
Short name T362
Test name
Test status
Simulation time 491505487045 ps
CPU time 727.7 seconds
Started Jun 24 05:56:25 PM PDT 24
Finished Jun 24 06:08:33 PM PDT 24
Peak memory 202504 kb
Host smart-c9949007-f0f6-4f31-bd38-ebff7a247df7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=120383720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.120383720
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1834128491
Short name T209
Test name
Test status
Simulation time 326903076789 ps
CPU time 117.9 seconds
Started Jun 24 05:56:27 PM PDT 24
Finished Jun 24 05:58:25 PM PDT 24
Peak memory 202280 kb
Host smart-a07f44a5-c6c3-4b39-914c-a7eedf5faaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834128491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1834128491
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2684865757
Short name T576
Test name
Test status
Simulation time 170629409626 ps
CPU time 56.58 seconds
Started Jun 24 05:56:27 PM PDT 24
Finished Jun 24 05:57:24 PM PDT 24
Peak memory 202444 kb
Host smart-f14d3599-309d-4d75-937c-0bdadbc58ce9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684865757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2684865757
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2877231492
Short name T783
Test name
Test status
Simulation time 424285004313 ps
CPU time 88.55 seconds
Started Jun 24 05:56:26 PM PDT 24
Finished Jun 24 05:57:55 PM PDT 24
Peak memory 202200 kb
Host smart-38ab91b8-a0b1-4b4b-aada-b7ded85397d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877231492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2877231492
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3533666108
Short name T536
Test name
Test status
Simulation time 202753900168 ps
CPU time 232.26 seconds
Started Jun 24 05:56:22 PM PDT 24
Finished Jun 24 06:00:15 PM PDT 24
Peak memory 202204 kb
Host smart-2d788a0f-999f-47d0-af81-76ebe38a3ba7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533666108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3533666108
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1919607788
Short name T117
Test name
Test status
Simulation time 114238793365 ps
CPU time 409.25 seconds
Started Jun 24 05:56:37 PM PDT 24
Finished Jun 24 06:03:27 PM PDT 24
Peak memory 202820 kb
Host smart-32125c0b-ebfc-49b8-a18a-1adacd631026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919607788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1919607788
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.4053734641
Short name T446
Test name
Test status
Simulation time 25194771677 ps
CPU time 31.73 seconds
Started Jun 24 05:56:27 PM PDT 24
Finished Jun 24 05:57:00 PM PDT 24
Peak memory 202216 kb
Host smart-e6074a27-306d-47c5-8c91-28023259cd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053734641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.4053734641
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.861048165
Short name T346
Test name
Test status
Simulation time 3138145663 ps
CPU time 7.66 seconds
Started Jun 24 05:56:26 PM PDT 24
Finished Jun 24 05:56:34 PM PDT 24
Peak memory 202016 kb
Host smart-acc57cd9-6a12-48de-9c75-e56b0a46a37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861048165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.861048165
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3483775710
Short name T657
Test name
Test status
Simulation time 5879298870 ps
CPU time 4.43 seconds
Started Jun 24 05:56:27 PM PDT 24
Finished Jun 24 05:56:32 PM PDT 24
Peak memory 202028 kb
Host smart-061f872d-0179-471e-a219-47bd4273bd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483775710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3483775710
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2237933850
Short name T570
Test name
Test status
Simulation time 304832087236 ps
CPU time 707.9 seconds
Started Jun 24 05:56:36 PM PDT 24
Finished Jun 24 06:08:25 PM PDT 24
Peak memory 212460 kb
Host smart-938526a2-8a47-4e55-9dce-6459d89b1feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237933850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2237933850
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1413979714
Short name T15
Test name
Test status
Simulation time 60156908885 ps
CPU time 112.33 seconds
Started Jun 24 05:56:36 PM PDT 24
Finished Jun 24 05:58:29 PM PDT 24
Peak memory 210596 kb
Host smart-1a20c175-89c0-4406-83e0-7a730c8f6431
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413979714 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1413979714
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3239411806
Short name T754
Test name
Test status
Simulation time 543598917 ps
CPU time 0.74 seconds
Started Jun 24 05:56:34 PM PDT 24
Finished Jun 24 05:56:35 PM PDT 24
Peak memory 201932 kb
Host smart-0a36ee90-e748-4f93-80d2-ea76d3f48de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239411806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3239411806
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2700955802
Short name T306
Test name
Test status
Simulation time 160583695365 ps
CPU time 185.74 seconds
Started Jun 24 05:56:35 PM PDT 24
Finished Jun 24 05:59:42 PM PDT 24
Peak memory 202268 kb
Host smart-37673e26-10cf-49b7-b035-61e8eb7dcda0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700955802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2700955802
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.390662381
Short name T396
Test name
Test status
Simulation time 164856159231 ps
CPU time 65.74 seconds
Started Jun 24 05:56:35 PM PDT 24
Finished Jun 24 05:57:42 PM PDT 24
Peak memory 202296 kb
Host smart-fa756956-5183-47e1-ac5a-709f8a44ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390662381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.390662381
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.4288486127
Short name T753
Test name
Test status
Simulation time 484073813897 ps
CPU time 596.48 seconds
Started Jun 24 05:56:35 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 202176 kb
Host smart-b8bc159a-b499-4d9f-a876-2d64855a5f9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288486127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.4288486127
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3598600080
Short name T158
Test name
Test status
Simulation time 490115159538 ps
CPU time 268.68 seconds
Started Jun 24 05:56:35 PM PDT 24
Finished Jun 24 06:01:05 PM PDT 24
Peak memory 202184 kb
Host smart-bd2f1311-5f87-477c-8a33-3ab2fb62f114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598600080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3598600080
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1181790312
Short name T661
Test name
Test status
Simulation time 494380947330 ps
CPU time 566.95 seconds
Started Jun 24 05:56:36 PM PDT 24
Finished Jun 24 06:06:04 PM PDT 24
Peak memory 202176 kb
Host smart-d56aebc5-264e-4b0e-8a22-59e875c2cdfc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181790312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1181790312
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3259593809
Short name T461
Test name
Test status
Simulation time 176918486534 ps
CPU time 111.41 seconds
Started Jun 24 05:56:36 PM PDT 24
Finished Jun 24 05:58:28 PM PDT 24
Peak memory 202204 kb
Host smart-4f3db184-c02a-4b31-a9f9-d9066a4d642e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259593809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3259593809
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1106137059
Short name T649
Test name
Test status
Simulation time 609792141678 ps
CPU time 177.33 seconds
Started Jun 24 05:56:35 PM PDT 24
Finished Jun 24 05:59:34 PM PDT 24
Peak memory 202172 kb
Host smart-4935f4b3-b949-461e-89a5-5b99b6f726e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106137059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1106137059
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.590649035
Short name T23
Test name
Test status
Simulation time 70555888550 ps
CPU time 296.74 seconds
Started Jun 24 05:56:36 PM PDT 24
Finished Jun 24 06:01:33 PM PDT 24
Peak memory 202520 kb
Host smart-bceac7f4-24f3-4dd7-a344-6dd53f15fdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590649035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.590649035
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.529785861
Short name T437
Test name
Test status
Simulation time 33578945062 ps
CPU time 6.59 seconds
Started Jun 24 05:56:38 PM PDT 24
Finished Jun 24 05:56:45 PM PDT 24
Peak memory 202016 kb
Host smart-783ad823-3eaf-460f-9cd9-379faff577f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529785861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.529785861
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2506009596
Short name T582
Test name
Test status
Simulation time 3578827950 ps
CPU time 1.82 seconds
Started Jun 24 05:56:36 PM PDT 24
Finished Jun 24 05:56:39 PM PDT 24
Peak memory 202020 kb
Host smart-645e4c9f-6f63-474a-9634-de72f07f904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506009596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2506009596
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1749642827
Short name T422
Test name
Test status
Simulation time 5849063711 ps
CPU time 2.78 seconds
Started Jun 24 05:56:35 PM PDT 24
Finished Jun 24 05:56:38 PM PDT 24
Peak memory 202012 kb
Host smart-80944d2c-b2bc-48bf-9619-ee7381a6f046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749642827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1749642827
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2269368001
Short name T33
Test name
Test status
Simulation time 213662477626 ps
CPU time 496.84 seconds
Started Jun 24 05:56:37 PM PDT 24
Finished Jun 24 06:04:54 PM PDT 24
Peak memory 202196 kb
Host smart-9b6fd84a-1583-4419-8b8b-98a1bc50210b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269368001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2269368001
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1968899633
Short name T636
Test name
Test status
Simulation time 443307212 ps
CPU time 0.87 seconds
Started Jun 24 05:56:44 PM PDT 24
Finished Jun 24 05:56:46 PM PDT 24
Peak memory 201928 kb
Host smart-3a8c1cd9-fadd-4163-9249-bd520402d315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968899633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1968899633
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2886127183
Short name T311
Test name
Test status
Simulation time 502045059197 ps
CPU time 1166.9 seconds
Started Jun 24 05:56:46 PM PDT 24
Finished Jun 24 06:16:14 PM PDT 24
Peak memory 202444 kb
Host smart-bd2a9769-db27-41c3-87b0-82c9ee84cfeb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886127183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2886127183
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3883723041
Short name T250
Test name
Test status
Simulation time 166054191131 ps
CPU time 208.47 seconds
Started Jun 24 05:56:46 PM PDT 24
Finished Jun 24 06:00:15 PM PDT 24
Peak memory 202120 kb
Host smart-5b635edd-f387-4a04-82b4-c1b7911f900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883723041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3883723041
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1231715979
Short name T599
Test name
Test status
Simulation time 488016131368 ps
CPU time 569.08 seconds
Started Jun 24 05:56:46 PM PDT 24
Finished Jun 24 06:06:16 PM PDT 24
Peak memory 202220 kb
Host smart-85e15670-2ca4-4b01-9e08-7d0c758d59e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231715979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1231715979
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2220502889
Short name T638
Test name
Test status
Simulation time 163741332668 ps
CPU time 93.51 seconds
Started Jun 24 05:56:45 PM PDT 24
Finished Jun 24 05:58:19 PM PDT 24
Peak memory 202192 kb
Host smart-2509e484-9534-4658-8c46-37ebe6043477
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220502889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2220502889
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.289944525
Short name T155
Test name
Test status
Simulation time 168808738980 ps
CPU time 72.53 seconds
Started Jun 24 05:56:44 PM PDT 24
Finished Jun 24 05:57:57 PM PDT 24
Peak memory 202288 kb
Host smart-a8ae24f2-cc28-4443-9651-216fcc4636c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289944525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.289944525
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1463720938
Short name T205
Test name
Test status
Simulation time 164232255882 ps
CPU time 96.64 seconds
Started Jun 24 05:56:46 PM PDT 24
Finished Jun 24 05:58:23 PM PDT 24
Peak memory 202180 kb
Host smart-b0c73f4b-9353-4d9a-86d5-bc3c2fd21cc9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463720938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1463720938
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1499113375
Short name T204
Test name
Test status
Simulation time 175824319957 ps
CPU time 98.98 seconds
Started Jun 24 05:56:45 PM PDT 24
Finished Jun 24 05:58:25 PM PDT 24
Peak memory 202276 kb
Host smart-7060612d-bd90-4682-8ced-53ea1e83a4fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499113375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1499113375
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2207649334
Short name T409
Test name
Test status
Simulation time 406735632752 ps
CPU time 227.44 seconds
Started Jun 24 05:56:45 PM PDT 24
Finished Jun 24 06:00:33 PM PDT 24
Peak memory 202276 kb
Host smart-ff411298-b842-4e76-836f-46459d37ae61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207649334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2207649334
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1518904505
Short name T390
Test name
Test status
Simulation time 66545723128 ps
CPU time 367.78 seconds
Started Jun 24 05:56:47 PM PDT 24
Finished Jun 24 06:02:55 PM PDT 24
Peak memory 202508 kb
Host smart-24a3c775-102e-415d-937e-b6b35e529da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518904505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1518904505
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1062825743
Short name T487
Test name
Test status
Simulation time 43771934713 ps
CPU time 31.8 seconds
Started Jun 24 05:56:44 PM PDT 24
Finished Jun 24 05:57:17 PM PDT 24
Peak memory 202032 kb
Host smart-2e626091-b42a-4904-8b1e-db37a948c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062825743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1062825743
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1296631804
Short name T624
Test name
Test status
Simulation time 5341680768 ps
CPU time 1.46 seconds
Started Jun 24 05:56:48 PM PDT 24
Finished Jun 24 05:56:50 PM PDT 24
Peak memory 202012 kb
Host smart-cb42e711-4eb6-461c-ba1d-ff089eb52863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296631804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1296631804
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.905781259
Short name T486
Test name
Test status
Simulation time 5704558210 ps
CPU time 9.57 seconds
Started Jun 24 05:56:45 PM PDT 24
Finished Jun 24 05:56:56 PM PDT 24
Peak memory 202012 kb
Host smart-d7d1d5b4-2ec5-4429-b28f-ef130904d003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905781259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.905781259
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1871862137
Short name T52
Test name
Test status
Simulation time 25785350826 ps
CPU time 64.11 seconds
Started Jun 24 05:56:44 PM PDT 24
Finished Jun 24 05:57:49 PM PDT 24
Peak memory 210804 kb
Host smart-cf202884-04f9-4f14-8e82-ec69c8f7dda4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871862137 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1871862137
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2913163673
Short name T592
Test name
Test status
Simulation time 472835683 ps
CPU time 1.18 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 05:57:04 PM PDT 24
Peak memory 201924 kb
Host smart-92da48ab-c19c-40eb-9b6c-a11d4fe7e663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913163673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2913163673
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3861169981
Short name T641
Test name
Test status
Simulation time 164736032474 ps
CPU time 92.07 seconds
Started Jun 24 05:56:44 PM PDT 24
Finished Jun 24 05:58:17 PM PDT 24
Peak memory 202276 kb
Host smart-f2553069-f0d1-469b-8509-aaa902cfbe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861169981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3861169981
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4240230551
Short name T587
Test name
Test status
Simulation time 161324205527 ps
CPU time 367.09 seconds
Started Jun 24 05:56:46 PM PDT 24
Finished Jun 24 06:02:53 PM PDT 24
Peak memory 202160 kb
Host smart-29fc9a64-9261-4036-b7c9-dd3b61e85f55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240230551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.4240230551
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1320560946
Short name T298
Test name
Test status
Simulation time 336911799373 ps
CPU time 345.59 seconds
Started Jun 24 05:56:45 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 202276 kb
Host smart-c7785174-8012-496e-8c75-d6c4a0e91db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320560946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1320560946
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2781802230
Short name T627
Test name
Test status
Simulation time 324319134318 ps
CPU time 754.74 seconds
Started Jun 24 05:56:44 PM PDT 24
Finished Jun 24 06:09:20 PM PDT 24
Peak memory 202260 kb
Host smart-218a62da-db12-4286-9725-dd662891ce04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781802230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2781802230
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1762449130
Short name T474
Test name
Test status
Simulation time 177715562238 ps
CPU time 29.29 seconds
Started Jun 24 05:56:45 PM PDT 24
Finished Jun 24 05:57:15 PM PDT 24
Peak memory 202276 kb
Host smart-f19badaf-c796-4961-a72d-d4fd7f73aa3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762449130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1762449130
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.505069843
Short name T515
Test name
Test status
Simulation time 610183958612 ps
CPU time 1397.61 seconds
Started Jun 24 05:56:45 PM PDT 24
Finished Jun 24 06:20:04 PM PDT 24
Peak memory 202096 kb
Host smart-c5ee6c35-271a-47db-a8dc-753b1e74416c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505069843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.505069843
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3359030848
Short name T780
Test name
Test status
Simulation time 35398774805 ps
CPU time 76.54 seconds
Started Jun 24 05:56:53 PM PDT 24
Finished Jun 24 05:58:10 PM PDT 24
Peak memory 202000 kb
Host smart-4d377e7e-1569-456b-a376-119512b8992e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359030848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3359030848
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2306932924
Short name T343
Test name
Test status
Simulation time 4951605716 ps
CPU time 12.66 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 05:57:15 PM PDT 24
Peak memory 202040 kb
Host smart-e3ade7c2-1117-4bfd-bd25-f1a62777101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306932924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2306932924
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.385703626
Short name T363
Test name
Test status
Simulation time 5701877877 ps
CPU time 2.46 seconds
Started Jun 24 05:56:45 PM PDT 24
Finished Jun 24 05:56:48 PM PDT 24
Peak memory 202012 kb
Host smart-b181d3f6-e862-401b-9ffd-cb130259f0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385703626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.385703626
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.774062445
Short name T538
Test name
Test status
Simulation time 259192627406 ps
CPU time 892.72 seconds
Started Jun 24 05:56:52 PM PDT 24
Finished Jun 24 06:11:45 PM PDT 24
Peak memory 210780 kb
Host smart-bec9bacb-561c-4d1a-8e80-fb1f9daaa301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774062445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
774062445
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2061077178
Short name T319
Test name
Test status
Simulation time 167975541859 ps
CPU time 282.04 seconds
Started Jun 24 05:56:53 PM PDT 24
Finished Jun 24 06:01:36 PM PDT 24
Peak memory 210832 kb
Host smart-62e3cd85-5ce8-4ac9-b67b-d81ceb70f1e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061077178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2061077178
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1477525939
Short name T552
Test name
Test status
Simulation time 370371171 ps
CPU time 1.49 seconds
Started Jun 24 05:57:01 PM PDT 24
Finished Jun 24 05:57:03 PM PDT 24
Peak memory 201904 kb
Host smart-1b4c4942-1876-44a7-8eb2-40bc99191dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477525939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1477525939
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1864122695
Short name T644
Test name
Test status
Simulation time 337914395421 ps
CPU time 846.33 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 06:11:10 PM PDT 24
Peak memory 202196 kb
Host smart-dda310e9-74ce-4d1a-b6b8-5d58b94600e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864122695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1864122695
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2533979039
Short name T195
Test name
Test status
Simulation time 165696874411 ps
CPU time 97.1 seconds
Started Jun 24 05:56:53 PM PDT 24
Finished Jun 24 05:58:30 PM PDT 24
Peak memory 202284 kb
Host smart-3301a3fb-dc1d-4932-9fad-1192cea4169c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533979039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2533979039
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2112275260
Short name T747
Test name
Test status
Simulation time 162754125096 ps
CPU time 368.01 seconds
Started Jun 24 05:56:53 PM PDT 24
Finished Jun 24 06:03:02 PM PDT 24
Peak memory 202232 kb
Host smart-7840a88b-f701-425b-919f-964803f8e295
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112275260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2112275260
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2534432020
Short name T273
Test name
Test status
Simulation time 335321582514 ps
CPU time 371.19 seconds
Started Jun 24 05:57:04 PM PDT 24
Finished Jun 24 06:03:16 PM PDT 24
Peak memory 202260 kb
Host smart-2747abc9-5573-4e57-bb18-a15fb79b1f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534432020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2534432020
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1991533479
Short name T348
Test name
Test status
Simulation time 330873142889 ps
CPU time 776.02 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 06:09:59 PM PDT 24
Peak memory 202204 kb
Host smart-5240ab1e-422e-4ccc-9c5b-73eab2be4b02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991533479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1991533479
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2062229358
Short name T551
Test name
Test status
Simulation time 195735185327 ps
CPU time 119.69 seconds
Started Jun 24 05:56:53 PM PDT 24
Finished Jun 24 05:58:54 PM PDT 24
Peak memory 202196 kb
Host smart-2e01228b-95b4-447d-acc8-9572bbe7232a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062229358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2062229358
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1953060207
Short name T479
Test name
Test status
Simulation time 598848475945 ps
CPU time 1236.33 seconds
Started Jun 24 05:57:01 PM PDT 24
Finished Jun 24 06:17:39 PM PDT 24
Peak memory 202236 kb
Host smart-9f05dc5a-48a5-47a9-972f-8033248acbbc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953060207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1953060207
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1727466390
Short name T58
Test name
Test status
Simulation time 82715877282 ps
CPU time 351.2 seconds
Started Jun 24 05:57:01 PM PDT 24
Finished Jun 24 06:02:53 PM PDT 24
Peak memory 202572 kb
Host smart-31afb4d9-77a4-44fa-90b9-c3854b6529d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727466390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1727466390
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2830296784
Short name T550
Test name
Test status
Simulation time 23341992743 ps
CPU time 53.8 seconds
Started Jun 24 05:57:01 PM PDT 24
Finished Jun 24 05:57:56 PM PDT 24
Peak memory 202060 kb
Host smart-54b3f707-6859-4269-8d7a-ef1328645277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830296784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2830296784
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3856306344
Short name T524
Test name
Test status
Simulation time 4218803346 ps
CPU time 2.94 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 05:57:05 PM PDT 24
Peak memory 202032 kb
Host smart-0a573e4b-e84e-4c64-b68f-7f790c29ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856306344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3856306344
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1855444041
Short name T744
Test name
Test status
Simulation time 5966242904 ps
CPU time 14.62 seconds
Started Jun 24 05:56:53 PM PDT 24
Finished Jun 24 05:57:08 PM PDT 24
Peak memory 201988 kb
Host smart-8af6901b-b682-42d0-9217-06ee61119322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855444041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1855444041
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4167821312
Short name T270
Test name
Test status
Simulation time 327261251524 ps
CPU time 709.05 seconds
Started Jun 24 05:57:03 PM PDT 24
Finished Jun 24 06:08:53 PM PDT 24
Peak memory 202392 kb
Host smart-2bb633d3-7c97-47e3-a2f6-12675ff98edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167821312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4167821312
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3111964900
Short name T41
Test name
Test status
Simulation time 107271901897 ps
CPU time 285.04 seconds
Started Jun 24 05:57:01 PM PDT 24
Finished Jun 24 06:01:47 PM PDT 24
Peak memory 210904 kb
Host smart-13949cd2-34fb-47b9-9ec2-2896c85ccf2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111964900 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3111964900
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.795638631
Short name T354
Test name
Test status
Simulation time 410283645 ps
CPU time 1.12 seconds
Started Jun 24 05:57:15 PM PDT 24
Finished Jun 24 05:57:17 PM PDT 24
Peak memory 201880 kb
Host smart-01369949-e968-4126-8d8d-bbb6e7ef112f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795638631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.795638631
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2662762202
Short name T503
Test name
Test status
Simulation time 594948346256 ps
CPU time 1170.94 seconds
Started Jun 24 05:57:05 PM PDT 24
Finished Jun 24 06:16:36 PM PDT 24
Peak memory 202216 kb
Host smart-9234ed73-92b4-4a54-b6ef-6c325d40c9e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662762202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2662762202
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2978010980
Short name T686
Test name
Test status
Simulation time 164886622063 ps
CPU time 359.84 seconds
Started Jun 24 05:57:07 PM PDT 24
Finished Jun 24 06:03:08 PM PDT 24
Peak memory 202300 kb
Host smart-13a08cc4-cb04-4bfe-8c3b-335322650aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978010980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2978010980
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1583842347
Short name T702
Test name
Test status
Simulation time 169598657424 ps
CPU time 109.73 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 05:58:53 PM PDT 24
Peak memory 202264 kb
Host smart-d3f82ccd-4553-4530-8ffe-8758b2f4400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583842347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1583842347
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1252331718
Short name T772
Test name
Test status
Simulation time 159911238458 ps
CPU time 92.38 seconds
Started Jun 24 05:57:01 PM PDT 24
Finished Jun 24 05:58:34 PM PDT 24
Peak memory 202180 kb
Host smart-b39c4006-6856-4b87-b605-0f2fc369f0bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252331718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1252331718
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4261685584
Short name T200
Test name
Test status
Simulation time 332838208668 ps
CPU time 110.08 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 05:58:53 PM PDT 24
Peak memory 202220 kb
Host smart-cefedbba-69f9-403d-8bee-900743e4b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261685584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4261685584
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2179430030
Short name T532
Test name
Test status
Simulation time 500622981137 ps
CPU time 1057.69 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 06:14:41 PM PDT 24
Peak memory 202164 kb
Host smart-17267603-6068-4f54-8750-29b5650c9925
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179430030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2179430030
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.920932677
Short name T739
Test name
Test status
Simulation time 184191278571 ps
CPU time 63.09 seconds
Started Jun 24 05:57:00 PM PDT 24
Finished Jun 24 05:58:04 PM PDT 24
Peak memory 202168 kb
Host smart-364a6573-cbc9-4243-aa01-c98ac1777a41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920932677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.920932677
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2211819233
Short name T660
Test name
Test status
Simulation time 402575771238 ps
CPU time 219.67 seconds
Started Jun 24 05:57:01 PM PDT 24
Finished Jun 24 06:00:41 PM PDT 24
Peak memory 202192 kb
Host smart-43946362-ba92-49af-827b-3a8aa05b603f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211819233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2211819233
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3186034533
Short name T430
Test name
Test status
Simulation time 137150713273 ps
CPU time 677.28 seconds
Started Jun 24 05:57:15 PM PDT 24
Finished Jun 24 06:08:33 PM PDT 24
Peak memory 202592 kb
Host smart-0df8c316-a6ed-4462-afeb-80bd5e9ca01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186034533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3186034533
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2620388218
Short name T511
Test name
Test status
Simulation time 39660233362 ps
CPU time 47.51 seconds
Started Jun 24 05:57:13 PM PDT 24
Finished Jun 24 05:58:02 PM PDT 24
Peak memory 202044 kb
Host smart-cc3eee93-a04d-48fb-af04-f877208f94af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620388218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2620388218
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2345917828
Short name T726
Test name
Test status
Simulation time 4560631024 ps
CPU time 2.1 seconds
Started Jun 24 05:57:02 PM PDT 24
Finished Jun 24 05:57:05 PM PDT 24
Peak memory 201996 kb
Host smart-bb5175ec-abc3-4266-a2d3-7775ff0e7e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345917828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2345917828
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1838716331
Short name T121
Test name
Test status
Simulation time 5582796845 ps
CPU time 12.83 seconds
Started Jun 24 05:57:01 PM PDT 24
Finished Jun 24 05:57:14 PM PDT 24
Peak memory 202272 kb
Host smart-4987b102-789b-4c65-8e36-383f2ad10b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838716331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1838716331
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.925189125
Short name T520
Test name
Test status
Simulation time 225198135069 ps
CPU time 132.05 seconds
Started Jun 24 05:57:12 PM PDT 24
Finished Jun 24 05:59:25 PM PDT 24
Peak memory 202264 kb
Host smart-62c7aaaf-d93e-44dc-ae29-f15f6a92f0a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925189125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
925189125
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3640198424
Short name T463
Test name
Test status
Simulation time 467028810 ps
CPU time 0.85 seconds
Started Jun 24 05:57:22 PM PDT 24
Finished Jun 24 05:57:24 PM PDT 24
Peak memory 201900 kb
Host smart-e2bae8d4-6259-4a7a-a1c7-1f950ede229d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640198424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3640198424
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.391427708
Short name T278
Test name
Test status
Simulation time 334821389664 ps
CPU time 249.03 seconds
Started Jun 24 05:57:13 PM PDT 24
Finished Jun 24 06:01:23 PM PDT 24
Peak memory 202280 kb
Host smart-bd264c25-62ee-43bf-9f65-346d2a546db6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391427708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.391427708
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.695234338
Short name T577
Test name
Test status
Simulation time 161394148561 ps
CPU time 378.77 seconds
Started Jun 24 05:57:11 PM PDT 24
Finished Jun 24 06:03:31 PM PDT 24
Peak memory 202260 kb
Host smart-0cec9011-4a0a-44ed-a4b7-16eaae63aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695234338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.695234338
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3206794862
Short name T212
Test name
Test status
Simulation time 495781757408 ps
CPU time 278.21 seconds
Started Jun 24 05:57:15 PM PDT 24
Finished Jun 24 06:01:54 PM PDT 24
Peak memory 202204 kb
Host smart-5904c399-bf92-49b1-bdc3-7ba9510a1796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206794862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3206794862
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1496745874
Short name T578
Test name
Test status
Simulation time 487505200989 ps
CPU time 239.71 seconds
Started Jun 24 05:57:13 PM PDT 24
Finished Jun 24 06:01:14 PM PDT 24
Peak memory 202244 kb
Host smart-6bb5e283-a81b-4d51-bbda-6484eac950ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496745874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1496745874
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3751323049
Short name T741
Test name
Test status
Simulation time 162573405366 ps
CPU time 329.18 seconds
Started Jun 24 05:57:13 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 202256 kb
Host smart-cc4a753e-4be6-4d3a-9c22-8adba86f3c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751323049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3751323049
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2134650587
Short name T431
Test name
Test status
Simulation time 485984084325 ps
CPU time 283.01 seconds
Started Jun 24 05:57:13 PM PDT 24
Finished Jun 24 06:01:57 PM PDT 24
Peak memory 202276 kb
Host smart-aa66c91a-edf0-4a46-aa4a-794f6fad8d2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134650587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2134650587
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2875972103
Short name T547
Test name
Test status
Simulation time 605031749714 ps
CPU time 1307.01 seconds
Started Jun 24 05:57:13 PM PDT 24
Finished Jun 24 06:19:01 PM PDT 24
Peak memory 202176 kb
Host smart-dda92169-512e-4885-8ce6-764af1ea4d4a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875972103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2875972103
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3677009341
Short name T114
Test name
Test status
Simulation time 123692051447 ps
CPU time 663.22 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 06:08:25 PM PDT 24
Peak memory 202588 kb
Host smart-395071d2-9d8d-438d-a8a6-ac80bf1181ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677009341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3677009341
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1802049893
Short name T481
Test name
Test status
Simulation time 30667275874 ps
CPU time 34.96 seconds
Started Jun 24 05:57:23 PM PDT 24
Finished Jun 24 05:57:59 PM PDT 24
Peak memory 202040 kb
Host smart-c6e65fe1-4333-4a49-84a9-a42996c49cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802049893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1802049893
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3468776210
Short name T648
Test name
Test status
Simulation time 2879881049 ps
CPU time 7.47 seconds
Started Jun 24 05:57:14 PM PDT 24
Finished Jun 24 05:57:23 PM PDT 24
Peak memory 202008 kb
Host smart-be3b367e-fd42-45ed-8af7-f46050e4d51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468776210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3468776210
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3695391703
Short name T506
Test name
Test status
Simulation time 5795008924 ps
CPU time 4.83 seconds
Started Jun 24 05:57:12 PM PDT 24
Finished Jun 24 05:57:18 PM PDT 24
Peak memory 202012 kb
Host smart-ce54bb1f-a4bf-447b-9e95-8b26af89bdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695391703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3695391703
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2128667563
Short name T777
Test name
Test status
Simulation time 4580610197 ps
CPU time 10.9 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 05:57:32 PM PDT 24
Peak memory 202036 kb
Host smart-0967ffde-c0eb-46e6-8138-ea9d71a76f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128667563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2128667563
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.863485089
Short name T494
Test name
Test status
Simulation time 315575554 ps
CPU time 1.37 seconds
Started Jun 24 05:57:23 PM PDT 24
Finished Jun 24 05:57:25 PM PDT 24
Peak memory 201900 kb
Host smart-87c42a4a-91a3-41b2-ab57-78e7d16cb931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863485089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.863485089
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.718491848
Short name T757
Test name
Test status
Simulation time 491576807867 ps
CPU time 141.22 seconds
Started Jun 24 05:57:23 PM PDT 24
Finished Jun 24 05:59:45 PM PDT 24
Peak memory 202240 kb
Host smart-fdfe6e2f-096c-4660-958a-20420e44188a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718491848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.718491848
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3448512973
Short name T160
Test name
Test status
Simulation time 370994641219 ps
CPU time 229.67 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 06:01:12 PM PDT 24
Peak memory 202200 kb
Host smart-4e21fb49-fbfd-4e3c-87e1-ce67182df860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448512973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3448512973
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2897990457
Short name T118
Test name
Test status
Simulation time 488563368442 ps
CPU time 260.18 seconds
Started Jun 24 05:57:20 PM PDT 24
Finished Jun 24 06:01:41 PM PDT 24
Peak memory 202184 kb
Host smart-ef413c4c-0cc5-4e2a-9cc2-5546e834546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897990457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2897990457
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1317055284
Short name T269
Test name
Test status
Simulation time 166524044221 ps
CPU time 417.06 seconds
Started Jun 24 05:57:22 PM PDT 24
Finished Jun 24 06:04:20 PM PDT 24
Peak memory 202196 kb
Host smart-0c87d9e6-f175-4911-9eb7-4573acfe1834
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317055284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1317055284
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1909419656
Short name T746
Test name
Test status
Simulation time 496385349927 ps
CPU time 309.98 seconds
Started Jun 24 05:57:23 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 202180 kb
Host smart-18937b3a-7b7d-46d5-8147-fa30eb658e2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909419656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1909419656
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1246296716
Short name T584
Test name
Test status
Simulation time 199985035850 ps
CPU time 281.14 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 06:02:03 PM PDT 24
Peak memory 202268 kb
Host smart-60dbf60a-0e86-4ee9-81e7-fe427e1686bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246296716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1246296716
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3682613310
Short name T640
Test name
Test status
Simulation time 604465016457 ps
CPU time 326.25 seconds
Started Jun 24 05:57:20 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 202108 kb
Host smart-8914b004-b1ce-4207-9610-f8605f01eb28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682613310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3682613310
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.849641318
Short name T55
Test name
Test status
Simulation time 95592675240 ps
CPU time 525.42 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 06:06:07 PM PDT 24
Peak memory 202592 kb
Host smart-c1fde7ea-2383-4a17-85fe-7fcfd753c885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849641318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.849641318
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.110206750
Short name T631
Test name
Test status
Simulation time 46651312749 ps
CPU time 98.46 seconds
Started Jun 24 05:57:22 PM PDT 24
Finished Jun 24 05:59:01 PM PDT 24
Peak memory 202272 kb
Host smart-fa40e2bf-575d-4dc5-a853-015ebb29e350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110206750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.110206750
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2183880753
Short name T519
Test name
Test status
Simulation time 5417572263 ps
CPU time 13 seconds
Started Jun 24 05:57:22 PM PDT 24
Finished Jun 24 05:57:35 PM PDT 24
Peak memory 202016 kb
Host smart-e9e50bbb-2b5e-4dfe-b3c2-3d55d08fe7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183880753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2183880753
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3070948353
Short name T9
Test name
Test status
Simulation time 5773110210 ps
CPU time 7.64 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 05:57:30 PM PDT 24
Peak memory 202012 kb
Host smart-a0c2c6b4-9fda-4bba-97bf-52f516f11684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070948353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3070948353
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3505320987
Short name T668
Test name
Test status
Simulation time 209448734922 ps
CPU time 442.21 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 06:04:44 PM PDT 24
Peak memory 202200 kb
Host smart-0ad0a559-6312-4140-ae05-6e5cc7081ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505320987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3505320987
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.197225860
Short name T94
Test name
Test status
Simulation time 93086498010 ps
CPU time 101.49 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 05:59:03 PM PDT 24
Peak memory 210600 kb
Host smart-4c94e44a-2a8d-48dd-9a50-c85d716e3c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197225860 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.197225860
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2869327239
Short name T769
Test name
Test status
Simulation time 394770621 ps
CPU time 0.87 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:55:15 PM PDT 24
Peak memory 201832 kb
Host smart-b4fd092d-e13c-4ff9-af29-28205e1c8e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869327239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2869327239
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1775062000
Short name T654
Test name
Test status
Simulation time 187638571247 ps
CPU time 106.22 seconds
Started Jun 24 05:55:14 PM PDT 24
Finished Jun 24 05:57:02 PM PDT 24
Peak memory 202188 kb
Host smart-1efcbdc4-b328-4f42-bbf6-4578d2dff817
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775062000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1775062000
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1982504977
Short name T316
Test name
Test status
Simulation time 168703131059 ps
CPU time 101.21 seconds
Started Jun 24 05:55:12 PM PDT 24
Finished Jun 24 05:56:55 PM PDT 24
Peak memory 202224 kb
Host smart-28fd741a-8e9c-4d5f-9a02-332ea23fec87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982504977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1982504977
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.4015938682
Short name T762
Test name
Test status
Simulation time 165408300527 ps
CPU time 93.12 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:56:46 PM PDT 24
Peak memory 202252 kb
Host smart-80168635-d5f8-4d84-8f7e-0118e7377fd9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015938682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.4015938682
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.378773109
Short name T561
Test name
Test status
Simulation time 325938256601 ps
CPU time 347.5 seconds
Started Jun 24 05:55:12 PM PDT 24
Finished Jun 24 06:01:02 PM PDT 24
Peak memory 202288 kb
Host smart-d1d807f6-4c84-45d0-bb25-8a87b85b22b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378773109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.378773109
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.4277469279
Short name T499
Test name
Test status
Simulation time 157055605029 ps
CPU time 333.79 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 06:00:48 PM PDT 24
Peak memory 202108 kb
Host smart-ecbeadde-b2a6-45b1-af94-410fdfee4d24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277469279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.4277469279
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1940873596
Short name T241
Test name
Test status
Simulation time 359872036683 ps
CPU time 875.72 seconds
Started Jun 24 05:55:17 PM PDT 24
Finished Jun 24 06:09:54 PM PDT 24
Peak memory 202240 kb
Host smart-476c2b80-da21-4311-91fc-6340ff1b610b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940873596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1940873596
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3646890546
Short name T360
Test name
Test status
Simulation time 198334748139 ps
CPU time 245.49 seconds
Started Jun 24 05:55:13 PM PDT 24
Finished Jun 24 05:59:21 PM PDT 24
Peak memory 202180 kb
Host smart-75986308-f03e-4bc4-b880-bfcfd2df1940
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646890546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3646890546
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2003624171
Short name T57
Test name
Test status
Simulation time 80038574584 ps
CPU time 294.92 seconds
Started Jun 24 05:55:17 PM PDT 24
Finished Jun 24 06:00:13 PM PDT 24
Peak memory 202512 kb
Host smart-889fadfb-9b39-4d02-8087-9c48b467b183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003624171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2003624171
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2300118442
Short name T473
Test name
Test status
Simulation time 37412260895 ps
CPU time 22.63 seconds
Started Jun 24 05:55:17 PM PDT 24
Finished Jun 24 05:55:40 PM PDT 24
Peak memory 202016 kb
Host smart-d086edf5-9e2e-40d8-babf-145d763290c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300118442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2300118442
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1999694405
Short name T581
Test name
Test status
Simulation time 3323243186 ps
CPU time 4.57 seconds
Started Jun 24 05:55:12 PM PDT 24
Finished Jun 24 05:55:19 PM PDT 24
Peak memory 202272 kb
Host smart-98977d9f-3526-42b7-8fb3-08d14294fe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999694405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1999694405
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.300922374
Short name T71
Test name
Test status
Simulation time 8576885243 ps
CPU time 5.87 seconds
Started Jun 24 05:55:18 PM PDT 24
Finished Jun 24 05:55:24 PM PDT 24
Peak memory 218784 kb
Host smart-2bcae6b1-dbd9-4de3-9416-868e82f393f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300922374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.300922374
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1953036813
Short name T85
Test name
Test status
Simulation time 5937413273 ps
CPU time 1.88 seconds
Started Jun 24 05:55:17 PM PDT 24
Finished Jun 24 05:55:20 PM PDT 24
Peak memory 202020 kb
Host smart-8d289a94-aa5b-43ac-b66b-4d95d06f026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953036813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1953036813
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3339951308
Short name T123
Test name
Test status
Simulation time 79377057348 ps
CPU time 259.79 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 05:59:33 PM PDT 24
Peak memory 202568 kb
Host smart-00deeb24-8582-455f-a4e4-5022bdb257f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339951308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3339951308
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.699267310
Short name T44
Test name
Test status
Simulation time 201740351667 ps
CPU time 81.23 seconds
Started Jun 24 05:55:19 PM PDT 24
Finished Jun 24 05:56:41 PM PDT 24
Peak memory 210588 kb
Host smart-1bcf686b-ead4-4c5b-8dc5-1e584e7641f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699267310 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.699267310
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.4165413853
Short name T408
Test name
Test status
Simulation time 339013132 ps
CPU time 1.36 seconds
Started Jun 24 05:57:31 PM PDT 24
Finished Jun 24 05:57:33 PM PDT 24
Peak memory 201908 kb
Host smart-136987ae-3b13-4087-b708-23a3eff7333a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165413853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.4165413853
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.4063647058
Short name T682
Test name
Test status
Simulation time 550767912768 ps
CPU time 133.68 seconds
Started Jun 24 05:57:29 PM PDT 24
Finished Jun 24 05:59:44 PM PDT 24
Peak memory 202216 kb
Host smart-68ca3748-8654-495a-8633-a4562e496cf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063647058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.4063647058
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1193283787
Short name T294
Test name
Test status
Simulation time 182794370645 ps
CPU time 207.7 seconds
Started Jun 24 05:57:34 PM PDT 24
Finished Jun 24 06:01:02 PM PDT 24
Peak memory 202200 kb
Host smart-5b723702-cf20-4eb8-83bb-a4cb38576072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193283787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1193283787
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3841032049
Short name T514
Test name
Test status
Simulation time 167655804822 ps
CPU time 362.5 seconds
Started Jun 24 05:57:32 PM PDT 24
Finished Jun 24 06:03:36 PM PDT 24
Peak memory 202240 kb
Host smart-22e89441-6562-48e8-b3ce-329b2784bb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841032049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3841032049
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3687927147
Short name T395
Test name
Test status
Simulation time 161823983737 ps
CPU time 141.66 seconds
Started Jun 24 05:57:32 PM PDT 24
Finished Jun 24 05:59:55 PM PDT 24
Peak memory 202164 kb
Host smart-510f6348-e539-4836-8073-f8aba6acb04a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687927147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3687927147
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1778710520
Short name T317
Test name
Test status
Simulation time 164666415319 ps
CPU time 354.36 seconds
Started Jun 24 05:57:34 PM PDT 24
Finished Jun 24 06:03:28 PM PDT 24
Peak memory 202208 kb
Host smart-a03e6ae1-f987-4e84-9108-e76541fe21f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778710520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1778710520
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3256698326
Short name T444
Test name
Test status
Simulation time 487480083600 ps
CPU time 1049.69 seconds
Started Jun 24 05:57:30 PM PDT 24
Finished Jun 24 06:15:01 PM PDT 24
Peak memory 202176 kb
Host smart-43968493-a75c-47a3-9ea0-3df55ec14ce1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256698326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3256698326
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1217970634
Short name T324
Test name
Test status
Simulation time 459145318211 ps
CPU time 535.46 seconds
Started Jun 24 05:57:31 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 202124 kb
Host smart-0e7f7685-d8a8-41f5-8259-09001e3031a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217970634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1217970634
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3025380395
Short name T683
Test name
Test status
Simulation time 399298265097 ps
CPU time 434.38 seconds
Started Jun 24 05:57:29 PM PDT 24
Finished Jun 24 06:04:44 PM PDT 24
Peak memory 202256 kb
Host smart-7b973a8e-2c48-4a6b-91fd-ad24c41da04c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025380395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3025380395
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.698188240
Short name T377
Test name
Test status
Simulation time 100774738289 ps
CPU time 575.56 seconds
Started Jun 24 05:57:31 PM PDT 24
Finished Jun 24 06:07:07 PM PDT 24
Peak memory 202592 kb
Host smart-4a0b41da-2a56-4982-aa3f-5a92e12d510c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698188240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.698188240
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2704743944
Short name T667
Test name
Test status
Simulation time 35492097742 ps
CPU time 75.87 seconds
Started Jun 24 05:57:31 PM PDT 24
Finished Jun 24 05:58:48 PM PDT 24
Peak memory 202064 kb
Host smart-ff37e289-f834-4f17-98c6-6e1936baa78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704743944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2704743944
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.4247237811
Short name T457
Test name
Test status
Simulation time 2968522817 ps
CPU time 1.72 seconds
Started Jun 24 05:57:29 PM PDT 24
Finished Jun 24 05:57:31 PM PDT 24
Peak memory 202020 kb
Host smart-a634814f-775d-4023-ab83-7dbc5bd80963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247237811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.4247237811
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1518089217
Short name T517
Test name
Test status
Simulation time 5987906992 ps
CPU time 14.31 seconds
Started Jun 24 05:57:21 PM PDT 24
Finished Jun 24 05:57:36 PM PDT 24
Peak memory 202024 kb
Host smart-b257f92e-4ba2-4326-87fc-4811c012a45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518089217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1518089217
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2924144621
Short name T485
Test name
Test status
Simulation time 9426198427 ps
CPU time 22.31 seconds
Started Jun 24 05:57:31 PM PDT 24
Finished Jun 24 05:57:54 PM PDT 24
Peak memory 202024 kb
Host smart-e300f508-c37d-41ec-9109-e1b714660c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924144621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2924144621
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1944424222
Short name T699
Test name
Test status
Simulation time 94722884975 ps
CPU time 255.7 seconds
Started Jun 24 05:57:30 PM PDT 24
Finished Jun 24 06:01:46 PM PDT 24
Peak memory 210812 kb
Host smart-e38eb39f-57d5-4565-b562-a4846776bb73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944424222 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1944424222
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3768780417
Short name T49
Test name
Test status
Simulation time 474744993 ps
CPU time 1.67 seconds
Started Jun 24 05:57:49 PM PDT 24
Finished Jun 24 05:57:51 PM PDT 24
Peak memory 201904 kb
Host smart-28f4ae98-250c-4176-9ecc-74593625416c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768780417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3768780417
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.359639174
Short name T7
Test name
Test status
Simulation time 170658866002 ps
CPU time 419.07 seconds
Started Jun 24 05:57:38 PM PDT 24
Finished Jun 24 06:04:37 PM PDT 24
Peak memory 202292 kb
Host smart-ee0fe06c-7d05-4f07-9929-8f61255df287
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359639174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.359639174
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2690118628
Short name T263
Test name
Test status
Simulation time 262178670889 ps
CPU time 564.56 seconds
Started Jun 24 05:57:38 PM PDT 24
Finished Jun 24 06:07:03 PM PDT 24
Peak memory 202280 kb
Host smart-771df84c-7b5d-4a01-b9f9-76fedd48f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690118628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2690118628
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4177143011
Short name T464
Test name
Test status
Simulation time 495369565094 ps
CPU time 1078.56 seconds
Started Jun 24 05:57:38 PM PDT 24
Finished Jun 24 06:15:37 PM PDT 24
Peak memory 202256 kb
Host smart-f8ee1ae9-5983-421f-820c-bba4267321ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177143011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4177143011
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2907439573
Short name T92
Test name
Test status
Simulation time 321375811348 ps
CPU time 776.03 seconds
Started Jun 24 05:57:40 PM PDT 24
Finished Jun 24 06:10:36 PM PDT 24
Peak memory 202268 kb
Host smart-73f31060-61e4-421b-af4b-b86147ee83c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907439573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2907439573
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2333255580
Short name T1
Test name
Test status
Simulation time 505582150077 ps
CPU time 583.45 seconds
Started Jun 24 05:57:39 PM PDT 24
Finished Jun 24 06:07:23 PM PDT 24
Peak memory 202176 kb
Host smart-e0066fd3-d78b-41f2-aa01-34d71ec75559
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333255580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2333255580
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3934942588
Short name T493
Test name
Test status
Simulation time 383716569231 ps
CPU time 73.81 seconds
Started Jun 24 05:57:40 PM PDT 24
Finished Jun 24 05:58:54 PM PDT 24
Peak memory 202256 kb
Host smart-53185f2e-2537-46fa-84ae-7ccf319bb7cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934942588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3934942588
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1685077675
Short name T336
Test name
Test status
Simulation time 116006297475 ps
CPU time 456.15 seconds
Started Jun 24 05:57:38 PM PDT 24
Finished Jun 24 06:05:14 PM PDT 24
Peak memory 202588 kb
Host smart-db825de1-733b-457d-959d-29e37bd84da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685077675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1685077675
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2723768611
Short name T364
Test name
Test status
Simulation time 32718236115 ps
CPU time 72.28 seconds
Started Jun 24 05:57:40 PM PDT 24
Finished Jun 24 05:58:53 PM PDT 24
Peak memory 202216 kb
Host smart-591336dd-f907-4cc0-a8e9-9fd6b26baada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723768611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2723768611
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2077016534
Short name T706
Test name
Test status
Simulation time 4089159783 ps
CPU time 2.9 seconds
Started Jun 24 05:57:40 PM PDT 24
Finished Jun 24 05:57:43 PM PDT 24
Peak memory 202024 kb
Host smart-08f33da3-2a52-4427-b6c7-4b80421c3a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077016534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2077016534
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2200162113
Short name T788
Test name
Test status
Simulation time 5953873401 ps
CPU time 12.91 seconds
Started Jun 24 05:57:34 PM PDT 24
Finished Jun 24 05:57:48 PM PDT 24
Peak memory 202012 kb
Host smart-aa218c93-ff3c-4c96-8ab1-8e1530a62356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200162113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2200162113
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3572864942
Short name T411
Test name
Test status
Simulation time 5594459858 ps
CPU time 3.74 seconds
Started Jun 24 05:57:46 PM PDT 24
Finished Jun 24 05:57:50 PM PDT 24
Peak memory 201948 kb
Host smart-2d483526-a13c-41cd-b08b-5d3bcdf80191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572864942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3572864942
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.4172507921
Short name T107
Test name
Test status
Simulation time 929332198783 ps
CPU time 183.94 seconds
Started Jun 24 05:57:47 PM PDT 24
Finished Jun 24 06:00:52 PM PDT 24
Peak memory 210544 kb
Host smart-84e3629f-be07-4566-8430-f7c429a845eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172507921 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.4172507921
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1972322689
Short name T677
Test name
Test status
Simulation time 373186740 ps
CPU time 1.45 seconds
Started Jun 24 05:57:57 PM PDT 24
Finished Jun 24 05:57:59 PM PDT 24
Peak memory 201896 kb
Host smart-129d1520-c81e-4280-acf9-597772b96990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972322689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1972322689
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1311434033
Short name T566
Test name
Test status
Simulation time 165334462271 ps
CPU time 368.45 seconds
Started Jun 24 05:57:45 PM PDT 24
Finished Jun 24 06:03:54 PM PDT 24
Peak memory 202312 kb
Host smart-6f6a109c-f2ca-425f-88ed-662a43503935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311434033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1311434033
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.452655762
Short name T397
Test name
Test status
Simulation time 169247693165 ps
CPU time 232.41 seconds
Started Jun 24 05:57:48 PM PDT 24
Finished Jun 24 06:01:41 PM PDT 24
Peak memory 202216 kb
Host smart-0493ef60-6133-4fe6-a00e-c5d013b14de1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=452655762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.452655762
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3135846481
Short name T419
Test name
Test status
Simulation time 160079128035 ps
CPU time 94.77 seconds
Started Jun 24 05:57:47 PM PDT 24
Finished Jun 24 05:59:23 PM PDT 24
Peak memory 202232 kb
Host smart-dce1ee41-b8e1-45c7-b20d-2180592c84ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135846481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3135846481
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1902961394
Short name T321
Test name
Test status
Simulation time 263474717686 ps
CPU time 296.43 seconds
Started Jun 24 05:57:48 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 202272 kb
Host smart-49b26394-a105-4ef9-980b-063bd165aeb6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902961394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1902961394
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3223639635
Short name T369
Test name
Test status
Simulation time 399306320493 ps
CPU time 248.55 seconds
Started Jun 24 05:57:48 PM PDT 24
Finished Jun 24 06:01:57 PM PDT 24
Peak memory 202252 kb
Host smart-d2845f72-667f-4858-945c-0a4417e54abb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223639635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3223639635
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3137886372
Short name T733
Test name
Test status
Simulation time 116597223454 ps
CPU time 387.89 seconds
Started Jun 24 05:57:57 PM PDT 24
Finished Jun 24 06:04:26 PM PDT 24
Peak memory 202748 kb
Host smart-39c8229e-68d2-42fd-bf14-6a4812702299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137886372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3137886372
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2792193526
Short name T490
Test name
Test status
Simulation time 34670633593 ps
CPU time 40.76 seconds
Started Jun 24 05:57:55 PM PDT 24
Finished Jun 24 05:58:37 PM PDT 24
Peak memory 202084 kb
Host smart-449b4164-b6d3-4cb9-8dc7-7c54f3dd93b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792193526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2792193526
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2445747089
Short name T365
Test name
Test status
Simulation time 5376822154 ps
CPU time 3.83 seconds
Started Jun 24 05:57:55 PM PDT 24
Finished Jun 24 05:57:59 PM PDT 24
Peak memory 202024 kb
Host smart-da030dcf-9ef2-4b7d-bfdd-e2156bced848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445747089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2445747089
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2865884156
Short name T370
Test name
Test status
Simulation time 5902431990 ps
CPU time 5.53 seconds
Started Jun 24 05:57:45 PM PDT 24
Finished Jun 24 05:57:52 PM PDT 24
Peak memory 201992 kb
Host smart-f8e342f5-5998-48d0-95f8-2668e3c1b50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865884156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2865884156
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3813083163
Short name T254
Test name
Test status
Simulation time 590426178418 ps
CPU time 1289.97 seconds
Started Jun 24 05:57:55 PM PDT 24
Finished Jun 24 06:19:26 PM PDT 24
Peak memory 202284 kb
Host smart-8ebe2b07-04c1-45f6-b300-03aadda531cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813083163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3813083163
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.221806249
Short name T21
Test name
Test status
Simulation time 50962617243 ps
CPU time 127.48 seconds
Started Jun 24 05:57:57 PM PDT 24
Finished Jun 24 06:00:05 PM PDT 24
Peak memory 211148 kb
Host smart-87b8e85a-f3cb-447d-a1af-3b7634e7b865
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221806249 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.221806249
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.907840445
Short name T127
Test name
Test status
Simulation time 421046227 ps
CPU time 0.85 seconds
Started Jun 24 05:58:04 PM PDT 24
Finished Jun 24 05:58:05 PM PDT 24
Peak memory 201880 kb
Host smart-65c2ca72-0cb5-4b59-9df9-b9dd2bf20c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907840445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.907840445
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3616496777
Short name T630
Test name
Test status
Simulation time 169009956598 ps
CPU time 92.76 seconds
Started Jun 24 05:57:56 PM PDT 24
Finished Jun 24 05:59:30 PM PDT 24
Peak memory 202204 kb
Host smart-88814edf-8780-4e3a-99a0-16a3a24bc305
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616496777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3616496777
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.780510582
Short name T608
Test name
Test status
Simulation time 335264319509 ps
CPU time 766.8 seconds
Started Jun 24 05:57:56 PM PDT 24
Finished Jun 24 06:10:44 PM PDT 24
Peak memory 202164 kb
Host smart-6ea74f93-00dc-40a0-9cd3-d26d7f122f7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=780510582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.780510582
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2379361644
Short name T30
Test name
Test status
Simulation time 321038304950 ps
CPU time 770.91 seconds
Started Jun 24 05:57:56 PM PDT 24
Finished Jun 24 06:10:48 PM PDT 24
Peak memory 202176 kb
Host smart-1c6253c2-9dad-43ab-bf9f-254dd2676302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379361644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2379361644
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3149912263
Short name T361
Test name
Test status
Simulation time 161323491345 ps
CPU time 67.76 seconds
Started Jun 24 05:57:56 PM PDT 24
Finished Jun 24 05:59:05 PM PDT 24
Peak memory 202244 kb
Host smart-004ab066-4e42-47a9-9742-a1316525e28c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149912263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3149912263
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2725757237
Short name T325
Test name
Test status
Simulation time 557498416816 ps
CPU time 593.35 seconds
Started Jun 24 05:57:57 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 202196 kb
Host smart-78ca957a-503d-4284-b83a-ed18a3f694c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725757237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2725757237
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3874116326
Short name T367
Test name
Test status
Simulation time 599266200726 ps
CPU time 721.48 seconds
Started Jun 24 05:57:56 PM PDT 24
Finished Jun 24 06:09:58 PM PDT 24
Peak memory 202236 kb
Host smart-c147640c-ca9a-47ca-be24-a1024a8cbaa2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874116326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3874116326
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3515987416
Short name T417
Test name
Test status
Simulation time 115973650309 ps
CPU time 624.19 seconds
Started Jun 24 05:58:05 PM PDT 24
Finished Jun 24 06:08:29 PM PDT 24
Peak memory 202596 kb
Host smart-03d9951e-56ea-4e92-b41f-105ec04e4422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515987416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3515987416
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2865309045
Short name T95
Test name
Test status
Simulation time 42616585606 ps
CPU time 7.41 seconds
Started Jun 24 05:58:04 PM PDT 24
Finished Jun 24 05:58:12 PM PDT 24
Peak memory 202044 kb
Host smart-79e82376-a65c-489e-90b9-e5ade3f4268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865309045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2865309045
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2757967309
Short name T88
Test name
Test status
Simulation time 3301512766 ps
CPU time 8.54 seconds
Started Jun 24 05:58:04 PM PDT 24
Finished Jun 24 05:58:13 PM PDT 24
Peak memory 202020 kb
Host smart-953e87dc-286c-4fe7-9e34-c4c55f9423c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757967309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2757967309
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.877730867
Short name T521
Test name
Test status
Simulation time 5594853414 ps
CPU time 3.3 seconds
Started Jun 24 05:57:56 PM PDT 24
Finished Jun 24 05:58:00 PM PDT 24
Peak memory 201956 kb
Host smart-a67ce06e-d571-4b0c-bf21-5cd0aefef11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877730867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.877730867
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.23345791
Short name T530
Test name
Test status
Simulation time 241298875997 ps
CPU time 467.56 seconds
Started Jun 24 05:58:05 PM PDT 24
Finished Jun 24 06:05:53 PM PDT 24
Peak memory 202696 kb
Host smart-60c6fb12-17ca-4ab7-a73e-66e520d24490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23345791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.23345791
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.860855940
Short name T96
Test name
Test status
Simulation time 67776103807 ps
CPU time 33.4 seconds
Started Jun 24 05:58:04 PM PDT 24
Finished Jun 24 05:58:37 PM PDT 24
Peak memory 210504 kb
Host smart-c3bca013-ac39-432d-a140-b18c77e6b964
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860855940 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.860855940
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1583411676
Short name T563
Test name
Test status
Simulation time 460879974 ps
CPU time 1.19 seconds
Started Jun 24 05:58:17 PM PDT 24
Finished Jun 24 05:58:19 PM PDT 24
Peak memory 201900 kb
Host smart-5c8922fc-6ccd-419c-bd8c-9e0bfb6a1c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583411676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1583411676
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2818127879
Short name T721
Test name
Test status
Simulation time 183633481389 ps
CPU time 38.88 seconds
Started Jun 24 05:58:04 PM PDT 24
Finished Jun 24 05:58:43 PM PDT 24
Peak memory 202248 kb
Host smart-a20e7baa-8d8e-4f08-913f-e36e960e5f1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818127879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2818127879
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.4225024067
Short name T97
Test name
Test status
Simulation time 323414879853 ps
CPU time 760.91 seconds
Started Jun 24 05:58:13 PM PDT 24
Finished Jun 24 06:10:55 PM PDT 24
Peak memory 202276 kb
Host smart-ce99b1f5-b3d8-4d5b-91a6-7c3662b0219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225024067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4225024067
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2055908044
Short name T262
Test name
Test status
Simulation time 164894943598 ps
CPU time 339.67 seconds
Started Jun 24 05:58:03 PM PDT 24
Finished Jun 24 06:03:43 PM PDT 24
Peak memory 202284 kb
Host smart-4dd56bcb-63eb-4a1b-8e83-c55cac7744ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055908044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2055908044
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2227677248
Short name T711
Test name
Test status
Simulation time 326843480312 ps
CPU time 742.16 seconds
Started Jun 24 05:58:05 PM PDT 24
Finished Jun 24 06:10:28 PM PDT 24
Peak memory 202428 kb
Host smart-5609b79b-7481-4e66-a8f3-5f348c8d5b71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227677248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2227677248
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1336595232
Short name T609
Test name
Test status
Simulation time 333834755479 ps
CPU time 386.98 seconds
Started Jun 24 05:58:02 PM PDT 24
Finished Jun 24 06:04:29 PM PDT 24
Peak memory 202204 kb
Host smart-6b3a3585-f8d4-4cb7-a27f-24ae40239605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336595232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1336595232
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1474486838
Short name T528
Test name
Test status
Simulation time 323727921023 ps
CPU time 53.5 seconds
Started Jun 24 05:58:05 PM PDT 24
Finished Jun 24 05:58:59 PM PDT 24
Peak memory 202112 kb
Host smart-db897c78-0b2d-4e72-a9ea-5a19f1f4fc0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474486838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1474486838
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.187594245
Short name T181
Test name
Test status
Simulation time 355389135937 ps
CPU time 210.32 seconds
Started Jun 24 05:58:02 PM PDT 24
Finished Jun 24 06:01:33 PM PDT 24
Peak memory 202264 kb
Host smart-5067a615-60e6-4f37-8112-072f5f2fa8ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187594245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.187594245
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2673368195
Short name T704
Test name
Test status
Simulation time 206040789713 ps
CPU time 133.24 seconds
Started Jun 24 05:58:04 PM PDT 24
Finished Jun 24 06:00:18 PM PDT 24
Peak memory 202200 kb
Host smart-a6b883b5-007c-4114-ad16-3fc1112b5a3e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673368195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2673368195
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.297312623
Short name T685
Test name
Test status
Simulation time 62181301088 ps
CPU time 222.11 seconds
Started Jun 24 05:58:14 PM PDT 24
Finished Jun 24 06:01:57 PM PDT 24
Peak memory 202572 kb
Host smart-291939ce-01eb-4800-aede-85271abdc687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297312623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.297312623
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3669481042
Short name T575
Test name
Test status
Simulation time 24619862112 ps
CPU time 60.53 seconds
Started Jun 24 05:58:17 PM PDT 24
Finished Jun 24 05:59:18 PM PDT 24
Peak memory 202048 kb
Host smart-88072241-8a92-4271-b75f-cd5fd607e216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669481042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3669481042
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1228949565
Short name T388
Test name
Test status
Simulation time 5356913569 ps
CPU time 12.83 seconds
Started Jun 24 05:58:14 PM PDT 24
Finished Jun 24 05:58:27 PM PDT 24
Peak memory 202020 kb
Host smart-eaa3cdb7-38d6-4ac5-a6f3-56f7b6aa8e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228949565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1228949565
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3609634898
Short name T795
Test name
Test status
Simulation time 5766655907 ps
CPU time 3.97 seconds
Started Jun 24 05:58:05 PM PDT 24
Finished Jun 24 05:58:10 PM PDT 24
Peak memory 202008 kb
Host smart-5e8a63ec-af76-4138-8add-6e8c9774343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609634898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3609634898
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3976966554
Short name T332
Test name
Test status
Simulation time 260602354468 ps
CPU time 562.11 seconds
Started Jun 24 05:58:17 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 202508 kb
Host smart-57bc8242-e826-452d-951c-d74e4e5dcd93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976966554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3976966554
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3682942632
Short name T709
Test name
Test status
Simulation time 231556842333 ps
CPU time 172.33 seconds
Started Jun 24 05:58:17 PM PDT 24
Finished Jun 24 06:01:10 PM PDT 24
Peak memory 218240 kb
Host smart-fa197389-8a77-4bb9-959d-ffe0e409d0c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682942632 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3682942632
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2908951395
Short name T472
Test name
Test status
Simulation time 323387236 ps
CPU time 1.32 seconds
Started Jun 24 05:58:21 PM PDT 24
Finished Jun 24 05:58:23 PM PDT 24
Peak memory 201924 kb
Host smart-ea6f7efc-fdd0-4433-8198-c7a6a58a5f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908951395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2908951395
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1563237691
Short name T169
Test name
Test status
Simulation time 554070344586 ps
CPU time 106.86 seconds
Started Jun 24 05:58:24 PM PDT 24
Finished Jun 24 06:00:12 PM PDT 24
Peak memory 202204 kb
Host smart-a42c0ca0-7f26-433d-ae37-1c9d384aa968
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563237691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1563237691
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3580602299
Short name T743
Test name
Test status
Simulation time 172892563974 ps
CPU time 419.39 seconds
Started Jun 24 05:58:23 PM PDT 24
Finished Jun 24 06:05:23 PM PDT 24
Peak memory 202200 kb
Host smart-0a33d858-45ee-42e7-a7cf-cd540eb578d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580602299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3580602299
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1279395661
Short name T429
Test name
Test status
Simulation time 165203485362 ps
CPU time 101.03 seconds
Started Jun 24 05:58:15 PM PDT 24
Finished Jun 24 05:59:57 PM PDT 24
Peak memory 202264 kb
Host smart-7f7d6451-d0f3-4f6d-97ed-5582ba459bd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279395661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1279395661
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3460956374
Short name T199
Test name
Test status
Simulation time 327772627809 ps
CPU time 102.65 seconds
Started Jun 24 05:58:14 PM PDT 24
Finished Jun 24 05:59:57 PM PDT 24
Peak memory 202204 kb
Host smart-4fa4e4bc-74bb-4911-b71e-d8263d1224a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460956374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3460956374
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2098319668
Short name T705
Test name
Test status
Simulation time 331098931448 ps
CPU time 201.81 seconds
Started Jun 24 05:58:12 PM PDT 24
Finished Jun 24 06:01:35 PM PDT 24
Peak memory 202176 kb
Host smart-b3725fb3-ce87-439a-8463-2d8cd79c84da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098319668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2098319668
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1639848235
Short name T165
Test name
Test status
Simulation time 186715860421 ps
CPU time 86.29 seconds
Started Jun 24 05:58:13 PM PDT 24
Finished Jun 24 05:59:39 PM PDT 24
Peak memory 202272 kb
Host smart-cbf4bc89-1fc7-4e5f-b884-55c05ed31a24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639848235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1639848235
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.582098791
Short name T190
Test name
Test status
Simulation time 621420662025 ps
CPU time 566.43 seconds
Started Jun 24 05:58:13 PM PDT 24
Finished Jun 24 06:07:40 PM PDT 24
Peak memory 202204 kb
Host smart-83fb3180-b0f8-46cb-a67c-7b756a9d7e34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582098791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.582098791
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1845113025
Short name T756
Test name
Test status
Simulation time 90511389656 ps
CPU time 330.36 seconds
Started Jun 24 05:58:22 PM PDT 24
Finished Jun 24 06:03:53 PM PDT 24
Peak memory 202604 kb
Host smart-07ac61cf-ffba-40e2-8d7c-eb25c157e33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845113025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1845113025
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.402577765
Short name T172
Test name
Test status
Simulation time 28012646363 ps
CPU time 16.17 seconds
Started Jun 24 05:58:20 PM PDT 24
Finished Jun 24 05:58:37 PM PDT 24
Peak memory 202024 kb
Host smart-a5c3b439-e515-4b31-8bb0-1784f257f236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402577765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.402577765
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3136655737
Short name T522
Test name
Test status
Simulation time 2914119893 ps
CPU time 7.76 seconds
Started Jun 24 05:58:21 PM PDT 24
Finished Jun 24 05:58:29 PM PDT 24
Peak memory 202020 kb
Host smart-f975708f-a3c5-4a11-ab84-38c033d703a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136655737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3136655737
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.533713056
Short name T793
Test name
Test status
Simulation time 6049816324 ps
CPU time 4.11 seconds
Started Jun 24 05:58:14 PM PDT 24
Finished Jun 24 05:58:18 PM PDT 24
Peak memory 202012 kb
Host smart-9046d1c9-1fff-4a86-b270-230789998758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533713056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.533713056
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2042731436
Short name T177
Test name
Test status
Simulation time 244286196126 ps
CPU time 362.56 seconds
Started Jun 24 05:58:21 PM PDT 24
Finished Jun 24 06:04:24 PM PDT 24
Peak memory 210776 kb
Host smart-29eb09d4-f5bb-4f2c-82dc-ac823343cbe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042731436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2042731436
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1592619360
Short name T612
Test name
Test status
Simulation time 332514000754 ps
CPU time 531.95 seconds
Started Jun 24 05:58:20 PM PDT 24
Finished Jun 24 06:07:13 PM PDT 24
Peak memory 210912 kb
Host smart-ce024c00-eca0-4d9c-a426-0c7d3e12424b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592619360 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1592619360
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4149882329
Short name T375
Test name
Test status
Simulation time 350671304 ps
CPU time 0.73 seconds
Started Jun 24 05:58:34 PM PDT 24
Finished Jun 24 05:58:35 PM PDT 24
Peak memory 201900 kb
Host smart-2772edb6-7dea-4002-a640-3d52b853f6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149882329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4149882329
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3880132409
Short name T230
Test name
Test status
Simulation time 162785531543 ps
CPU time 251.85 seconds
Started Jun 24 05:58:33 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 202196 kb
Host smart-b72456cc-7158-422a-b91c-9c8ee20d3976
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880132409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3880132409
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.4173071575
Short name T585
Test name
Test status
Simulation time 330429419888 ps
CPU time 222.49 seconds
Started Jun 24 05:58:33 PM PDT 24
Finished Jun 24 06:02:16 PM PDT 24
Peak memory 202200 kb
Host smart-b42bce70-b8b6-44e8-af0b-29b6b0308474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173071575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4173071575
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2591069566
Short name T179
Test name
Test status
Simulation time 490594347220 ps
CPU time 565.91 seconds
Started Jun 24 05:58:21 PM PDT 24
Finished Jun 24 06:07:48 PM PDT 24
Peak memory 202208 kb
Host smart-9e2493ba-c2fb-4e59-b275-ef4d402456b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591069566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2591069566
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4036008736
Short name T589
Test name
Test status
Simulation time 167265375406 ps
CPU time 182.1 seconds
Started Jun 24 05:58:33 PM PDT 24
Finished Jun 24 06:01:36 PM PDT 24
Peak memory 202168 kb
Host smart-e2982f39-dbe3-4185-bbcb-94b7a5b6ac1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036008736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4036008736
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3570173000
Short name T307
Test name
Test status
Simulation time 165251205422 ps
CPU time 110.78 seconds
Started Jun 24 05:58:21 PM PDT 24
Finished Jun 24 06:00:13 PM PDT 24
Peak memory 202260 kb
Host smart-cc0fa416-e9df-45cb-b6c8-fcfa5d5c606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570173000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3570173000
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1524999842
Short name T586
Test name
Test status
Simulation time 327744629680 ps
CPU time 722.67 seconds
Started Jun 24 05:58:21 PM PDT 24
Finished Jun 24 06:10:24 PM PDT 24
Peak memory 202176 kb
Host smart-fe470367-af8d-44c2-b668-dd87a046f788
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524999842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1524999842
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.829723112
Short name T645
Test name
Test status
Simulation time 193443341691 ps
CPU time 229.54 seconds
Started Jun 24 05:58:31 PM PDT 24
Finished Jun 24 06:02:21 PM PDT 24
Peak memory 202152 kb
Host smart-ca29de97-3dd8-43b7-af57-842d318e68c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829723112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.829723112
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.370122331
Short name T628
Test name
Test status
Simulation time 116044578653 ps
CPU time 570.61 seconds
Started Jun 24 05:58:31 PM PDT 24
Finished Jun 24 06:08:02 PM PDT 24
Peak memory 202532 kb
Host smart-cb5c980f-b274-4997-beda-f5929f0defee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370122331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.370122331
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1423731544
Short name T707
Test name
Test status
Simulation time 43142063624 ps
CPU time 18.83 seconds
Started Jun 24 05:58:32 PM PDT 24
Finished Jun 24 05:58:51 PM PDT 24
Peak memory 202044 kb
Host smart-f9479498-924a-41ae-abd5-a60f15f89aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423731544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1423731544
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2293755636
Short name T554
Test name
Test status
Simulation time 3329774877 ps
CPU time 4.83 seconds
Started Jun 24 05:58:31 PM PDT 24
Finished Jun 24 05:58:36 PM PDT 24
Peak memory 201948 kb
Host smart-719e7273-01c8-4c40-9afd-b7ab8cbcd042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293755636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2293755636
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3961325068
Short name T595
Test name
Test status
Simulation time 6160139980 ps
CPU time 1.71 seconds
Started Jun 24 05:58:22 PM PDT 24
Finished Jun 24 05:58:24 PM PDT 24
Peak memory 202012 kb
Host smart-2b9765e8-672c-45f4-8185-16457105343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961325068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3961325068
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1691807343
Short name T607
Test name
Test status
Simulation time 253881283064 ps
CPU time 331.85 seconds
Started Jun 24 05:58:33 PM PDT 24
Finished Jun 24 06:04:06 PM PDT 24
Peak memory 212200 kb
Host smart-72f2900a-5145-4adc-ad77-d122fb927204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691807343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1691807343
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3419208200
Short name T40
Test name
Test status
Simulation time 28398309713 ps
CPU time 86.26 seconds
Started Jun 24 05:58:33 PM PDT 24
Finished Jun 24 05:59:59 PM PDT 24
Peak memory 210908 kb
Host smart-38aca2dc-168a-43f5-8b28-08c125679297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419208200 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3419208200
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.382813231
Short name T76
Test name
Test status
Simulation time 514446100 ps
CPU time 0.84 seconds
Started Jun 24 05:58:42 PM PDT 24
Finished Jun 24 05:58:43 PM PDT 24
Peak memory 201876 kb
Host smart-d3feba64-4bc0-45c5-9090-60e15c004a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382813231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.382813231
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3463701570
Short name T302
Test name
Test status
Simulation time 527156675099 ps
CPU time 367.06 seconds
Started Jun 24 05:58:40 PM PDT 24
Finished Jun 24 06:04:48 PM PDT 24
Peak memory 202276 kb
Host smart-763bd406-7b1d-4f2e-9502-a17e9573e097
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463701570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3463701570
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.372654003
Short name T206
Test name
Test status
Simulation time 341876772599 ps
CPU time 201.07 seconds
Started Jun 24 05:58:40 PM PDT 24
Finished Jun 24 06:02:02 PM PDT 24
Peak memory 202296 kb
Host smart-957d5283-d3b2-4064-9c38-b6f603b1c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372654003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.372654003
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.520250583
Short name T297
Test name
Test status
Simulation time 323115225142 ps
CPU time 787.23 seconds
Started Jun 24 05:58:39 PM PDT 24
Finished Jun 24 06:11:47 PM PDT 24
Peak memory 202132 kb
Host smart-9ba8f019-4f9e-4e74-a23d-a77ff299df84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520250583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.520250583
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4269339963
Short name T412
Test name
Test status
Simulation time 166612298059 ps
CPU time 396.33 seconds
Started Jun 24 05:58:40 PM PDT 24
Finished Jun 24 06:05:17 PM PDT 24
Peak memory 202172 kb
Host smart-c74ec482-99f4-4d5b-addc-5b3128277b6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269339963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.4269339963
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.4249475144
Short name T115
Test name
Test status
Simulation time 168237510464 ps
CPU time 95.11 seconds
Started Jun 24 05:58:40 PM PDT 24
Finished Jun 24 06:00:15 PM PDT 24
Peak memory 202272 kb
Host smart-dee88762-ccab-49ac-8b03-296d2b48ae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249475144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.4249475144
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3119709529
Short name T688
Test name
Test status
Simulation time 489202258099 ps
CPU time 1076.94 seconds
Started Jun 24 05:58:42 PM PDT 24
Finished Jun 24 06:16:40 PM PDT 24
Peak memory 202224 kb
Host smart-2d771d0b-65f4-4aa2-b674-38cf9e357137
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119709529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3119709529
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.939707323
Short name T213
Test name
Test status
Simulation time 507534960045 ps
CPU time 241.37 seconds
Started Jun 24 05:58:39 PM PDT 24
Finished Jun 24 06:02:40 PM PDT 24
Peak memory 202216 kb
Host smart-806e9795-279a-491d-87da-f54a84527c2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939707323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.939707323
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2912038177
Short name T745
Test name
Test status
Simulation time 394107210771 ps
CPU time 843.65 seconds
Started Jun 24 05:58:42 PM PDT 24
Finished Jun 24 06:12:46 PM PDT 24
Peak memory 202184 kb
Host smart-a4ff0734-47ca-4dcd-bcfd-b25dd204e4c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912038177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2912038177
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.430935000
Short name T618
Test name
Test status
Simulation time 105065137608 ps
CPU time 601.52 seconds
Started Jun 24 05:58:40 PM PDT 24
Finished Jun 24 06:08:42 PM PDT 24
Peak memory 202564 kb
Host smart-cfa43cb4-b846-4532-9b57-1eca3ee8d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430935000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.430935000
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3346115374
Short name T2
Test name
Test status
Simulation time 31571252023 ps
CPU time 15.41 seconds
Started Jun 24 05:58:40 PM PDT 24
Finished Jun 24 05:58:56 PM PDT 24
Peak memory 202020 kb
Host smart-1472cd59-97c2-4f45-a950-b9ae0c814073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346115374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3346115374
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.524461478
Short name T785
Test name
Test status
Simulation time 2979403585 ps
CPU time 4.13 seconds
Started Jun 24 05:58:38 PM PDT 24
Finished Jun 24 05:58:43 PM PDT 24
Peak memory 202000 kb
Host smart-ff23f417-6f84-4881-be1b-c205f4070c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524461478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.524461478
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.4217037958
Short name T453
Test name
Test status
Simulation time 5735982058 ps
CPU time 13.69 seconds
Started Jun 24 05:58:33 PM PDT 24
Finished Jun 24 05:58:47 PM PDT 24
Peak memory 202008 kb
Host smart-199c04fa-9843-4f74-9718-6641151ef4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217037958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.4217037958
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.365713470
Short name T91
Test name
Test status
Simulation time 91246933129 ps
CPU time 41.23 seconds
Started Jun 24 05:58:39 PM PDT 24
Finished Jun 24 05:59:20 PM PDT 24
Peak memory 210516 kb
Host smart-0d9283de-daf4-4d60-9958-64ac21681adc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365713470 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.365713470
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2828973192
Short name T470
Test name
Test status
Simulation time 358754010 ps
CPU time 1.2 seconds
Started Jun 24 05:58:51 PM PDT 24
Finished Jun 24 05:58:53 PM PDT 24
Peak memory 201904 kb
Host smart-c01aea65-633c-45cd-9325-03f4ab31215b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828973192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2828973192
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2076000498
Short name T633
Test name
Test status
Simulation time 333409314003 ps
CPU time 159.85 seconds
Started Jun 24 05:58:50 PM PDT 24
Finished Jun 24 06:01:31 PM PDT 24
Peak memory 202136 kb
Host smart-b8c04c3f-8067-4b17-9b39-027c43fb8a73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076000498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2076000498
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3757385128
Short name T235
Test name
Test status
Simulation time 337750803603 ps
CPU time 114.73 seconds
Started Jun 24 05:58:50 PM PDT 24
Finished Jun 24 06:00:45 PM PDT 24
Peak memory 202200 kb
Host smart-585a36a1-8591-4d89-b496-ba389a5238a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757385128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3757385128
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2812767838
Short name T180
Test name
Test status
Simulation time 325818324597 ps
CPU time 272.16 seconds
Started Jun 24 05:58:48 PM PDT 24
Finished Jun 24 06:03:21 PM PDT 24
Peak memory 202220 kb
Host smart-88d1c44d-3574-461e-a232-68ab8e4e1e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812767838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2812767838
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1394382558
Short name T602
Test name
Test status
Simulation time 164929454248 ps
CPU time 383.32 seconds
Started Jun 24 05:58:50 PM PDT 24
Finished Jun 24 06:05:14 PM PDT 24
Peak memory 202168 kb
Host smart-c04cb2e5-faf6-4b70-a330-ff91f3433c56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394382558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1394382558
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1418823235
Short name T664
Test name
Test status
Simulation time 483317780563 ps
CPU time 987.52 seconds
Started Jun 24 05:58:52 PM PDT 24
Finished Jun 24 06:15:20 PM PDT 24
Peak memory 202264 kb
Host smart-6b01a814-fd03-4964-bd52-a91ed2823ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418823235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1418823235
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3768884195
Short name T191
Test name
Test status
Simulation time 485507925941 ps
CPU time 270.07 seconds
Started Jun 24 05:58:51 PM PDT 24
Finished Jun 24 06:03:21 PM PDT 24
Peak memory 202176 kb
Host smart-674f446c-01b7-411f-93eb-47fb01e7e8af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768884195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3768884195
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3069872232
Short name T309
Test name
Test status
Simulation time 359160953702 ps
CPU time 891.2 seconds
Started Jun 24 05:58:53 PM PDT 24
Finished Jun 24 06:13:45 PM PDT 24
Peak memory 202180 kb
Host smart-9ea4cab7-d27b-4be2-9e17-38dfd2c16dcd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069872232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3069872232
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1360167181
Short name T454
Test name
Test status
Simulation time 409778190526 ps
CPU time 468.9 seconds
Started Jun 24 05:58:52 PM PDT 24
Finished Jun 24 06:06:41 PM PDT 24
Peak memory 202196 kb
Host smart-10d8eda5-266b-4e23-9c94-1047e05a4eb7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360167181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1360167181
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1819981418
Short name T462
Test name
Test status
Simulation time 121044266267 ps
CPU time 633.5 seconds
Started Jun 24 05:58:53 PM PDT 24
Finished Jun 24 06:09:27 PM PDT 24
Peak memory 202488 kb
Host smart-4bf285f1-5c4b-4fcf-800e-40a67d007578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819981418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1819981418
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.924466672
Short name T382
Test name
Test status
Simulation time 24245243276 ps
CPU time 27.68 seconds
Started Jun 24 05:58:52 PM PDT 24
Finished Jun 24 05:59:20 PM PDT 24
Peak memory 202040 kb
Host smart-379e51fc-b997-4eaa-b561-2310b33e0a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924466672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.924466672
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4266575270
Short name T353
Test name
Test status
Simulation time 2845662796 ps
CPU time 2.44 seconds
Started Jun 24 05:58:49 PM PDT 24
Finished Jun 24 05:58:52 PM PDT 24
Peak memory 202008 kb
Host smart-5535daba-46a1-4e2b-b039-8d246eea506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266575270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4266575270
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1676318481
Short name T480
Test name
Test status
Simulation time 5780261515 ps
CPU time 7.49 seconds
Started Jun 24 05:58:40 PM PDT 24
Finished Jun 24 05:58:48 PM PDT 24
Peak memory 202016 kb
Host smart-a30fb92e-c836-4cb2-a6e1-b18ab2d099ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676318481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1676318481
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1855958655
Short name T778
Test name
Test status
Simulation time 38067211889 ps
CPU time 88.88 seconds
Started Jun 24 05:58:51 PM PDT 24
Finished Jun 24 06:00:21 PM PDT 24
Peak memory 218932 kb
Host smart-7d8da0c8-3425-4180-a5b1-c903ccf86bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855958655 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1855958655
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2291471796
Short name T680
Test name
Test status
Simulation time 311716358 ps
CPU time 1.35 seconds
Started Jun 24 05:59:00 PM PDT 24
Finished Jun 24 05:59:02 PM PDT 24
Peak memory 201904 kb
Host smart-62d4bdee-c417-4502-a971-729939fa35af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291471796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2291471796
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.869844476
Short name T285
Test name
Test status
Simulation time 363912163532 ps
CPU time 410.67 seconds
Started Jun 24 05:59:00 PM PDT 24
Finished Jun 24 06:05:51 PM PDT 24
Peak memory 202268 kb
Host smart-d02003ec-de22-476c-9986-cb737c9f7256
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869844476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.869844476
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.729782842
Short name T289
Test name
Test status
Simulation time 199320686607 ps
CPU time 237.47 seconds
Started Jun 24 05:58:58 PM PDT 24
Finished Jun 24 06:02:56 PM PDT 24
Peak memory 202216 kb
Host smart-6ec066e7-0a16-4d6c-9a32-500a8898a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729782842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.729782842
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3413571350
Short name T531
Test name
Test status
Simulation time 483050816437 ps
CPU time 291.84 seconds
Started Jun 24 05:58:59 PM PDT 24
Finished Jun 24 06:03:52 PM PDT 24
Peak memory 202148 kb
Host smart-8f7eb814-ce7d-48fe-916a-fbe8bc6f0e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413571350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3413571350
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.588082645
Short name T750
Test name
Test status
Simulation time 323987438021 ps
CPU time 184.81 seconds
Started Jun 24 05:58:57 PM PDT 24
Finished Jun 24 06:02:03 PM PDT 24
Peak memory 202244 kb
Host smart-262def87-8591-4864-a0d9-7d0582371783
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=588082645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.588082645
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1269821305
Short name T455
Test name
Test status
Simulation time 323017777073 ps
CPU time 190.8 seconds
Started Jun 24 05:58:58 PM PDT 24
Finished Jun 24 06:02:09 PM PDT 24
Peak memory 202224 kb
Host smart-ae7766bd-d946-4b9f-8f93-c3e090ec0420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269821305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1269821305
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.392507930
Short name T768
Test name
Test status
Simulation time 490457749105 ps
CPU time 273.58 seconds
Started Jun 24 05:58:59 PM PDT 24
Finished Jun 24 06:03:33 PM PDT 24
Peak memory 202236 kb
Host smart-43d408c4-bb12-4bd9-950f-be6cc4c83092
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=392507930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.392507930
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.491149256
Short name T796
Test name
Test status
Simulation time 362645093534 ps
CPU time 784.18 seconds
Started Jun 24 05:58:57 PM PDT 24
Finished Jun 24 06:12:02 PM PDT 24
Peak memory 202216 kb
Host smart-1bb0bac4-e6f9-40cf-af0e-fbe67b4898e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491149256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.491149256
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.4208434521
Short name T669
Test name
Test status
Simulation time 206594502676 ps
CPU time 121.26 seconds
Started Jun 24 05:58:58 PM PDT 24
Finished Jun 24 06:01:00 PM PDT 24
Peak memory 202204 kb
Host smart-e0a6b797-5eba-4391-a1ed-15ee5bc204b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208434521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.4208434521
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2993159740
Short name T372
Test name
Test status
Simulation time 92556592401 ps
CPU time 466.77 seconds
Started Jun 24 05:58:57 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 202508 kb
Host smart-284e4fb2-89df-4c76-b2b9-5e44e50f7634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993159740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2993159740
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3194225238
Short name T580
Test name
Test status
Simulation time 39608567125 ps
CPU time 17.77 seconds
Started Jun 24 05:58:58 PM PDT 24
Finished Jun 24 05:59:16 PM PDT 24
Peak memory 202048 kb
Host smart-ce3f2796-84b1-4bb2-8ecd-a25bd3a329a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194225238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3194225238
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3653488706
Short name T605
Test name
Test status
Simulation time 2641862533 ps
CPU time 4.03 seconds
Started Jun 24 05:58:59 PM PDT 24
Finished Jun 24 05:59:04 PM PDT 24
Peak memory 202020 kb
Host smart-cbd5ed8d-aaed-4eaa-9b2e-f0f5c4cbaf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653488706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3653488706
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2339270893
Short name T675
Test name
Test status
Simulation time 6011278075 ps
CPU time 7.75 seconds
Started Jun 24 05:58:50 PM PDT 24
Finished Jun 24 05:58:58 PM PDT 24
Peak memory 202012 kb
Host smart-8bdf2c5d-2bc6-40e1-8909-10a9e16b03f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339270893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2339270893
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.155467503
Short name T634
Test name
Test status
Simulation time 175276163183 ps
CPU time 179.95 seconds
Started Jun 24 05:59:00 PM PDT 24
Finished Jun 24 06:02:00 PM PDT 24
Peak memory 202280 kb
Host smart-8215a967-3f80-46d6-8248-6648e3658bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155467503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
155467503
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4118971554
Short name T760
Test name
Test status
Simulation time 66909407764 ps
CPU time 41.62 seconds
Started Jun 24 05:58:59 PM PDT 24
Finished Jun 24 05:59:41 PM PDT 24
Peak memory 210596 kb
Host smart-f508cc32-3d91-45ae-89b9-9b93c1370af0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118971554 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.4118971554
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2179795420
Short name T428
Test name
Test status
Simulation time 450967201 ps
CPU time 0.87 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 05:55:23 PM PDT 24
Peak memory 201896 kb
Host smart-97401a14-0e34-4db6-94b4-5cdbc56e9401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179795420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2179795420
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1886459902
Short name T63
Test name
Test status
Simulation time 507487960762 ps
CPU time 1063.11 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 06:13:06 PM PDT 24
Peak memory 202204 kb
Host smart-c8d9a611-92e0-43c1-9727-cab1a386bd5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886459902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1886459902
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.819732951
Short name T643
Test name
Test status
Simulation time 171584623220 ps
CPU time 230.52 seconds
Started Jun 24 05:55:18 PM PDT 24
Finished Jun 24 05:59:10 PM PDT 24
Peak memory 202204 kb
Host smart-5dc258f1-3e9d-49a0-9c04-6a761c1c3419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819732951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.819732951
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2156358189
Short name T579
Test name
Test status
Simulation time 160818742053 ps
CPU time 96.32 seconds
Started Jun 24 05:55:18 PM PDT 24
Finished Jun 24 05:56:55 PM PDT 24
Peak memory 202268 kb
Host smart-7db2126d-23ab-4dbd-9ca5-57f91e59223d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156358189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2156358189
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.983445152
Short name T502
Test name
Test status
Simulation time 165759194310 ps
CPU time 373.54 seconds
Started Jun 24 05:55:20 PM PDT 24
Finished Jun 24 06:01:34 PM PDT 24
Peak memory 202180 kb
Host smart-ac59d69a-a317-4cd8-88ec-addf313cde34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=983445152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.983445152
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1355542568
Short name T225
Test name
Test status
Simulation time 337307433325 ps
CPU time 767.45 seconds
Started Jun 24 05:55:13 PM PDT 24
Finished Jun 24 06:08:03 PM PDT 24
Peak memory 202272 kb
Host smart-1f7f32e3-efd4-4cf5-8d9f-c0cf33535ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355542568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1355542568
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.792549383
Short name T403
Test name
Test status
Simulation time 488310342577 ps
CPU time 1055.39 seconds
Started Jun 24 05:55:11 PM PDT 24
Finished Jun 24 06:12:49 PM PDT 24
Peak memory 202148 kb
Host smart-cf9641b2-021d-4225-b294-17bcf5bc4692
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=792549383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.792549383
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.589950944
Short name T253
Test name
Test status
Simulation time 352161541136 ps
CPU time 208.65 seconds
Started Jun 24 05:55:22 PM PDT 24
Finished Jun 24 05:58:53 PM PDT 24
Peak memory 202156 kb
Host smart-e2cf29ff-d88c-44ce-80c6-998a79c692a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589950944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.589950944
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4240557321
Short name T593
Test name
Test status
Simulation time 582635144460 ps
CPU time 241.31 seconds
Started Jun 24 05:55:20 PM PDT 24
Finished Jun 24 05:59:22 PM PDT 24
Peak memory 202196 kb
Host smart-1abfde59-bd95-440d-9cea-b9205de2341d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240557321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4240557321
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2787205921
Short name T509
Test name
Test status
Simulation time 33784608728 ps
CPU time 78.93 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 05:56:42 PM PDT 24
Peak memory 202004 kb
Host smart-1a429b1c-0049-4703-86e9-b91ffe6f0d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787205921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2787205921
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1937123107
Short name T357
Test name
Test status
Simulation time 4904825121 ps
CPU time 6.94 seconds
Started Jun 24 05:55:20 PM PDT 24
Finished Jun 24 05:55:28 PM PDT 24
Peak memory 202020 kb
Host smart-78da8c38-c7b3-4518-a97c-11a49f00a8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937123107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1937123107
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1930899477
Short name T730
Test name
Test status
Simulation time 5704044856 ps
CPU time 12.79 seconds
Started Jun 24 05:55:19 PM PDT 24
Finished Jun 24 05:55:33 PM PDT 24
Peak memory 202008 kb
Host smart-40538b8e-39c4-4bf3-a33e-1a574f9a7778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930899477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1930899477
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1324188052
Short name T513
Test name
Test status
Simulation time 281930441 ps
CPU time 1.31 seconds
Started Jun 24 05:59:10 PM PDT 24
Finished Jun 24 05:59:11 PM PDT 24
Peak memory 201900 kb
Host smart-02312e05-b35b-4f02-a584-d9965b40d779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324188052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1324188052
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.755489397
Short name T323
Test name
Test status
Simulation time 161832032154 ps
CPU time 80.06 seconds
Started Jun 24 05:59:08 PM PDT 24
Finished Jun 24 06:00:28 PM PDT 24
Peak memory 202208 kb
Host smart-15fda30e-910d-43dc-81c3-4e49362c0dec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755489397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.755489397
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3108777931
Short name T625
Test name
Test status
Simulation time 500583101221 ps
CPU time 1035.69 seconds
Started Jun 24 05:59:08 PM PDT 24
Finished Jun 24 06:16:24 PM PDT 24
Peak memory 202196 kb
Host smart-98ff87ed-ed82-4684-849a-cbddcee06f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108777931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3108777931
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3172568627
Short name T482
Test name
Test status
Simulation time 494275245921 ps
CPU time 1164.09 seconds
Started Jun 24 05:59:08 PM PDT 24
Finished Jun 24 06:18:32 PM PDT 24
Peak memory 202188 kb
Host smart-5458b40b-ce75-47f2-ba9c-50ba7d35a5a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172568627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3172568627
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2745757276
Short name T167
Test name
Test status
Simulation time 337739756057 ps
CPU time 74.18 seconds
Started Jun 24 05:59:09 PM PDT 24
Finished Jun 24 06:00:24 PM PDT 24
Peak memory 202208 kb
Host smart-2fb7c106-0f44-4b60-9a3b-f038662bca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745757276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2745757276
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3364815893
Short name T603
Test name
Test status
Simulation time 509608838085 ps
CPU time 1209.27 seconds
Started Jun 24 05:59:09 PM PDT 24
Finished Jun 24 06:19:19 PM PDT 24
Peak memory 202256 kb
Host smart-36ea173c-e8ab-4017-8de3-3c21d04ddb45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364815893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3364815893
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3587264301
Short name T671
Test name
Test status
Simulation time 539449021300 ps
CPU time 212.61 seconds
Started Jun 24 05:59:07 PM PDT 24
Finished Jun 24 06:02:40 PM PDT 24
Peak memory 202284 kb
Host smart-a78ef337-d2c6-46ad-964c-6c473a1bb51a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587264301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3587264301
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3627247453
Short name T433
Test name
Test status
Simulation time 197425109620 ps
CPU time 429.95 seconds
Started Jun 24 05:59:09 PM PDT 24
Finished Jun 24 06:06:20 PM PDT 24
Peak memory 202180 kb
Host smart-fa261077-35a1-4ad1-84ae-1595af329ab8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627247453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3627247453
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2230205915
Short name T690
Test name
Test status
Simulation time 124558337589 ps
CPU time 447.78 seconds
Started Jun 24 05:59:09 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 202572 kb
Host smart-76319d54-6b4e-4e30-8189-3be8cfd4cbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230205915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2230205915
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1898646382
Short name T781
Test name
Test status
Simulation time 42435498051 ps
CPU time 92.56 seconds
Started Jun 24 05:59:07 PM PDT 24
Finished Jun 24 06:00:40 PM PDT 24
Peak memory 202020 kb
Host smart-bb377a20-a69b-4c13-86b7-1f7be0194102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898646382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1898646382
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.753860032
Short name T698
Test name
Test status
Simulation time 3099389303 ps
CPU time 7.46 seconds
Started Jun 24 05:59:10 PM PDT 24
Finished Jun 24 05:59:18 PM PDT 24
Peak memory 202008 kb
Host smart-3c0ec6f6-7505-47dc-bb06-6374b52e0b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753860032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.753860032
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2558724914
Short name T516
Test name
Test status
Simulation time 5740656219 ps
CPU time 3.55 seconds
Started Jun 24 05:58:59 PM PDT 24
Finished Jun 24 05:59:03 PM PDT 24
Peak memory 202012 kb
Host smart-b517f4b0-c434-472f-8a9b-6c3b02aa7f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558724914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2558724914
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1942217297
Short name T759
Test name
Test status
Simulation time 352684353564 ps
CPU time 1171.21 seconds
Started Jun 24 05:59:07 PM PDT 24
Finished Jun 24 06:18:38 PM PDT 24
Peak memory 210704 kb
Host smart-64eb8b1a-b37e-4e23-9dc6-6e97c604c117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942217297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1942217297
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2034506160
Short name T392
Test name
Test status
Simulation time 363813990 ps
CPU time 1.47 seconds
Started Jun 24 05:59:25 PM PDT 24
Finished Jun 24 05:59:27 PM PDT 24
Peak memory 201916 kb
Host smart-2307bcdd-8377-4fc0-9df9-ec18e0cd1e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034506160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2034506160
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1039714366
Short name T264
Test name
Test status
Simulation time 167485166774 ps
CPU time 367.23 seconds
Started Jun 24 05:59:14 PM PDT 24
Finished Jun 24 06:05:21 PM PDT 24
Peak memory 202276 kb
Host smart-84fcb085-0faf-452f-9436-dc5fdafe0aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039714366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1039714366
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2646916558
Short name T383
Test name
Test status
Simulation time 163869787135 ps
CPU time 179.94 seconds
Started Jun 24 05:59:15 PM PDT 24
Finished Jun 24 06:02:15 PM PDT 24
Peak memory 202204 kb
Host smart-a4f0e7b1-18e9-4234-b12f-1be3d354dc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646916558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2646916558
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1836047357
Short name T681
Test name
Test status
Simulation time 325335868397 ps
CPU time 727.32 seconds
Started Jun 24 05:59:17 PM PDT 24
Finished Jun 24 06:11:25 PM PDT 24
Peak memory 202252 kb
Host smart-b9e9beab-24d5-4af2-a27f-82329504b78d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836047357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1836047357
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2624993011
Short name T442
Test name
Test status
Simulation time 495603244612 ps
CPU time 304 seconds
Started Jun 24 05:59:08 PM PDT 24
Finished Jun 24 06:04:12 PM PDT 24
Peak memory 202160 kb
Host smart-c0e3a84e-fbc9-4b94-90ef-1896d8f9300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624993011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2624993011
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2039496041
Short name T597
Test name
Test status
Simulation time 488335234111 ps
CPU time 389.98 seconds
Started Jun 24 05:59:15 PM PDT 24
Finished Jun 24 06:05:45 PM PDT 24
Peak memory 202236 kb
Host smart-b8f136fb-b987-40a4-a08d-8e557235cb1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039496041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2039496041
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3324638797
Short name T252
Test name
Test status
Simulation time 277430465417 ps
CPU time 85.6 seconds
Started Jun 24 05:59:16 PM PDT 24
Finished Jun 24 06:00:42 PM PDT 24
Peak memory 202144 kb
Host smart-469e0f2f-b94f-489d-ba4c-9749839b9b8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324638797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3324638797
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2091533484
Short name T344
Test name
Test status
Simulation time 205432367237 ps
CPU time 139.63 seconds
Started Jun 24 05:59:18 PM PDT 24
Finished Jun 24 06:01:38 PM PDT 24
Peak memory 202188 kb
Host smart-99279a1d-66f5-47ad-8c1a-8b9355fef1a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091533484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2091533484
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2607875933
Short name T221
Test name
Test status
Simulation time 75673097226 ps
CPU time 236.92 seconds
Started Jun 24 05:59:13 PM PDT 24
Finished Jun 24 06:03:10 PM PDT 24
Peak memory 202572 kb
Host smart-093b6aef-055a-45ea-a906-0538dc5abc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607875933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2607875933
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2536935820
Short name T719
Test name
Test status
Simulation time 32782135926 ps
CPU time 35.58 seconds
Started Jun 24 05:59:15 PM PDT 24
Finished Jun 24 05:59:51 PM PDT 24
Peak memory 202084 kb
Host smart-82908ff3-6d87-4dce-8d39-7467b64b28ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536935820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2536935820
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2873902882
Short name T617
Test name
Test status
Simulation time 3662123123 ps
CPU time 10.64 seconds
Started Jun 24 05:59:16 PM PDT 24
Finished Jun 24 05:59:27 PM PDT 24
Peak memory 202008 kb
Host smart-75dbb51a-834e-4504-b656-cb0bb192e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873902882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2873902882
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3926774175
Short name T456
Test name
Test status
Simulation time 5828107391 ps
CPU time 13.51 seconds
Started Jun 24 05:59:07 PM PDT 24
Finished Jun 24 05:59:21 PM PDT 24
Peak memory 202016 kb
Host smart-22538c7f-d3b9-459b-b94b-b4bf0afcbbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926774175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3926774175
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2890566824
Short name T687
Test name
Test status
Simulation time 345162764269 ps
CPU time 227.64 seconds
Started Jun 24 05:59:14 PM PDT 24
Finished Jun 24 06:03:02 PM PDT 24
Peak memory 202192 kb
Host smart-480f51cd-5d70-49d0-8324-e02bdc682b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890566824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2890566824
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.277012995
Short name T19
Test name
Test status
Simulation time 84592583453 ps
CPU time 172.05 seconds
Started Jun 24 05:59:15 PM PDT 24
Finished Jun 24 06:02:08 PM PDT 24
Peak memory 210508 kb
Host smart-5c6822a8-80b3-46b0-905f-2be6d56de990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277012995 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.277012995
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2438366492
Short name T556
Test name
Test status
Simulation time 314113009 ps
CPU time 0.91 seconds
Started Jun 24 05:59:39 PM PDT 24
Finished Jun 24 05:59:41 PM PDT 24
Peak memory 201916 kb
Host smart-890b5c83-4588-485b-8549-71f93d4e0add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438366492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2438366492
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2822458192
Short name T501
Test name
Test status
Simulation time 166732990815 ps
CPU time 363.15 seconds
Started Jun 24 05:59:26 PM PDT 24
Finished Jun 24 06:05:30 PM PDT 24
Peak memory 202292 kb
Host smart-f3e17802-dba0-435a-a71f-45e3c5bd707d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822458192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2822458192
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1435740598
Short name T773
Test name
Test status
Simulation time 167252128999 ps
CPU time 103.95 seconds
Started Jun 24 05:59:25 PM PDT 24
Finished Jun 24 06:01:10 PM PDT 24
Peak memory 202104 kb
Host smart-f20853ba-70f6-4755-96db-3a40dfbc79fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435740598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1435740598
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3049928725
Short name T459
Test name
Test status
Simulation time 329277872986 ps
CPU time 379.53 seconds
Started Jun 24 05:59:26 PM PDT 24
Finished Jun 24 06:05:46 PM PDT 24
Peak memory 202200 kb
Host smart-2b6bfa04-f303-43bd-9d0b-6d5bbf8b4af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049928725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3049928725
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.517503476
Short name T594
Test name
Test status
Simulation time 477127855447 ps
CPU time 199.23 seconds
Started Jun 24 05:59:24 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 202176 kb
Host smart-8fb894d6-48fe-4202-bdf4-19aee3c7dadc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=517503476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.517503476
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2130675163
Short name T29
Test name
Test status
Simulation time 184685443355 ps
CPU time 25.06 seconds
Started Jun 24 05:59:25 PM PDT 24
Finished Jun 24 05:59:51 PM PDT 24
Peak memory 202240 kb
Host smart-9b297217-722a-4893-aa7e-e92693c2df6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130675163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2130675163
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2493055008
Short name T495
Test name
Test status
Simulation time 195750282892 ps
CPU time 463.17 seconds
Started Jun 24 05:59:26 PM PDT 24
Finished Jun 24 06:07:10 PM PDT 24
Peak memory 202424 kb
Host smart-3da9a414-835b-4d3d-a117-990873ed891b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493055008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2493055008
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.795550448
Short name T379
Test name
Test status
Simulation time 77829222904 ps
CPU time 317.11 seconds
Started Jun 24 05:59:35 PM PDT 24
Finished Jun 24 06:04:53 PM PDT 24
Peak memory 202592 kb
Host smart-41d2ae12-f5f0-4c67-9da9-928c7494988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795550448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.795550448
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.4058006533
Short name T523
Test name
Test status
Simulation time 34226375842 ps
CPU time 19.5 seconds
Started Jun 24 05:59:26 PM PDT 24
Finished Jun 24 05:59:46 PM PDT 24
Peak memory 202040 kb
Host smart-9604fd99-11a9-4b4b-9e99-d3a51fa2f425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058006533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.4058006533
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1387018995
Short name T401
Test name
Test status
Simulation time 4454042870 ps
CPU time 10.72 seconds
Started Jun 24 05:59:26 PM PDT 24
Finished Jun 24 05:59:37 PM PDT 24
Peak memory 202000 kb
Host smart-4de7a5e3-8e32-4064-9180-f68002815cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387018995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1387018995
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2102817959
Short name T381
Test name
Test status
Simulation time 5825005618 ps
CPU time 7.58 seconds
Started Jun 24 05:59:26 PM PDT 24
Finished Jun 24 05:59:34 PM PDT 24
Peak memory 201988 kb
Host smart-d93a464a-627c-49cb-9d18-5ff549f5f3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102817959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2102817959
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.4156670264
Short name T632
Test name
Test status
Simulation time 549604124671 ps
CPU time 134.22 seconds
Started Jun 24 05:59:33 PM PDT 24
Finished Jun 24 06:01:48 PM PDT 24
Peak memory 202264 kb
Host smart-c5916277-7a5b-4843-ab2d-22f2f13098e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156670264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.4156670264
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1372166841
Short name T51
Test name
Test status
Simulation time 105485150597 ps
CPU time 152.21 seconds
Started Jun 24 05:59:32 PM PDT 24
Finished Jun 24 06:02:05 PM PDT 24
Peak memory 210888 kb
Host smart-9242f199-1bf2-4ed5-b9f1-206097302d71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372166841 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1372166841
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2287849446
Short name T350
Test name
Test status
Simulation time 486159466 ps
CPU time 1.25 seconds
Started Jun 24 05:59:34 PM PDT 24
Finished Jun 24 05:59:36 PM PDT 24
Peak memory 201892 kb
Host smart-6bc2a4f8-256c-46d3-83a1-41feab97dfd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287849446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2287849446
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1044108229
Short name T276
Test name
Test status
Simulation time 364786132874 ps
CPU time 460.33 seconds
Started Jun 24 05:59:33 PM PDT 24
Finished Jun 24 06:07:14 PM PDT 24
Peak memory 202204 kb
Host smart-f7464975-7344-42e1-887b-c026b3965d7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044108229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1044108229
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.453994963
Short name T291
Test name
Test status
Simulation time 373172516482 ps
CPU time 405.18 seconds
Started Jun 24 05:59:38 PM PDT 24
Finished Jun 24 06:06:24 PM PDT 24
Peak memory 202392 kb
Host smart-faa9ad13-e8b4-46e2-8f79-b9f1d1726489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453994963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.453994963
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.264129526
Short name T315
Test name
Test status
Simulation time 322222561124 ps
CPU time 228.79 seconds
Started Jun 24 05:59:35 PM PDT 24
Finished Jun 24 06:03:25 PM PDT 24
Peak memory 202284 kb
Host smart-4d69c1dc-b0cf-4bbf-bc32-81303692fe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264129526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.264129526
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.467323972
Short name T716
Test name
Test status
Simulation time 319801704688 ps
CPU time 361.61 seconds
Started Jun 24 05:59:35 PM PDT 24
Finished Jun 24 06:05:37 PM PDT 24
Peak memory 202188 kb
Host smart-ae29915b-799f-4402-aa26-8e50f5cf4a97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=467323972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.467323972
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.4246421058
Short name T670
Test name
Test status
Simulation time 325291171821 ps
CPU time 139.42 seconds
Started Jun 24 05:59:34 PM PDT 24
Finished Jun 24 06:01:54 PM PDT 24
Peak memory 202240 kb
Host smart-07f88ea8-f070-4eb3-b646-cfa18aa6a49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246421058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4246421058
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2697276791
Short name T427
Test name
Test status
Simulation time 490336623981 ps
CPU time 1060.2 seconds
Started Jun 24 05:59:34 PM PDT 24
Finished Jun 24 06:17:16 PM PDT 24
Peak memory 202188 kb
Host smart-975f781f-5de6-4d64-89b9-d0c2e1780092
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697276791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2697276791
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2812129615
Short name T629
Test name
Test status
Simulation time 189334901599 ps
CPU time 399.12 seconds
Started Jun 24 05:59:34 PM PDT 24
Finished Jun 24 06:06:14 PM PDT 24
Peak memory 202196 kb
Host smart-6b107416-bc1b-473e-b21e-bb7386e69ab1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812129615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2812129615
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.910361066
Short name T28
Test name
Test status
Simulation time 612079099591 ps
CPU time 1031.54 seconds
Started Jun 24 05:59:38 PM PDT 24
Finished Jun 24 06:16:50 PM PDT 24
Peak memory 202372 kb
Host smart-57e107f2-b609-4ebb-9a0b-bcde0a0c2a5a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910361066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.910361066
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1776046881
Short name T468
Test name
Test status
Simulation time 105967335703 ps
CPU time 296.88 seconds
Started Jun 24 05:59:37 PM PDT 24
Finished Jun 24 06:04:34 PM PDT 24
Peak memory 202752 kb
Host smart-ad69e994-62a9-403c-9aac-bfe1fd89d580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776046881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1776046881
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.720338837
Short name T508
Test name
Test status
Simulation time 23428294288 ps
CPU time 48.36 seconds
Started Jun 24 05:59:34 PM PDT 24
Finished Jun 24 06:00:24 PM PDT 24
Peak memory 202000 kb
Host smart-6fd824e4-fc14-417e-af9d-d7128b8e3d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720338837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.720338837
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3088719160
Short name T349
Test name
Test status
Simulation time 3814686516 ps
CPU time 9.57 seconds
Started Jun 24 05:59:33 PM PDT 24
Finished Jun 24 05:59:43 PM PDT 24
Peak memory 201928 kb
Host smart-de6dbf56-eb3b-4d74-977c-e77d7a10bb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088719160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3088719160
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3208008152
Short name T410
Test name
Test status
Simulation time 5520767472 ps
CPU time 6.55 seconds
Started Jun 24 05:59:34 PM PDT 24
Finished Jun 24 05:59:41 PM PDT 24
Peak memory 202028 kb
Host smart-a4eca2f2-b8f2-40c4-9fe6-4c870275acc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208008152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3208008152
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1127703017
Short name T399
Test name
Test status
Simulation time 9484706667 ps
CPU time 22.87 seconds
Started Jun 24 05:59:35 PM PDT 24
Finished Jun 24 05:59:59 PM PDT 24
Peak memory 201952 kb
Host smart-b171e964-9718-42d5-a165-5de8e65872c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127703017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1127703017
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3783100921
Short name T35
Test name
Test status
Simulation time 532120936 ps
CPU time 0.94 seconds
Started Jun 24 05:59:43 PM PDT 24
Finished Jun 24 05:59:44 PM PDT 24
Peak memory 201900 kb
Host smart-fa288a96-6834-46df-8c4a-f21f47f46302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783100921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3783100921
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.4061005245
Short name T6
Test name
Test status
Simulation time 332141265124 ps
CPU time 180.06 seconds
Started Jun 24 05:59:43 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 202252 kb
Host smart-575a98ec-5722-4907-93dc-3407d7c20d20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061005245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.4061005245
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1748202299
Short name T573
Test name
Test status
Simulation time 492778300759 ps
CPU time 273.24 seconds
Started Jun 24 05:59:35 PM PDT 24
Finished Jun 24 06:04:09 PM PDT 24
Peak memory 202276 kb
Host smart-80ce458c-bd38-435e-80ba-e6cc27b2f745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748202299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1748202299
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1414318959
Short name T443
Test name
Test status
Simulation time 161921666121 ps
CPU time 68.71 seconds
Started Jun 24 05:59:34 PM PDT 24
Finished Jun 24 06:00:43 PM PDT 24
Peak memory 202152 kb
Host smart-690abc35-17eb-4620-9a4b-b859927920e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414318959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1414318959
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3669218574
Short name T421
Test name
Test status
Simulation time 161674508381 ps
CPU time 21.98 seconds
Started Jun 24 05:59:34 PM PDT 24
Finished Jun 24 05:59:56 PM PDT 24
Peak memory 202264 kb
Host smart-37c4fca3-9f7b-44b2-be19-953d4729b1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669218574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3669218574
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2366249207
Short name T188
Test name
Test status
Simulation time 336694858493 ps
CPU time 202.91 seconds
Started Jun 24 05:59:35 PM PDT 24
Finished Jun 24 06:02:58 PM PDT 24
Peak memory 202172 kb
Host smart-f7c9c72d-50e7-45d8-8d02-7a3bd67908b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366249207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2366249207
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3550897082
Short name T725
Test name
Test status
Simulation time 160805623932 ps
CPU time 95.81 seconds
Started Jun 24 05:59:35 PM PDT 24
Finished Jun 24 06:01:12 PM PDT 24
Peak memory 202240 kb
Host smart-95968112-53a7-42f4-89a5-9d7294f61f32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550897082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3550897082
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2060209798
Short name T389
Test name
Test status
Simulation time 211277300197 ps
CPU time 131.08 seconds
Started Jun 24 05:59:40 PM PDT 24
Finished Jun 24 06:01:51 PM PDT 24
Peak memory 202176 kb
Host smart-8884518b-2f53-4623-b1d5-9f052735a65b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060209798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2060209798
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.449564855
Short name T53
Test name
Test status
Simulation time 103293721157 ps
CPU time 342.38 seconds
Started Jun 24 05:59:47 PM PDT 24
Finished Jun 24 06:05:30 PM PDT 24
Peak memory 202576 kb
Host smart-91d9b9ed-985a-4281-85d7-8d0a1c3b8dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449564855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.449564855
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.813443851
Short name T588
Test name
Test status
Simulation time 31701842403 ps
CPU time 10.29 seconds
Started Jun 24 05:59:43 PM PDT 24
Finished Jun 24 05:59:54 PM PDT 24
Peak memory 202020 kb
Host smart-52565413-1064-4a16-bc05-153450ed497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813443851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.813443851
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.198959482
Short name T445
Test name
Test status
Simulation time 4835769780 ps
CPU time 10.49 seconds
Started Jun 24 05:59:42 PM PDT 24
Finished Jun 24 05:59:53 PM PDT 24
Peak memory 202008 kb
Host smart-40b9e286-5712-4409-89de-c0d1f7e870ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198959482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.198959482
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2871862124
Short name T423
Test name
Test status
Simulation time 5675486019 ps
CPU time 14.17 seconds
Started Jun 24 05:59:33 PM PDT 24
Finished Jun 24 05:59:48 PM PDT 24
Peak memory 202024 kb
Host smart-c8e13e36-c098-4fc3-be55-e93a74bf7f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871862124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2871862124
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.698335334
Short name T339
Test name
Test status
Simulation time 130768977475 ps
CPU time 336.6 seconds
Started Jun 24 05:59:46 PM PDT 24
Finished Jun 24 06:05:23 PM PDT 24
Peak memory 218288 kb
Host smart-d16cc7c8-39bc-43b0-937f-a233be6fe0ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698335334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
698335334
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3713671945
Short name T22
Test name
Test status
Simulation time 394919529172 ps
CPU time 256.42 seconds
Started Jun 24 05:59:43 PM PDT 24
Finished Jun 24 06:04:00 PM PDT 24
Peak memory 210552 kb
Host smart-15719af4-0c5d-46b4-9675-13549630e3dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713671945 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3713671945
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2772572109
Short name T385
Test name
Test status
Simulation time 514656331 ps
CPU time 1.71 seconds
Started Jun 24 06:00:02 PM PDT 24
Finished Jun 24 06:00:05 PM PDT 24
Peak memory 201924 kb
Host smart-e85ed3da-9017-4ef1-950b-f7ebaff780ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772572109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2772572109
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.667707355
Short name T119
Test name
Test status
Simulation time 498660612958 ps
CPU time 311.23 seconds
Started Jun 24 05:59:52 PM PDT 24
Finished Jun 24 06:05:04 PM PDT 24
Peak memory 202200 kb
Host smart-7f322924-a85a-492e-b9b8-841bcbdb8728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667707355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.667707355
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3292275636
Short name T693
Test name
Test status
Simulation time 334151784668 ps
CPU time 699.68 seconds
Started Jun 24 05:59:52 PM PDT 24
Finished Jun 24 06:11:32 PM PDT 24
Peak memory 202236 kb
Host smart-081890ff-be84-44f1-9d5a-b96d4c441d76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292275636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3292275636
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2396829530
Short name T26
Test name
Test status
Simulation time 161907395077 ps
CPU time 39.76 seconds
Started Jun 24 05:59:43 PM PDT 24
Finished Jun 24 06:00:23 PM PDT 24
Peak memory 202512 kb
Host smart-98d9cdfb-312b-48e1-aca9-41fe30a5f26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396829530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2396829530
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2121706264
Short name T742
Test name
Test status
Simulation time 322855633799 ps
CPU time 204.35 seconds
Started Jun 24 05:59:51 PM PDT 24
Finished Jun 24 06:03:16 PM PDT 24
Peak memory 202180 kb
Host smart-d666604b-701b-43ff-9fd6-e08ff9ca74ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121706264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2121706264
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2524328120
Short name T231
Test name
Test status
Simulation time 188207380249 ps
CPU time 212.52 seconds
Started Jun 24 05:59:52 PM PDT 24
Finished Jun 24 06:03:25 PM PDT 24
Peak memory 202196 kb
Host smart-680a3403-deed-401a-95ac-69283721cb73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524328120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2524328120
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2369204511
Short name T484
Test name
Test status
Simulation time 598733606562 ps
CPU time 633.33 seconds
Started Jun 24 05:59:53 PM PDT 24
Finished Jun 24 06:10:27 PM PDT 24
Peak memory 202188 kb
Host smart-757937e4-92ba-4cb2-a263-c7772df18d82
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369204511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2369204511
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3625234423
Short name T441
Test name
Test status
Simulation time 88451940175 ps
CPU time 489.75 seconds
Started Jun 24 06:00:02 PM PDT 24
Finished Jun 24 06:08:13 PM PDT 24
Peak memory 202524 kb
Host smart-9228d11e-070d-46cb-b604-21712f7c2bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625234423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3625234423
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3361681395
Short name T374
Test name
Test status
Simulation time 31435643557 ps
CPU time 38.01 seconds
Started Jun 24 06:00:01 PM PDT 24
Finished Jun 24 06:00:40 PM PDT 24
Peak memory 202032 kb
Host smart-4de6207b-7980-4ae1-bda8-cf4d6a2a0af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361681395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3361681395
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4282921163
Short name T758
Test name
Test status
Simulation time 5223209903 ps
CPU time 4.13 seconds
Started Jun 24 06:00:02 PM PDT 24
Finished Jun 24 06:00:07 PM PDT 24
Peak memory 202008 kb
Host smart-bf454393-a4ac-4104-9295-474f58e1b25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282921163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4282921163
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3786375028
Short name T614
Test name
Test status
Simulation time 6009941419 ps
CPU time 3.69 seconds
Started Jun 24 05:59:46 PM PDT 24
Finished Jun 24 05:59:50 PM PDT 24
Peak memory 202012 kb
Host smart-fa93e839-b703-4ee9-b3a3-3437648a290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786375028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3786375028
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2343164106
Short name T18
Test name
Test status
Simulation time 134530988878 ps
CPU time 93.44 seconds
Started Jun 24 06:00:03 PM PDT 24
Finished Jun 24 06:01:37 PM PDT 24
Peak memory 210572 kb
Host smart-0315697a-72a3-4f9d-8a56-9dc2d45c8504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343164106 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2343164106
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2563115085
Short name T359
Test name
Test status
Simulation time 345614950 ps
CPU time 0.96 seconds
Started Jun 24 06:00:11 PM PDT 24
Finished Jun 24 06:00:12 PM PDT 24
Peak memory 201904 kb
Host smart-80a848c2-8f51-4e85-ae45-240ecc5bb51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563115085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2563115085
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.672582601
Short name T274
Test name
Test status
Simulation time 173097049265 ps
CPU time 212.7 seconds
Started Jun 24 06:00:00 PM PDT 24
Finished Jun 24 06:03:34 PM PDT 24
Peak memory 202208 kb
Host smart-abdb8b46-5ebf-494a-9599-404cdf6d7555
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672582601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.672582601
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3440651445
Short name T313
Test name
Test status
Simulation time 484620146906 ps
CPU time 1134.95 seconds
Started Jun 24 06:00:01 PM PDT 24
Finished Jun 24 06:18:57 PM PDT 24
Peak memory 202252 kb
Host smart-45f62917-a85f-4b89-848b-e3998e78f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440651445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3440651445
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3435763860
Short name T583
Test name
Test status
Simulation time 488317130809 ps
CPU time 1178.86 seconds
Started Jun 24 06:00:01 PM PDT 24
Finished Jun 24 06:19:41 PM PDT 24
Peak memory 202144 kb
Host smart-86aa3779-baca-45cd-ac79-b163eb69c02f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435763860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3435763860
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2868036599
Short name T257
Test name
Test status
Simulation time 334940085326 ps
CPU time 395.28 seconds
Started Jun 24 06:00:03 PM PDT 24
Finished Jun 24 06:06:39 PM PDT 24
Peak memory 202200 kb
Host smart-c531127e-9406-4af8-bd5a-4c96b4393567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868036599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2868036599
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2919404732
Short name T763
Test name
Test status
Simulation time 336007405808 ps
CPU time 158.02 seconds
Started Jun 24 06:00:02 PM PDT 24
Finished Jun 24 06:02:41 PM PDT 24
Peak memory 202164 kb
Host smart-0881ddc9-5cec-461b-b998-27f4ae75c52d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919404732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2919404732
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.609324818
Short name T400
Test name
Test status
Simulation time 399431270129 ps
CPU time 846.87 seconds
Started Jun 24 06:00:01 PM PDT 24
Finished Jun 24 06:14:09 PM PDT 24
Peak memory 202176 kb
Host smart-b1244670-1083-4e70-8705-87ec4ee808c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609324818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.609324818
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4171170459
Short name T335
Test name
Test status
Simulation time 66886849123 ps
CPU time 248.36 seconds
Started Jun 24 06:00:01 PM PDT 24
Finished Jun 24 06:04:10 PM PDT 24
Peak memory 202588 kb
Host smart-ca6f33b2-7d86-448a-a335-8812211611cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171170459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4171170459
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1018171111
Short name T749
Test name
Test status
Simulation time 39213859059 ps
CPU time 23.24 seconds
Started Jun 24 06:00:08 PM PDT 24
Finished Jun 24 06:00:31 PM PDT 24
Peak memory 202020 kb
Host smart-43499041-9821-49e5-86f3-185c00051cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018171111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1018171111
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1300755096
Short name T356
Test name
Test status
Simulation time 3595352608 ps
CPU time 9.05 seconds
Started Jun 24 06:00:01 PM PDT 24
Finished Jun 24 06:00:11 PM PDT 24
Peak memory 202016 kb
Host smart-b929042e-eb18-48e7-a952-959a7537f1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300755096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1300755096
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.398225170
Short name T424
Test name
Test status
Simulation time 5919972824 ps
CPU time 13.42 seconds
Started Jun 24 06:00:02 PM PDT 24
Finished Jun 24 06:00:17 PM PDT 24
Peak memory 202012 kb
Host smart-9d3a7368-1a04-4967-a452-2e3c6ed6b4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398225170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.398225170
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2702419333
Short name T637
Test name
Test status
Simulation time 359348742758 ps
CPU time 824.18 seconds
Started Jun 24 06:00:11 PM PDT 24
Finished Jun 24 06:13:56 PM PDT 24
Peak memory 202112 kb
Host smart-71a8ae6e-ec41-4c3e-9ebc-068784f3f3d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702419333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2702419333
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2479713736
Short name T265
Test name
Test status
Simulation time 565337909233 ps
CPU time 190.33 seconds
Started Jun 24 06:00:01 PM PDT 24
Finished Jun 24 06:03:13 PM PDT 24
Peak memory 210520 kb
Host smart-3c132d78-df23-4b2a-8548-bbf6527a9f80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479713736 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2479713736
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2347799166
Short name T376
Test name
Test status
Simulation time 500294424 ps
CPU time 1.18 seconds
Started Jun 24 06:00:18 PM PDT 24
Finished Jun 24 06:00:19 PM PDT 24
Peak memory 201920 kb
Host smart-9679e833-7cd8-4be9-a625-8cf684707699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347799166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2347799166
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2571628245
Short name T465
Test name
Test status
Simulation time 170184002303 ps
CPU time 207.79 seconds
Started Jun 24 06:00:10 PM PDT 24
Finished Jun 24 06:03:39 PM PDT 24
Peak memory 202308 kb
Host smart-cb3a28e4-a285-4178-acb9-cc1aa0c7f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571628245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2571628245
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.702323188
Short name T497
Test name
Test status
Simulation time 168813965001 ps
CPU time 61.54 seconds
Started Jun 24 06:00:12 PM PDT 24
Finished Jun 24 06:01:14 PM PDT 24
Peak memory 202096 kb
Host smart-091ec7e1-2178-4a79-ae44-b243b0993700
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=702323188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.702323188
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2426797677
Short name T651
Test name
Test status
Simulation time 491622010148 ps
CPU time 533.57 seconds
Started Jun 24 06:00:10 PM PDT 24
Finished Jun 24 06:09:04 PM PDT 24
Peak memory 202272 kb
Host smart-03d2cf95-e0cd-493f-bd48-681d7b101bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426797677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2426797677
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2691851779
Short name T4
Test name
Test status
Simulation time 163594653137 ps
CPU time 97.17 seconds
Started Jun 24 06:00:10 PM PDT 24
Finished Jun 24 06:01:48 PM PDT 24
Peak memory 202200 kb
Host smart-0cf1773c-8a51-4255-a58f-b94ba422aec9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691851779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2691851779
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1880535946
Short name T308
Test name
Test status
Simulation time 598780590830 ps
CPU time 1328.34 seconds
Started Jun 24 06:00:11 PM PDT 24
Finished Jun 24 06:22:20 PM PDT 24
Peak memory 202276 kb
Host smart-b7997362-c6d6-4ba7-9024-6f4d8054fe22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880535946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1880535946
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.4090386054
Short name T189
Test name
Test status
Simulation time 196375818798 ps
CPU time 468.57 seconds
Started Jun 24 06:00:09 PM PDT 24
Finished Jun 24 06:07:58 PM PDT 24
Peak memory 202160 kb
Host smart-f16bd70d-2510-4979-81b2-003d3b2b2d2e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090386054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.4090386054
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2410151033
Short name T717
Test name
Test status
Simulation time 70332063875 ps
CPU time 257.79 seconds
Started Jun 24 06:00:17 PM PDT 24
Finished Jun 24 06:04:35 PM PDT 24
Peak memory 202512 kb
Host smart-e7705eef-028d-4c3a-ae6c-2ce54bc86423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410151033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2410151033
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3062423833
Short name T366
Test name
Test status
Simulation time 26474397730 ps
CPU time 17.28 seconds
Started Jun 24 06:00:17 PM PDT 24
Finished Jun 24 06:00:35 PM PDT 24
Peak memory 202056 kb
Host smart-db6c0599-0a7e-4ba2-86f1-c7b9c44551e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062423833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3062423833
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3771937853
Short name T386
Test name
Test status
Simulation time 2836795649 ps
CPU time 2.26 seconds
Started Jun 24 06:00:09 PM PDT 24
Finished Jun 24 06:00:12 PM PDT 24
Peak memory 202028 kb
Host smart-7ed1231b-2418-4669-bc34-351d85a4ea8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771937853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3771937853
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3403765725
Short name T751
Test name
Test status
Simulation time 5635468645 ps
CPU time 3.41 seconds
Started Jun 24 06:00:10 PM PDT 24
Finished Jun 24 06:00:14 PM PDT 24
Peak memory 201992 kb
Host smart-cff7bd5e-52d6-45a1-910c-f049d54b7e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403765725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3403765725
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.4221719013
Short name T34
Test name
Test status
Simulation time 297836740961 ps
CPU time 1083.15 seconds
Started Jun 24 06:00:45 PM PDT 24
Finished Jun 24 06:18:49 PM PDT 24
Peak memory 210692 kb
Host smart-1c7d45d5-68c5-4d21-b155-866a04f3a559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221719013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.4221719013
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1224320149
Short name T694
Test name
Test status
Simulation time 62880289613 ps
CPU time 104.47 seconds
Started Jun 24 06:00:19 PM PDT 24
Finished Jun 24 06:02:04 PM PDT 24
Peak memory 202596 kb
Host smart-88a1fdba-ac1d-4297-873e-ae275768134d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224320149 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1224320149
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.977610309
Short name T662
Test name
Test status
Simulation time 451021995 ps
CPU time 0.72 seconds
Started Jun 24 06:00:27 PM PDT 24
Finished Jun 24 06:00:29 PM PDT 24
Peak memory 201904 kb
Host smart-ed8de7d6-d623-48a6-af34-8ffe12b1c467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977610309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.977610309
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2550825136
Short name T99
Test name
Test status
Simulation time 445232109054 ps
CPU time 774.34 seconds
Started Jun 24 06:00:17 PM PDT 24
Finished Jun 24 06:13:12 PM PDT 24
Peak memory 202276 kb
Host smart-b72f4f10-af88-4924-8ecd-ee1b378848ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550825136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2550825136
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1784339005
Short name T293
Test name
Test status
Simulation time 331998978248 ps
CPU time 355.9 seconds
Started Jun 24 06:00:22 PM PDT 24
Finished Jun 24 06:06:18 PM PDT 24
Peak memory 202212 kb
Host smart-aee9e98d-74ca-4d3f-b72f-45d06f03b702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784339005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1784339005
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1281120503
Short name T259
Test name
Test status
Simulation time 330925541272 ps
CPU time 364.79 seconds
Started Jun 24 06:00:18 PM PDT 24
Finished Jun 24 06:06:24 PM PDT 24
Peak memory 202204 kb
Host smart-55fcb8d1-661a-4b23-966f-a7d019ff2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281120503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1281120503
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1612722768
Short name T620
Test name
Test status
Simulation time 167368168376 ps
CPU time 57.76 seconds
Started Jun 24 06:00:18 PM PDT 24
Finished Jun 24 06:01:17 PM PDT 24
Peak memory 202156 kb
Host smart-902e10f6-9641-47a8-a8c1-bb33cd731cc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612722768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1612722768
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1565535023
Short name T305
Test name
Test status
Simulation time 499873270497 ps
CPU time 1051.12 seconds
Started Jun 24 06:00:19 PM PDT 24
Finished Jun 24 06:17:51 PM PDT 24
Peak memory 202256 kb
Host smart-77b67854-aa48-4506-a48b-ac3b39859764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565535023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1565535023
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1459054475
Short name T406
Test name
Test status
Simulation time 329773241168 ps
CPU time 111.66 seconds
Started Jun 24 06:00:18 PM PDT 24
Finished Jun 24 06:02:11 PM PDT 24
Peak memory 202092 kb
Host smart-16d00f2a-325f-4bc3-b1d1-8d5208e7063c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459054475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1459054475
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.544274121
Short name T642
Test name
Test status
Simulation time 370773427232 ps
CPU time 458.34 seconds
Started Jun 24 06:00:19 PM PDT 24
Finished Jun 24 06:07:58 PM PDT 24
Peak memory 202188 kb
Host smart-afe7a4e1-7a3b-4b67-8c0f-0494f5869d8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544274121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.544274121
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3777873806
Short name T598
Test name
Test status
Simulation time 398021622265 ps
CPU time 265.21 seconds
Started Jun 24 06:00:18 PM PDT 24
Finished Jun 24 06:04:43 PM PDT 24
Peak memory 202256 kb
Host smart-894466c1-403d-4588-a8ba-17ee9bf2ddb4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777873806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3777873806
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1243326861
Short name T100
Test name
Test status
Simulation time 79006949482 ps
CPU time 344.62 seconds
Started Jun 24 06:00:29 PM PDT 24
Finished Jun 24 06:06:14 PM PDT 24
Peak memory 202576 kb
Host smart-3940e869-7d74-454e-b9e3-1a14734d8202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243326861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1243326861
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2340364051
Short name T755
Test name
Test status
Simulation time 29359454826 ps
CPU time 10.26 seconds
Started Jun 24 06:00:28 PM PDT 24
Finished Jun 24 06:00:39 PM PDT 24
Peak memory 201976 kb
Host smart-4b7a3fef-a357-4e35-b9bd-bd19b9cbca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340364051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2340364051
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3866410089
Short name T498
Test name
Test status
Simulation time 4754895477 ps
CPU time 12.31 seconds
Started Jun 24 06:00:27 PM PDT 24
Finished Jun 24 06:00:39 PM PDT 24
Peak memory 201972 kb
Host smart-f9606a6f-6746-4a33-9a2d-1bb88a36aab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866410089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3866410089
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.506338573
Short name T341
Test name
Test status
Simulation time 5530176525 ps
CPU time 4.06 seconds
Started Jun 24 06:00:18 PM PDT 24
Finished Jun 24 06:00:23 PM PDT 24
Peak memory 202028 kb
Host smart-d6816515-9d91-4370-8c91-eb125e194f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506338573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.506338573
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.712811944
Short name T766
Test name
Test status
Simulation time 91945421801 ps
CPU time 480.49 seconds
Started Jun 24 06:00:27 PM PDT 24
Finished Jun 24 06:08:28 PM PDT 24
Peak memory 210708 kb
Host smart-16b6788a-f1ea-43cf-ba16-552ebec111d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712811944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
712811944
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1136771743
Short name T658
Test name
Test status
Simulation time 152167892447 ps
CPU time 165.89 seconds
Started Jun 24 06:00:29 PM PDT 24
Finished Jun 24 06:03:15 PM PDT 24
Peak memory 210600 kb
Host smart-0927264d-358f-46da-8f9c-2de8e3a4a733
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136771743 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1136771743
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3710142297
Short name T525
Test name
Test status
Simulation time 436537670 ps
CPU time 1.45 seconds
Started Jun 24 06:00:38 PM PDT 24
Finished Jun 24 06:00:40 PM PDT 24
Peak memory 201836 kb
Host smart-b50b547a-726f-487b-beeb-fa41ad18c48d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710142297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3710142297
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.652225639
Short name T279
Test name
Test status
Simulation time 175972431198 ps
CPU time 391.96 seconds
Started Jun 24 06:00:39 PM PDT 24
Finished Jun 24 06:07:12 PM PDT 24
Peak memory 202232 kb
Host smart-5d593ab8-cb73-4689-8cc9-8c91b19c203e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652225639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.652225639
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.799882102
Short name T280
Test name
Test status
Simulation time 178905231654 ps
CPU time 182.7 seconds
Started Jun 24 06:00:37 PM PDT 24
Finished Jun 24 06:03:40 PM PDT 24
Peak memory 202208 kb
Host smart-c1d3fa93-e9f8-45ad-a3a2-45e23c7b3c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799882102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.799882102
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1441091953
Short name T249
Test name
Test status
Simulation time 322389036265 ps
CPU time 753.72 seconds
Started Jun 24 06:00:30 PM PDT 24
Finished Jun 24 06:13:04 PM PDT 24
Peak memory 202288 kb
Host smart-5bbd152d-c4dc-4f24-ba82-8830940cb966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441091953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1441091953
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.4141352170
Short name T565
Test name
Test status
Simulation time 163300361238 ps
CPU time 97.79 seconds
Started Jun 24 06:00:27 PM PDT 24
Finished Jun 24 06:02:05 PM PDT 24
Peak memory 202232 kb
Host smart-3b7aafff-da5e-428d-ac02-65436b66df03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141352170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.4141352170
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1095865432
Short name T720
Test name
Test status
Simulation time 166642334944 ps
CPU time 351.15 seconds
Started Jun 24 06:00:28 PM PDT 24
Finished Jun 24 06:06:20 PM PDT 24
Peak memory 202208 kb
Host smart-41566cc7-d6e3-474a-a735-24f66971130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095865432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1095865432
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1470473524
Short name T591
Test name
Test status
Simulation time 330222806381 ps
CPU time 643.51 seconds
Started Jun 24 06:00:28 PM PDT 24
Finished Jun 24 06:11:12 PM PDT 24
Peak memory 202172 kb
Host smart-5c2b20cd-5035-4396-8916-11a7995c4736
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470473524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1470473524
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4254255096
Short name T149
Test name
Test status
Simulation time 357655871923 ps
CPU time 425.69 seconds
Started Jun 24 06:00:28 PM PDT 24
Finished Jun 24 06:07:34 PM PDT 24
Peak memory 202272 kb
Host smart-901aaa77-44f4-4e45-a711-369c97e2b39b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254255096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4254255096
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.133246965
Short name T764
Test name
Test status
Simulation time 587169908203 ps
CPU time 250.94 seconds
Started Jun 24 06:00:29 PM PDT 24
Finished Jun 24 06:04:41 PM PDT 24
Peak memory 202256 kb
Host smart-f2e2ca49-7b8a-4c84-b7f0-c19ffe43fc74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133246965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.133246965
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1970860406
Short name T512
Test name
Test status
Simulation time 85130366724 ps
CPU time 328.91 seconds
Started Jun 24 06:00:38 PM PDT 24
Finished Jun 24 06:06:08 PM PDT 24
Peak memory 202508 kb
Host smart-c17ecf6c-a288-43a8-a9fe-510d29121c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970860406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1970860406
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3370411885
Short name T655
Test name
Test status
Simulation time 24737998431 ps
CPU time 14.32 seconds
Started Jun 24 06:00:36 PM PDT 24
Finished Jun 24 06:00:51 PM PDT 24
Peak memory 201996 kb
Host smart-850b1c73-858b-4a3c-94ee-99e3f7fb9acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370411885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3370411885
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3289402454
Short name T345
Test name
Test status
Simulation time 4590136845 ps
CPU time 1.73 seconds
Started Jun 24 06:00:37 PM PDT 24
Finished Jun 24 06:00:40 PM PDT 24
Peak memory 202016 kb
Host smart-d0d4c793-24e8-4d19-90ca-5ef68add57a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289402454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3289402454
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4175525826
Short name T543
Test name
Test status
Simulation time 5994779862 ps
CPU time 13.79 seconds
Started Jun 24 06:00:30 PM PDT 24
Finished Jun 24 06:00:44 PM PDT 24
Peak memory 202012 kb
Host smart-d7f70338-69f5-4a92-bd2f-713425215d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175525826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4175525826
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1209893028
Short name T45
Test name
Test status
Simulation time 61290347838 ps
CPU time 120.36 seconds
Started Jun 24 06:00:37 PM PDT 24
Finished Jun 24 06:02:38 PM PDT 24
Peak memory 210924 kb
Host smart-483f5cdc-c86b-48ff-aa81-6257be329125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209893028 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1209893028
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3221740431
Short name T545
Test name
Test status
Simulation time 552327482 ps
CPU time 0.91 seconds
Started Jun 24 05:55:20 PM PDT 24
Finished Jun 24 05:55:22 PM PDT 24
Peak memory 201900 kb
Host smart-44509353-a12c-4ba9-9cd4-ac45f715cf4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221740431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3221740431
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1119432283
Short name T674
Test name
Test status
Simulation time 170799165563 ps
CPU time 89.16 seconds
Started Jun 24 05:55:23 PM PDT 24
Finished Jun 24 05:56:54 PM PDT 24
Peak memory 202192 kb
Host smart-5706cd88-7282-4212-aeba-5ab2e94de032
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119432283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1119432283
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1246392745
Short name T414
Test name
Test status
Simulation time 245494006621 ps
CPU time 574.97 seconds
Started Jun 24 05:55:18 PM PDT 24
Finished Jun 24 06:04:54 PM PDT 24
Peak memory 202200 kb
Host smart-8f3632a8-46c2-4a84-939b-64018d5c3477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246392745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1246392745
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.212832578
Short name T708
Test name
Test status
Simulation time 325312824564 ps
CPU time 199.49 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 05:58:42 PM PDT 24
Peak memory 202520 kb
Host smart-75a52f24-9683-4ab6-9fb4-46e3cb85bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212832578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.212832578
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.138608228
Short name T567
Test name
Test status
Simulation time 330498508833 ps
CPU time 159.2 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 05:58:02 PM PDT 24
Peak memory 202236 kb
Host smart-6c6a4466-24cf-40c9-81a4-dbcf703532be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=138608228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.138608228
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1454746578
Short name T208
Test name
Test status
Simulation time 329454592013 ps
CPU time 184.02 seconds
Started Jun 24 05:55:22 PM PDT 24
Finished Jun 24 05:58:28 PM PDT 24
Peak memory 202172 kb
Host smart-2f7c8ff8-fad0-403a-b6f3-c568cabec07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454746578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1454746578
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3909015286
Short name T449
Test name
Test status
Simulation time 494066132986 ps
CPU time 1102.04 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 06:13:45 PM PDT 24
Peak memory 202180 kb
Host smart-addaa059-5481-4f92-9cd7-e88a3fb8d0ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909015286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3909015286
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3275602283
Short name T187
Test name
Test status
Simulation time 543471199981 ps
CPU time 320.82 seconds
Started Jun 24 05:55:23 PM PDT 24
Finished Jun 24 06:00:46 PM PDT 24
Peak memory 202152 kb
Host smart-a846e3c7-fbf9-4a46-b82d-3df25ca890da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275602283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3275602283
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2356018711
Short name T539
Test name
Test status
Simulation time 197433603244 ps
CPU time 457.69 seconds
Started Jun 24 05:55:22 PM PDT 24
Finished Jun 24 06:03:02 PM PDT 24
Peak memory 202180 kb
Host smart-890c2a55-ae6f-4397-9bb6-ce589a3eb92a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356018711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2356018711
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.959840501
Short name T606
Test name
Test status
Simulation time 78805080550 ps
CPU time 270.98 seconds
Started Jun 24 05:55:22 PM PDT 24
Finished Jun 24 05:59:55 PM PDT 24
Peak memory 202572 kb
Host smart-189c979f-6e2e-44c7-88bd-32783de84f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959840501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.959840501
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1386379208
Short name T466
Test name
Test status
Simulation time 33709010650 ps
CPU time 73.09 seconds
Started Jun 24 05:55:23 PM PDT 24
Finished Jun 24 05:56:38 PM PDT 24
Peak memory 202000 kb
Host smart-f6681c91-bbbf-4526-b496-4b3ae6424b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386379208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1386379208
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2053563480
Short name T128
Test name
Test status
Simulation time 5221969894 ps
CPU time 11.28 seconds
Started Jun 24 05:55:20 PM PDT 24
Finished Jun 24 05:55:32 PM PDT 24
Peak memory 201940 kb
Host smart-faa3f490-1929-4070-80c0-c9cc5e973e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053563480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2053563480
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2315492213
Short name T405
Test name
Test status
Simulation time 5717141868 ps
CPU time 3.83 seconds
Started Jun 24 05:55:22 PM PDT 24
Finished Jun 24 05:55:28 PM PDT 24
Peak memory 202020 kb
Host smart-cea82a81-0824-4cfd-a2f8-fe5d28ff0883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315492213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2315492213
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1366906708
Short name T679
Test name
Test status
Simulation time 220374763068 ps
CPU time 246.99 seconds
Started Jun 24 05:55:19 PM PDT 24
Finished Jun 24 05:59:27 PM PDT 24
Peak memory 202192 kb
Host smart-5b558108-6167-4ad4-864a-ab652c94a1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366906708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1366906708
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2037188113
Short name T770
Test name
Test status
Simulation time 581875715092 ps
CPU time 114.9 seconds
Started Jun 24 05:55:23 PM PDT 24
Finished Jun 24 05:57:20 PM PDT 24
Peak memory 210500 kb
Host smart-17950371-b67d-4e5f-9d8e-9eddc84504e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037188113 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2037188113
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3717630958
Short name T373
Test name
Test status
Simulation time 519768647 ps
CPU time 0.77 seconds
Started Jun 24 05:55:35 PM PDT 24
Finished Jun 24 05:55:37 PM PDT 24
Peak memory 201912 kb
Host smart-00e2aaeb-773e-4196-a8c6-940bf5e3adbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717630958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3717630958
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.421641206
Short name T124
Test name
Test status
Simulation time 164591642356 ps
CPU time 29.17 seconds
Started Jun 24 05:55:22 PM PDT 24
Finished Jun 24 05:55:53 PM PDT 24
Peak memory 202216 kb
Host smart-cb9e9f46-d16f-4457-a9c3-b15b494758c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421641206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.421641206
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2158388233
Short name T183
Test name
Test status
Simulation time 523932992650 ps
CPU time 1100.46 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 06:13:44 PM PDT 24
Peak memory 202220 kb
Host smart-f64c5dff-6c0a-43a6-b26c-8ffe5fc045f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158388233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2158388233
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1952418507
Short name T210
Test name
Test status
Simulation time 157511313247 ps
CPU time 377.47 seconds
Started Jun 24 05:55:22 PM PDT 24
Finished Jun 24 06:01:41 PM PDT 24
Peak memory 202296 kb
Host smart-34e52ab7-d500-41df-b54f-1fd7baa3c404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952418507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1952418507
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1540209625
Short name T125
Test name
Test status
Simulation time 159224035015 ps
CPU time 367.09 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 06:01:30 PM PDT 24
Peak memory 202484 kb
Host smart-9a720ba6-160f-4d27-b7cc-e3eca6247a41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540209625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1540209625
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1377648612
Short name T413
Test name
Test status
Simulation time 324173926286 ps
CPU time 367.23 seconds
Started Jun 24 05:55:20 PM PDT 24
Finished Jun 24 06:01:29 PM PDT 24
Peak memory 202204 kb
Host smart-a42c8248-137c-4373-81ad-63bf37f84ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377648612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1377648612
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3751798051
Short name T11
Test name
Test status
Simulation time 492545459197 ps
CPU time 1085.33 seconds
Started Jun 24 05:55:23 PM PDT 24
Finished Jun 24 06:13:30 PM PDT 24
Peak memory 202256 kb
Host smart-40511246-c3f1-499b-aafa-45f92bcbbb05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751798051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3751798051
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2797528768
Short name T548
Test name
Test status
Simulation time 551689772487 ps
CPU time 468.22 seconds
Started Jun 24 05:55:21 PM PDT 24
Finished Jun 24 06:03:11 PM PDT 24
Peak memory 202288 kb
Host smart-84cc313a-d73f-4df0-bef7-b3c074a46c51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797528768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2797528768
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2662377189
Short name T696
Test name
Test status
Simulation time 588225931803 ps
CPU time 1251.88 seconds
Started Jun 24 05:55:20 PM PDT 24
Finished Jun 24 06:16:13 PM PDT 24
Peak memory 202192 kb
Host smart-913faf45-5609-4bed-95f5-149e2eea9f55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662377189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2662377189
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.210982640
Short name T534
Test name
Test status
Simulation time 113045319672 ps
CPU time 548.61 seconds
Started Jun 24 05:55:33 PM PDT 24
Finished Jun 24 06:04:43 PM PDT 24
Peak memory 202428 kb
Host smart-bfb7f201-9e1c-4245-bac2-b118be987b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210982640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.210982640
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1956768138
Short name T738
Test name
Test status
Simulation time 26076137252 ps
CPU time 31.34 seconds
Started Jun 24 05:55:28 PM PDT 24
Finished Jun 24 05:56:00 PM PDT 24
Peak memory 202020 kb
Host smart-53bce909-e255-4492-ae5e-df2619f7e946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956768138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1956768138
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.479110651
Short name T475
Test name
Test status
Simulation time 4191476400 ps
CPU time 3.06 seconds
Started Jun 24 05:55:23 PM PDT 24
Finished Jun 24 05:55:28 PM PDT 24
Peak memory 202036 kb
Host smart-b9d4ba60-879f-40fe-8f5e-e81d6bb7315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479110651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.479110651
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.798284437
Short name T106
Test name
Test status
Simulation time 5704775023 ps
CPU time 4.39 seconds
Started Jun 24 05:55:19 PM PDT 24
Finished Jun 24 05:55:24 PM PDT 24
Peak memory 202036 kb
Host smart-4839a49e-4bbc-4ada-9534-526e99f40331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798284437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.798284437
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1685049845
Short name T483
Test name
Test status
Simulation time 48930808855 ps
CPU time 102.65 seconds
Started Jun 24 05:55:30 PM PDT 24
Finished Jun 24 05:57:15 PM PDT 24
Peak memory 210596 kb
Host smart-a7252aa8-8371-4f76-a62f-850a14c93bfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685049845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1685049845
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1617665457
Short name T691
Test name
Test status
Simulation time 458830592 ps
CPU time 1.31 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:55:32 PM PDT 24
Peak memory 201896 kb
Host smart-62d9690c-0b02-4888-9f71-8395c2d4aa10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617665457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1617665457
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3375005468
Short name T568
Test name
Test status
Simulation time 202685814097 ps
CPU time 237.2 seconds
Started Jun 24 05:55:35 PM PDT 24
Finished Jun 24 05:59:33 PM PDT 24
Peak memory 202172 kb
Host smart-1687760a-e0dd-4adc-9a4b-5bc45c85e6e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375005468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3375005468
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.89208347
Short name T619
Test name
Test status
Simulation time 355731582666 ps
CPU time 847.34 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 06:09:39 PM PDT 24
Peak memory 202212 kb
Host smart-13947e11-d70a-44a5-a38e-a6b27928d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89208347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.89208347
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.4011297290
Short name T31
Test name
Test status
Simulation time 162851416921 ps
CPU time 99.12 seconds
Started Jun 24 05:55:35 PM PDT 24
Finished Jun 24 05:57:15 PM PDT 24
Peak memory 202188 kb
Host smart-23bf6ddc-854a-4662-ab27-64b24ee2e577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011297290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.4011297290
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2057499293
Short name T232
Test name
Test status
Simulation time 492124125076 ps
CPU time 614.5 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 06:05:47 PM PDT 24
Peak memory 202168 kb
Host smart-c31e0da0-8143-428d-97c2-493e634fd5d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057499293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2057499293
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3311977381
Short name T277
Test name
Test status
Simulation time 167267925902 ps
CPU time 411.76 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 06:02:24 PM PDT 24
Peak memory 202248 kb
Host smart-82221ed1-cdf7-451e-9809-624d4326e9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311977381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3311977381
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.388824179
Short name T646
Test name
Test status
Simulation time 489903821812 ps
CPU time 1165.2 seconds
Started Jun 24 05:55:36 PM PDT 24
Finished Jun 24 06:15:02 PM PDT 24
Peak memory 202360 kb
Host smart-6def927b-dad4-4cdf-867b-38a43cf4002e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=388824179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.388824179
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1506376717
Short name T526
Test name
Test status
Simulation time 419810312000 ps
CPU time 224.23 seconds
Started Jun 24 05:55:32 PM PDT 24
Finished Jun 24 05:59:17 PM PDT 24
Peak memory 202288 kb
Host smart-3d547741-ae56-4e52-a2cc-ce86cfb5b511
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506376717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1506376717
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3815743559
Short name T420
Test name
Test status
Simulation time 619533256221 ps
CPU time 362.1 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 06:01:35 PM PDT 24
Peak memory 202236 kb
Host smart-42db03c4-dcfa-4b00-8e3b-c0c6f273ec00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815743559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3815743559
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.942595716
Short name T393
Test name
Test status
Simulation time 92384851834 ps
CPU time 472.56 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 06:03:24 PM PDT 24
Peak memory 202516 kb
Host smart-d09b125c-e321-4cb3-9466-4fe961a57e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942595716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.942595716
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3142656262
Short name T541
Test name
Test status
Simulation time 23200611381 ps
CPU time 14.74 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:55:45 PM PDT 24
Peak memory 202020 kb
Host smart-d95a787a-e7d5-445e-900a-0410a608e9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142656262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3142656262
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3798966985
Short name T467
Test name
Test status
Simulation time 3988939954 ps
CPU time 10.62 seconds
Started Jun 24 05:55:27 PM PDT 24
Finished Jun 24 05:55:39 PM PDT 24
Peak memory 202020 kb
Host smart-cd28b48a-d4fe-4037-b011-cb028ceef12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798966985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3798966985
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3597347518
Short name T105
Test name
Test status
Simulation time 5806637298 ps
CPU time 12.38 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:55:43 PM PDT 24
Peak memory 202000 kb
Host smart-2276d1c3-bba8-4d1d-ad21-2c8d3cad0d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597347518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3597347518
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.101529424
Short name T553
Test name
Test status
Simulation time 45979598493 ps
CPU time 112.56 seconds
Started Jun 24 05:55:34 PM PDT 24
Finished Jun 24 05:57:27 PM PDT 24
Peak memory 210824 kb
Host smart-b76ac4b0-503e-4faa-b3c7-84ca6a3d1c6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101529424 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.101529424
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4276068712
Short name T784
Test name
Test status
Simulation time 496816165 ps
CPU time 0.97 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:55:32 PM PDT 24
Peak memory 201872 kb
Host smart-e167e76c-9eec-4df5-adb6-19e6270943f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276068712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4276068712
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1905166268
Short name T201
Test name
Test status
Simulation time 508977927487 ps
CPU time 181.93 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:58:31 PM PDT 24
Peak memory 202252 kb
Host smart-ff84b8d7-3027-47bd-9123-119f6138272c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905166268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1905166268
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1257752088
Short name T182
Test name
Test status
Simulation time 541940435346 ps
CPU time 1161.25 seconds
Started Jun 24 05:55:30 PM PDT 24
Finished Jun 24 06:14:53 PM PDT 24
Peak memory 202128 kb
Host smart-be65375d-aaf8-4148-9b6a-c8af48bcdfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257752088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1257752088
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2141152541
Short name T415
Test name
Test status
Simulation time 333329089893 ps
CPU time 358.84 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 06:01:32 PM PDT 24
Peak memory 202248 kb
Host smart-6f93bd84-5bc7-460a-a137-24fd7e65ab8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141152541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2141152541
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2584136785
Short name T171
Test name
Test status
Simulation time 324748394612 ps
CPU time 774.12 seconds
Started Jun 24 05:55:33 PM PDT 24
Finished Jun 24 06:08:28 PM PDT 24
Peak memory 202268 kb
Host smart-1283573a-be72-4201-a989-7effac3091fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584136785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2584136785
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2442694058
Short name T492
Test name
Test status
Simulation time 325661389778 ps
CPU time 197.1 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:58:47 PM PDT 24
Peak memory 202244 kb
Host smart-823c87f7-2129-423b-a797-98290a6d2766
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442694058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2442694058
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.621027217
Short name T196
Test name
Test status
Simulation time 177762690760 ps
CPU time 205.07 seconds
Started Jun 24 05:55:30 PM PDT 24
Finished Jun 24 05:58:57 PM PDT 24
Peak memory 202104 kb
Host smart-65f38b4b-89fd-4e5e-b9d4-da0267d8b085
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621027217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.621027217
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3318016970
Short name T352
Test name
Test status
Simulation time 194494209193 ps
CPU time 232.19 seconds
Started Jun 24 05:55:30 PM PDT 24
Finished Jun 24 05:59:24 PM PDT 24
Peak memory 202224 kb
Host smart-c16a85b4-cb35-422d-9c48-b36bbd648362
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318016970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3318016970
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3403906829
Short name T537
Test name
Test status
Simulation time 121774885239 ps
CPU time 623.97 seconds
Started Jun 24 05:55:33 PM PDT 24
Finished Jun 24 06:05:58 PM PDT 24
Peak memory 202492 kb
Host smart-b37a795f-3fdd-450d-b14d-b0cff68aa003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403906829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3403906829
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3238625615
Short name T616
Test name
Test status
Simulation time 38961206784 ps
CPU time 42.95 seconds
Started Jun 24 05:55:36 PM PDT 24
Finished Jun 24 05:56:20 PM PDT 24
Peak memory 201952 kb
Host smart-a83286b5-dc3e-4171-b957-3a1e889e7f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238625615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3238625615
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.112291860
Short name T477
Test name
Test status
Simulation time 3503256530 ps
CPU time 8.46 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 05:55:41 PM PDT 24
Peak memory 202048 kb
Host smart-c56844f3-751e-421a-b0bb-6ec1842a9c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112291860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.112291860
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3141075484
Short name T174
Test name
Test status
Simulation time 5834398447 ps
CPU time 8.16 seconds
Started Jun 24 05:55:32 PM PDT 24
Finished Jun 24 05:55:41 PM PDT 24
Peak memory 202016 kb
Host smart-83ad313c-72ab-4670-a78a-61557b6ed803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141075484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3141075484
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2883446586
Short name T93
Test name
Test status
Simulation time 3767356305198 ps
CPU time 8352.52 seconds
Started Jun 24 05:55:36 PM PDT 24
Finished Jun 24 08:14:50 PM PDT 24
Peak memory 210900 kb
Host smart-f0dfa455-4553-4cef-8466-ca76c0172900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883446586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2883446586
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2473528423
Short name T542
Test name
Test status
Simulation time 25720273136 ps
CPU time 47.88 seconds
Started Jun 24 05:55:32 PM PDT 24
Finished Jun 24 05:56:22 PM PDT 24
Peak memory 210888 kb
Host smart-fecfc5dd-dbe8-4f3b-a057-4b545ab0ca94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473528423 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2473528423
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1519369791
Short name T613
Test name
Test status
Simulation time 357004298 ps
CPU time 0.98 seconds
Started Jun 24 05:55:28 PM PDT 24
Finished Jun 24 05:55:30 PM PDT 24
Peak memory 201896 kb
Host smart-09593dad-41f8-4889-ad2d-403278efd48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519369791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1519369791
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.246529874
Short name T299
Test name
Test status
Simulation time 166889944007 ps
CPU time 87.66 seconds
Started Jun 24 05:55:30 PM PDT 24
Finished Jun 24 05:57:00 PM PDT 24
Peak memory 202276 kb
Host smart-24321bba-56be-4a59-ad07-a3e977188edc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246529874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.246529874
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2059892700
Short name T601
Test name
Test status
Simulation time 332216874704 ps
CPU time 757.86 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 06:08:11 PM PDT 24
Peak memory 202228 kb
Host smart-c5bc9da3-ad0f-4a6d-9efa-42ba227e5c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059892700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2059892700
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.959279253
Short name T238
Test name
Test status
Simulation time 161358580932 ps
CPU time 177.19 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 05:58:30 PM PDT 24
Peak memory 202296 kb
Host smart-78b5fdeb-c2a3-45b0-95e4-f5016bb3927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959279253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.959279253
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3309565123
Short name T731
Test name
Test status
Simulation time 162052312823 ps
CPU time 170.52 seconds
Started Jun 24 05:55:33 PM PDT 24
Finished Jun 24 05:58:25 PM PDT 24
Peak memory 202168 kb
Host smart-4fe1e4cf-f402-44cf-bdaf-42b589a93c72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309565123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3309565123
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3308063634
Short name T436
Test name
Test status
Simulation time 159339544622 ps
CPU time 165.92 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 05:58:18 PM PDT 24
Peak memory 202200 kb
Host smart-bcc40274-5ed5-42a8-9d56-c87bbee17f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308063634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3308063634
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2620350615
Short name T558
Test name
Test status
Simulation time 333000492644 ps
CPU time 182.59 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:58:33 PM PDT 24
Peak memory 202256 kb
Host smart-049b1abb-fcdd-4ed6-9cb8-d0f6a505a750
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620350615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2620350615
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3507306613
Short name T665
Test name
Test status
Simulation time 618826969834 ps
CPU time 1416.12 seconds
Started Jun 24 05:55:27 PM PDT 24
Finished Jun 24 06:19:04 PM PDT 24
Peak memory 202196 kb
Host smart-368f5960-2a55-4165-95b8-c1111e511b6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507306613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3507306613
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2851982025
Short name T358
Test name
Test status
Simulation time 200717797147 ps
CPU time 111.16 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:57:22 PM PDT 24
Peak memory 202196 kb
Host smart-007b6292-969e-44bb-b98c-d7056510e4c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851982025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2851982025
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4185276427
Short name T635
Test name
Test status
Simulation time 103705707693 ps
CPU time 483.05 seconds
Started Jun 24 05:55:35 PM PDT 24
Finished Jun 24 06:03:39 PM PDT 24
Peak memory 202752 kb
Host smart-82b3c977-75ad-4b86-9d76-2e9f9937bb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185276427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4185276427
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2422583434
Short name T347
Test name
Test status
Simulation time 26206971972 ps
CPU time 63.5 seconds
Started Jun 24 05:55:29 PM PDT 24
Finished Jun 24 05:56:34 PM PDT 24
Peak memory 202016 kb
Host smart-0d5ab7f5-f136-49c1-b6ff-cce1ccee6ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422583434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2422583434
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4037364331
Short name T562
Test name
Test status
Simulation time 5357820471 ps
CPU time 10.42 seconds
Started Jun 24 05:55:30 PM PDT 24
Finished Jun 24 05:55:42 PM PDT 24
Peak memory 202020 kb
Host smart-cc87cc95-75a1-4392-8f2e-d1eaf20b446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037364331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4037364331
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1866185846
Short name T544
Test name
Test status
Simulation time 6021983324 ps
CPU time 14.74 seconds
Started Jun 24 05:55:31 PM PDT 24
Finished Jun 24 05:55:48 PM PDT 24
Peak memory 202016 kb
Host smart-76b2242e-2994-484a-9302-6e7bbc99b7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866185846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1866185846
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1174546964
Short name T56
Test name
Test status
Simulation time 184691390378 ps
CPU time 418.33 seconds
Started Jun 24 05:55:35 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 202528 kb
Host smart-389ff38a-0889-48dd-b6e4-55cadf6dc5f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174546964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1174546964
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2358655962
Short name T791
Test name
Test status
Simulation time 263038132786 ps
CPU time 55.52 seconds
Started Jun 24 05:55:34 PM PDT 24
Finished Jun 24 05:56:31 PM PDT 24
Peak memory 202248 kb
Host smart-bfa17ff4-b86d-4d7a-9783-a27b14318f96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358655962 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2358655962
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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