Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7087	1			T4	110		T6	49		T8	35
testmodes[AdcCtrlTestmodeNormal]	5537	1			T3	3		T4	69		T5	3
testmodes[AdcCtrlTestmodeLowpower]	5699	1			T1	2		T2	18		T4	62
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3937	1			T4	62		T6	15		T8	7
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1683	1			T4	21		T6	15		T8	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1357	1			T4	26		T6	19		T8	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1746	1			T4	25		T6	12		T8	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2056	1			T3	2		T4	23		T5	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1378	1			T4	21		T6	17		T8	8
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1295	1			T4	23		T6	22		T8	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1455	1			T4	24		T6	15		T8	10
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2717	1			T1	1		T2	17		T4	15